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1 /*
2 * QEMU TCG vCPU common functionality
3 *
4 * Functionality common to all TCG vCPU variants: mttcg, rr and icount.
5 *
6 * Copyright (c) 2003-2008 Fabrice Bellard
7 * Copyright (c) 2014 Red Hat Inc.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "accel/accel-ops.h"
30 #include "accel/accel-cpu-ops.h"
31 #include "accel/tcg/cpu-loop.h"
32 #include "system/tcg.h"
33 #include "system/replay.h"
34 #include "exec/icount.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/guest-random.h"
37 #include "qemu/timer.h"
38 #include "exec/cputlb.h"
39 #include "exec/hwaddr.h"
40 #include "exec/tb-flush.h"
41 #include "exec/translation-block.h"
42 #include "exec/watchpoint.h"
43 #include "gdbstub/enums.h"
44
45 #include "hw/core/cpu.h"
46
47 #include "tcg-accel-ops.h"
48 #include "tcg-accel-ops-mttcg.h"
49 #include "tcg-accel-ops-rr.h"
50 #include "tcg-accel-ops-icount.h"
51
52 /* common functionality among all TCG variants */
53
54 void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
55 {
56 uint32_t cflags;
57
58 /*
59 * Include the cluster number in the hash we use to look up TBs.
60 * This is important because a TB that is valid for one cluster at
61 * a given physical address and set of CPU flags is not necessarily
62 * valid for another:
63 * the two clusters may have different views of physical memory, or
64 * may have different CPU features (eg FPU present or absent).
65 */
66 cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
67
68 cflags |= parallel ? CF_PARALLEL : 0;
69 cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
70 tcg_cflags_set(cpu, cflags);
71 }
72
73 void tcg_cpu_destroy(CPUState *cpu)
74 {
75 cpu_thread_signal_destroyed(cpu);
76 }
77
78 int tcg_cpu_exec(CPUState *cpu)
79 {
80 int ret;
81 assert(tcg_enabled());
82 cpu_exec_start(cpu);
83 ret = cpu_exec(cpu);
84 cpu_exec_end(cpu);
85
86 return ret;
87 }
88
89 static void tcg_cpu_reset_hold(CPUState *cpu)
90 {
91 tcg_flush_jmp_cache(cpu);
92
93 tlb_flush(cpu);
94 }
95
96 /* mask must never be zero, except for A20 change call */
97 void tcg_handle_interrupt(CPUState *cpu, int mask)
98 {
99 cpu_set_interrupt(cpu, mask);
100
101 /*
102 * If called from iothread context, wake the target cpu in
103 * case its halted.
104 */
105 if (!qemu_cpu_is_self(cpu)) {
106 qemu_cpu_kick(cpu);
107 } else {
108 qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
109 }
110 }
111
112 /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */
113 static inline int xlat_gdb_type(CPUState *cpu, GdbBreakpointType gdbtype)
114 {
115 static const int xlat[] = {
116 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
117 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
118 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
119 };
120
121 int cputype = xlat[gdbtype];
122
123 if (cpu->cc->gdb_stop_before_watchpoint) {
124 cputype |= BP_STOP_BEFORE_ACCESS;
125 }
126 return cputype;
127 }
128
129 static int tcg_insert_gdbstub_breakpoint(CPUState *cs, GdbBreakpointType type,
130 vaddr addr, vaddr len)
131 {
132 CPUState *cpu;
133 int err = 0;
134
135 switch (type) {
136 case GDB_BREAKPOINT_SW:
137 case GDB_BREAKPOINT_HW:
138 CPU_FOREACH(cpu) {
139 err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL);
140 if (err) {
141 break;
142 }
143 }
144 return err;
145 case GDB_WATCHPOINT_WRITE:
146 case GDB_WATCHPOINT_READ:
147 case GDB_WATCHPOINT_ACCESS:
148 CPU_FOREACH(cpu) {
149 err = cpu_watchpoint_insert(cpu, addr, len,
150 xlat_gdb_type(cpu, type), NULL);
151 if (err) {
152 break;
153 }
154 }
155 return err;
156 default:
157 return -ENOSYS;
158 }
159 }
160
161 static int tcg_remove_gdbstub_breakpoint(CPUState *cs, GdbBreakpointType type,
162 vaddr addr, vaddr len)
163 {
164 CPUState *cpu;
165 int err = 0;
166
167 switch (type) {
168 case GDB_BREAKPOINT_SW:
169 case GDB_BREAKPOINT_HW:
170 CPU_FOREACH(cpu) {
171 err = cpu_breakpoint_remove(cpu, addr, BP_GDB);
172 if (err) {
173 break;
174 }
175 }
176 return err;
177 case GDB_WATCHPOINT_WRITE:
178 case GDB_WATCHPOINT_READ:
179 case GDB_WATCHPOINT_ACCESS:
180 CPU_FOREACH(cpu) {
181 err = cpu_watchpoint_remove(cpu, addr, len,
182 xlat_gdb_type(cpu, type));
183 if (err) {
184 break;
185 }
186 }
187 return err;
188 default:
189 return -ENOSYS;
190 }
191 }
192
193 static void tcg_remove_all_gdbstub_breakpoints(CPUState *cpu)
194 {
195 cpu_breakpoint_remove_all(cpu, BP_GDB);
196 cpu_watchpoint_remove_all(cpu, BP_GDB);
197 }
198
199 static void tcg_accel_ops_init(AccelClass *ac)
200 {
201 AccelOpsClass *ops = ac->ops;
202
203 if (qemu_tcg_mttcg_enabled()) {
204 ops->create_vcpu_thread = mttcg_start_vcpu_thread;
205 ops->kick_vcpu_thread = tcg_kick_vcpu_thread;
206 ops->handle_interrupt = tcg_handle_interrupt;
207 } else {
208 ops->create_vcpu_thread = rr_start_vcpu_thread;
209 ops->kick_vcpu_thread = rr_kick_vcpu_thread;
210
211 if (icount_enabled()) {
212 ops->handle_interrupt = icount_handle_interrupt;
213 ops->get_virtual_clock = icount_get;
214 ops->get_elapsed_ticks = icount_get;
215 } else {
216 ops->handle_interrupt = tcg_handle_interrupt;
217 }
218 }
219
220 ops->cpu_reset_hold = tcg_cpu_reset_hold;
221 ops->insert_gdbstub_breakpoint = tcg_insert_gdbstub_breakpoint;
222 ops->remove_gdbstub_breakpoint = tcg_remove_gdbstub_breakpoint;
223 ops->remove_all_gdbstub_breakpoints = tcg_remove_all_gdbstub_breakpoints;
224 }
225
226 static void tcg_accel_ops_class_init(ObjectClass *oc, const void *data)
227 {
228 AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
229
230 ops->ops_init = tcg_accel_ops_init;
231 }
232
233 static const TypeInfo tcg_accel_ops_type = {
234 .name = ACCEL_OPS_NAME("tcg"),
235
236 .parent = TYPE_ACCEL_OPS,
237 .class_init = tcg_accel_ops_class_init,
238 .abstract = true,
239 };
240 module_obj(ACCEL_OPS_NAME("tcg"));
241
242 static void tcg_accel_ops_register_types(void)
243 {
244 type_register_static(&tcg_accel_ops_type);
245 }
246 type_init(tcg_accel_ops_register_types);