| 1 | /* |
| 2 | * ARM AArch64 ELF definitions for bsd-user |
| 3 | * |
| 4 | * Copyright (c) 2015 Stacey D. Son |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | #ifndef TARGET_ARCH_ELF_H |
| 9 | #define TARGET_ARCH_ELF_H |
| 10 | |
| 11 | #define ELF_START_MMAP 0x80000000 |
| 12 | #define ELF_ET_DYN_LOAD_ADDR 0x100000 |
| 13 | |
| 14 | #define elf_check_arch(x) ((x) == EM_AARCH64) |
| 15 | |
| 16 | #define ELF_CLASS ELFCLASS64 |
| 17 | #define ELF_DATA ELFDATA2LSB |
| 18 | #define ELF_ARCH EM_AARCH64 |
| 19 | |
| 20 | #define USE_ELF_CORE_DUMP |
| 21 | #define ELF_EXEC_PAGESIZE 4096 |
| 22 | |
| 23 | enum { |
| 24 | ARM_HWCAP_A64_FP = 1 << 0, |
| 25 | ARM_HWCAP_A64_ASIMD = 1 << 1, |
| 26 | ARM_HWCAP_A64_EVTSTRM = 1 << 2, |
| 27 | ARM_HWCAP_A64_AES = 1 << 3, |
| 28 | ARM_HWCAP_A64_PMULL = 1 << 4, |
| 29 | ARM_HWCAP_A64_SHA1 = 1 << 5, |
| 30 | ARM_HWCAP_A64_SHA2 = 1 << 6, |
| 31 | ARM_HWCAP_A64_CRC32 = 1 << 7, |
| 32 | ARM_HWCAP_A64_ATOMICS = 1 << 8, |
| 33 | ARM_HWCAP_A64_FPHP = 1 << 9, |
| 34 | ARM_HWCAP_A64_ASIMDHP = 1 << 10, |
| 35 | ARM_HWCAP_A64_CPUID = 1 << 11, |
| 36 | ARM_HWCAP_A64_ASIMDRDM = 1 << 12, |
| 37 | ARM_HWCAP_A64_JSCVT = 1 << 13, |
| 38 | ARM_HWCAP_A64_FCMA = 1 << 14, |
| 39 | ARM_HWCAP_A64_LRCPC = 1 << 15, |
| 40 | ARM_HWCAP_A64_DCPOP = 1 << 16, |
| 41 | ARM_HWCAP_A64_SHA3 = 1 << 17, |
| 42 | ARM_HWCAP_A64_SM3 = 1 << 18, |
| 43 | ARM_HWCAP_A64_SM4 = 1 << 19, |
| 44 | ARM_HWCAP_A64_ASIMDDP = 1 << 20, |
| 45 | ARM_HWCAP_A64_SHA512 = 1 << 21, |
| 46 | ARM_HWCAP_A64_SVE = 1 << 22, |
| 47 | ARM_HWCAP_A64_ASIMDFHM = 1 << 23, |
| 48 | ARM_HWCAP_A64_DIT = 1 << 24, |
| 49 | ARM_HWCAP_A64_USCAT = 1 << 25, |
| 50 | ARM_HWCAP_A64_ILRCPC = 1 << 26, |
| 51 | ARM_HWCAP_A64_FLAGM = 1 << 27, |
| 52 | ARM_HWCAP_A64_SSBS = 1 << 28, |
| 53 | ARM_HWCAP_A64_SB = 1 << 29, |
| 54 | ARM_HWCAP_A64_PACA = 1 << 30, |
| 55 | ARM_HWCAP_A64_PACG = 1UL << 31, |
| 56 | |
| 57 | ARM_HWCAP2_A64_DCPODP = 1 << 0, |
| 58 | ARM_HWCAP2_A64_SVE2 = 1 << 1, |
| 59 | ARM_HWCAP2_A64_SVEAES = 1 << 2, |
| 60 | ARM_HWCAP2_A64_SVEPMULL = 1 << 3, |
| 61 | ARM_HWCAP2_A64_SVEBITPERM = 1 << 4, |
| 62 | ARM_HWCAP2_A64_SVESHA3 = 1 << 5, |
| 63 | ARM_HWCAP2_A64_SVESM4 = 1 << 6, |
| 64 | ARM_HWCAP2_A64_FLAGM2 = 1 << 7, |
| 65 | ARM_HWCAP2_A64_FRINT = 1 << 8, |
| 66 | ARM_HWCAP2_A64_SVEI8MM = 1 << 9, |
| 67 | ARM_HWCAP2_A64_SVEF32MM = 1 << 10, |
| 68 | ARM_HWCAP2_A64_SVEF64MM = 1 << 11, |
| 69 | ARM_HWCAP2_A64_SVEBF16 = 1 << 12, |
| 70 | ARM_HWCAP2_A64_I8MM = 1 << 13, |
| 71 | ARM_HWCAP2_A64_BF16 = 1 << 14, |
| 72 | ARM_HWCAP2_A64_DGH = 1 << 15, |
| 73 | ARM_HWCAP2_A64_RNG = 1 << 16, |
| 74 | ARM_HWCAP2_A64_BTI = 1 << 17, |
| 75 | ARM_HWCAP2_A64_MTE = 1 << 18, |
| 76 | }; |
| 77 | |
| 78 | #define ELF_HWCAP get_elf_hwcap() |
| 79 | #define ELF_HWCAP2 get_elf_hwcap2() |
| 80 | |
| 81 | #define GET_FEATURE_ID(feat, hwcap) \ |
| 82 | do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) |
| 83 | |
| 84 | static uint32_t get_elf_hwcap(void) |
| 85 | { |
| 86 | ARMCPU *cpu = ARM_CPU(thread_cpu); |
| 87 | uint32_t hwcaps = 0; |
| 88 | |
| 89 | hwcaps |= ARM_HWCAP_A64_FP; |
| 90 | hwcaps |= ARM_HWCAP_A64_ASIMD; |
| 91 | hwcaps |= ARM_HWCAP_A64_CPUID; |
| 92 | |
| 93 | /* probe for the extra features */ |
| 94 | |
| 95 | GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); |
| 96 | GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); |
| 97 | GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1); |
| 98 | GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2); |
| 99 | GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512); |
| 100 | GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32); |
| 101 | GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3); |
| 102 | GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3); |
| 103 | GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4); |
| 104 | GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); |
| 105 | GET_FEATURE_ID(aa64_lse, ARM_HWCAP_A64_ATOMICS); |
| 106 | GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); |
| 107 | GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); |
| 108 | GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); |
| 109 | GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); |
| 110 | GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); |
| 111 | GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); |
| 112 | GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); |
| 113 | GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); |
| 114 | GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); |
| 115 | GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); |
| 116 | GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); |
| 117 | GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); |
| 118 | |
| 119 | return hwcaps; |
| 120 | } |
| 121 | |
| 122 | static uint32_t get_elf_hwcap2(void) |
| 123 | { |
| 124 | ARMCPU *cpu = ARM_CPU(thread_cpu); |
| 125 | uint32_t hwcaps = 0; |
| 126 | |
| 127 | GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); |
| 128 | GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); |
| 129 | GET_FEATURE_ID(aa64_sve_aes, ARM_HWCAP2_A64_SVEAES); |
| 130 | GET_FEATURE_ID(aa64_sve_pmull128, ARM_HWCAP2_A64_SVEPMULL); |
| 131 | GET_FEATURE_ID(aa64_sve_bitperm, ARM_HWCAP2_A64_SVEBITPERM); |
| 132 | GET_FEATURE_ID(aa64_sve_sha3, ARM_HWCAP2_A64_SVESHA3); |
| 133 | GET_FEATURE_ID(aa64_sve_sm4, ARM_HWCAP2_A64_SVESM4); |
| 134 | GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); |
| 135 | GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); |
| 136 | GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); |
| 137 | GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); |
| 138 | GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); |
| 139 | GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); |
| 140 | GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); |
| 141 | GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); |
| 142 | GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); |
| 143 | GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); |
| 144 | GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); |
| 145 | |
| 146 | return hwcaps; |
| 147 | } |
| 148 | |
| 149 | #undef GET_FEATURE_ID |
| 150 | |
| 151 | #endif /* TARGET_ARCH_ELF_H */ |