| 1 | /* |
| 2 | * arm ELF definitions |
| 3 | * |
| 4 | * Copyright (c) 2013 Stacey D. Son |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | #ifndef TARGET_ARCH_ELF_H |
| 9 | #define TARGET_ARCH_ELF_H |
| 10 | |
| 11 | #define ELF_ET_DYN_LOAD_ADDR 0x500000 |
| 12 | |
| 13 | #define elf_check_arch(x) ((x) == EM_ARM) |
| 14 | |
| 15 | #define ELF_CLASS ELFCLASS32 |
| 16 | #define ELF_DATA ELFDATA2LSB |
| 17 | #define ELF_ARCH EM_ARM |
| 18 | |
| 19 | #define USE_ELF_CORE_DUMP |
| 20 | #define ELF_EXEC_PAGESIZE 4096 |
| 21 | |
| 22 | #define ELF_HWCAP get_elf_hwcap() |
| 23 | #define ELF_HWCAP2 get_elf_hwcap2() |
| 24 | |
| 25 | #define GET_FEATURE(feat, hwcap) \ |
| 26 | do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) |
| 27 | |
| 28 | #define GET_FEATURE_ID(feat, hwcap) \ |
| 29 | do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) |
| 30 | |
| 31 | enum { |
| 32 | ARM_HWCAP_ARM_SWP = 1 << 0, |
| 33 | ARM_HWCAP_ARM_HALF = 1 << 1, |
| 34 | ARM_HWCAP_ARM_THUMB = 1 << 2, |
| 35 | ARM_HWCAP_ARM_26BIT = 1 << 3, |
| 36 | ARM_HWCAP_ARM_FAST_MULT = 1 << 4, |
| 37 | ARM_HWCAP_ARM_FPA = 1 << 5, |
| 38 | ARM_HWCAP_ARM_VFP = 1 << 6, |
| 39 | ARM_HWCAP_ARM_EDSP = 1 << 7, |
| 40 | ARM_HWCAP_ARM_JAVA = 1 << 8, |
| 41 | ARM_HWCAP_ARM_IWMMXT = 1 << 9, |
| 42 | ARM_HWCAP_ARM_CRUNCH = 1 << 10, |
| 43 | ARM_HWCAP_ARM_THUMBEE = 1 << 11, |
| 44 | ARM_HWCAP_ARM_NEON = 1 << 12, |
| 45 | ARM_HWCAP_ARM_VFPv3 = 1 << 13, |
| 46 | ARM_HWCAP_ARM_VFPv3D16 = 1 << 14, |
| 47 | ARM_HWCAP_ARM_TLS = 1 << 15, |
| 48 | ARM_HWCAP_ARM_VFPv4 = 1 << 16, |
| 49 | ARM_HWCAP_ARM_IDIVA = 1 << 17, |
| 50 | ARM_HWCAP_ARM_IDIVT = 1 << 18, |
| 51 | ARM_HWCAP_ARM_VFPD32 = 1 << 19, |
| 52 | ARM_HWCAP_ARM_LPAE = 1 << 20, |
| 53 | ARM_HWCAP_ARM_EVTSTRM = 1 << 21, |
| 54 | }; |
| 55 | |
| 56 | enum { |
| 57 | ARM_HWCAP2_ARM_AES = 1 << 0, |
| 58 | ARM_HWCAP2_ARM_PMULL = 1 << 1, |
| 59 | ARM_HWCAP2_ARM_SHA1 = 1 << 2, |
| 60 | ARM_HWCAP2_ARM_SHA2 = 1 << 3, |
| 61 | ARM_HWCAP2_ARM_CRC32 = 1 << 4, |
| 62 | }; |
| 63 | |
| 64 | static uint32_t get_elf_hwcap(void) |
| 65 | { |
| 66 | ARMCPU *cpu = ARM_CPU(thread_cpu); |
| 67 | uint32_t hwcaps = 0; |
| 68 | |
| 69 | hwcaps |= ARM_HWCAP_ARM_SWP; |
| 70 | hwcaps |= ARM_HWCAP_ARM_HALF; |
| 71 | hwcaps |= ARM_HWCAP_ARM_THUMB; |
| 72 | hwcaps |= ARM_HWCAP_ARM_FAST_MULT; |
| 73 | |
| 74 | /* probe for the extra features */ |
| 75 | /* EDSP is in v5TE and above */ |
| 76 | GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); |
| 77 | GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); |
| 78 | GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); |
| 79 | GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); |
| 80 | GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); |
| 81 | GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); |
| 82 | GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); |
| 83 | GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); |
| 84 | |
| 85 | if (cpu_isar_feature(aa32_fpsp_v3, cpu) || |
| 86 | cpu_isar_feature(aa32_fpdp_v3, cpu)) { |
| 87 | hwcaps |= ARM_HWCAP_ARM_VFPv3; |
| 88 | if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
| 89 | hwcaps |= ARM_HWCAP_ARM_VFPD32; |
| 90 | } else { |
| 91 | hwcaps |= ARM_HWCAP_ARM_VFPv3D16; |
| 92 | } |
| 93 | } |
| 94 | GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); |
| 95 | |
| 96 | return hwcaps; |
| 97 | } |
| 98 | |
| 99 | static uint32_t get_elf_hwcap2(void) |
| 100 | { |
| 101 | ARMCPU *cpu = ARM_CPU(thread_cpu); |
| 102 | uint32_t hwcaps = 0; |
| 103 | |
| 104 | GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); |
| 105 | GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); |
| 106 | GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1); |
| 107 | GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2); |
| 108 | GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32); |
| 109 | return hwcaps; |
| 110 | } |
| 111 | |
| 112 | #undef GET_FEATURE |
| 113 | #undef GET_FEATURE_ID |
| 114 | |
| 115 | #endif /* TARGET_ARCH_ELF_H */ |