| 1 | /* |
| 2 | * i386 cpu init and loop |
| 3 | * |
| 4 | * Copyright (c) 2013 Stacey D. Son |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | #ifndef TARGET_ARCH_CPU_H |
| 9 | #define TARGET_ARCH_CPU_H |
| 10 | |
| 11 | #include "target_arch.h" |
| 12 | #include "signal-common.h" |
| 13 | |
| 14 | #define TARGET_DEFAULT_CPU_MODEL "qemu32" |
| 15 | |
| 16 | static inline void target_cpu_init(CPUX86State *env, |
| 17 | struct target_pt_regs *regs) |
| 18 | { |
| 19 | uint64_t *gdt_table; |
| 20 | |
| 21 | env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; |
| 22 | env->hflags |= HF_PE_MASK | HF_CPL_MASK; |
| 23 | if (env->features[FEAT_1_EDX] & CPUID_SSE) { |
| 24 | env->cr[4] |= CR4_OSFXSR_MASK; |
| 25 | env->hflags |= HF_OSFXSR_MASK; |
| 26 | } |
| 27 | |
| 28 | /* flags setup : we activate the IRQs by default as in user mode */ |
| 29 | env->eflags |= IF_MASK; |
| 30 | |
| 31 | /* register setup */ |
| 32 | env->regs[R_EAX] = regs->eax; |
| 33 | env->regs[R_EBX] = regs->ebx; |
| 34 | env->regs[R_ECX] = regs->ecx; |
| 35 | env->regs[R_EDX] = regs->edx; |
| 36 | env->regs[R_ESI] = regs->esi; |
| 37 | env->regs[R_EDI] = regs->edi; |
| 38 | env->regs[R_EBP] = regs->ebp; |
| 39 | env->regs[R_ESP] = regs->esp; |
| 40 | env->eip = regs->eip; |
| 41 | |
| 42 | /* interrupt setup */ |
| 43 | env->idt.limit = 255; |
| 44 | |
| 45 | env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), |
| 46 | PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); |
| 47 | bsd_i386_set_idt_base(env->idt.base); |
| 48 | bsd_i386_set_idt(0, 0); |
| 49 | bsd_i386_set_idt(1, 0); |
| 50 | bsd_i386_set_idt(2, 0); |
| 51 | bsd_i386_set_idt(3, 3); |
| 52 | bsd_i386_set_idt(4, 3); |
| 53 | bsd_i386_set_idt(5, 0); |
| 54 | bsd_i386_set_idt(6, 0); |
| 55 | bsd_i386_set_idt(7, 0); |
| 56 | bsd_i386_set_idt(8, 0); |
| 57 | bsd_i386_set_idt(9, 0); |
| 58 | bsd_i386_set_idt(10, 0); |
| 59 | bsd_i386_set_idt(11, 0); |
| 60 | bsd_i386_set_idt(12, 0); |
| 61 | bsd_i386_set_idt(13, 0); |
| 62 | bsd_i386_set_idt(14, 0); |
| 63 | bsd_i386_set_idt(15, 0); |
| 64 | bsd_i386_set_idt(16, 0); |
| 65 | bsd_i386_set_idt(17, 0); |
| 66 | bsd_i386_set_idt(18, 0); |
| 67 | bsd_i386_set_idt(19, 0); |
| 68 | bsd_i386_set_idt(0x80, 3); |
| 69 | |
| 70 | /* segment setup */ |
| 71 | env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, |
| 72 | PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); |
| 73 | env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; |
| 74 | gdt_table = g2h_untagged(env->gdt.base); |
| 75 | |
| 76 | bsd_i386_write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
| 77 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | |
| 78 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); |
| 79 | |
| 80 | bsd_i386_write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, |
| 81 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | |
| 82 | (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); |
| 83 | |
| 84 | cpu_x86_load_seg(env, R_CS, __USER_CS); |
| 85 | cpu_x86_load_seg(env, R_SS, __USER_DS); |
| 86 | cpu_x86_load_seg(env, R_DS, __USER_DS); |
| 87 | cpu_x86_load_seg(env, R_ES, __USER_DS); |
| 88 | cpu_x86_load_seg(env, R_FS, __USER_DS); |
| 89 | cpu_x86_load_seg(env, R_GS, __USER_DS); |
| 90 | /* This hack makes Wine work... */ |
| 91 | env->segs[R_FS].selector = 0; |
| 92 | } |
| 93 | |
| 94 | static inline G_NORETURN void target_cpu_loop(CPUX86State *env) |
| 95 | { |
| 96 | CPUState *cs = env_cpu(env); |
| 97 | int trapnr; |
| 98 | abi_ulong pc; |
| 99 | /* target_siginfo_t info; */ |
| 100 | |
| 101 | for (;;) { |
| 102 | cpu_exec_start(cs); |
| 103 | trapnr = cpu_exec(cs); |
| 104 | cpu_exec_end(cs); |
| 105 | qemu_process_cpu_events(cs); |
| 106 | |
| 107 | switch (trapnr) { |
| 108 | case 0x80: { |
| 109 | /* syscall from int $0x80 */ |
| 110 | abi_ulong params = (abi_ulong) env->regs[R_ESP] + |
| 111 | sizeof(int32_t); |
| 112 | int32_t syscall_nr = env->regs[R_EAX]; |
| 113 | int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8; |
| 114 | |
| 115 | if (syscall_nr == TARGET_FREEBSD_NR_syscall) { |
| 116 | get_user_s32(syscall_nr, params); |
| 117 | params += sizeof(int32_t); |
| 118 | } else if (syscall_nr == TARGET_FREEBSD_NR___syscall) { |
| 119 | get_user_s32(syscall_nr, params); |
| 120 | params += sizeof(int64_t); |
| 121 | } |
| 122 | get_user_s32(arg1, params); |
| 123 | params += sizeof(int32_t); |
| 124 | get_user_s32(arg2, params); |
| 125 | params += sizeof(int32_t); |
| 126 | get_user_s32(arg3, params); |
| 127 | params += sizeof(int32_t); |
| 128 | get_user_s32(arg4, params); |
| 129 | params += sizeof(int32_t); |
| 130 | get_user_s32(arg5, params); |
| 131 | params += sizeof(int32_t); |
| 132 | get_user_s32(arg6, params); |
| 133 | params += sizeof(int32_t); |
| 134 | get_user_s32(arg7, params); |
| 135 | params += sizeof(int32_t); |
| 136 | get_user_s32(arg8, params); |
| 137 | env->regs[R_EAX] = do_freebsd_syscall(env, |
| 138 | syscall_nr, |
| 139 | arg1, |
| 140 | arg2, |
| 141 | arg3, |
| 142 | arg4, |
| 143 | arg5, |
| 144 | arg6, |
| 145 | arg7, |
| 146 | arg8); |
| 147 | } |
| 148 | if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) { |
| 149 | env->regs[R_EAX] = -env->regs[R_EAX]; |
| 150 | env->eflags |= CC_C; |
| 151 | } else { |
| 152 | env->eflags &= ~CC_C; |
| 153 | } |
| 154 | break; |
| 155 | |
| 156 | case EXCP_SYSCALL: |
| 157 | /* doesn't do anything */ |
| 158 | break; |
| 159 | |
| 160 | case EXCP_INTERRUPT: |
| 161 | /* just indicate that signals should be handled asap */ |
| 162 | break; |
| 163 | |
| 164 | case EXCP_ATOMIC: |
| 165 | cpu_exec_step_atomic(cs); |
| 166 | break; |
| 167 | |
| 168 | default: |
| 169 | pc = env->segs[R_CS].base + env->eip; |
| 170 | fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - " |
| 171 | "aborting\n", (long)pc, trapnr); |
| 172 | abort(); |
| 173 | } |
| 174 | process_pending_signals(env); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | static inline void target_cpu_clone_regs(CPUX86State *env, target_ulong newsp) |
| 179 | { |
| 180 | if (newsp) { |
| 181 | env->regs[R_ESP] = newsp; |
| 182 | } |
| 183 | env->regs[R_EAX] = 0; |
| 184 | } |
| 185 | |
| 186 | static inline void target_cpu_reset(CPUArchState *env) |
| 187 | { |
| 188 | cpu_reset(env_cpu(env)); |
| 189 | } |
| 190 | |
| 191 | #endif /* TARGET_ARCH_CPU_H */ |