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1 /*
2 * x86_64 cpu init and loop
3 *
4 * Copyright (c) 2013 Stacey D. Son
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8 #ifndef TARGET_ARCH_CPU_H
9 #define TARGET_ARCH_CPU_H
10
11 #include "target_arch.h"
12 #include "signal-common.h"
13
14 #define TARGET_DEFAULT_CPU_MODEL "qemu64"
15
16 static inline void target_cpu_init(CPUX86State *env,
17 struct target_pt_regs *regs)
18 {
19 uint64_t *gdt_table;
20
21 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
22 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
23 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
24 env->cr[4] |= CR4_OSFXSR_MASK;
25 env->hflags |= HF_OSFXSR_MASK;
26 }
27
28 /* enable 64 bit mode if possible */
29 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
30 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
31 exit(1);
32 }
33 env->cr[4] |= CR4_PAE_MASK;
34 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
35 env->hflags |= HF_LMA_MASK;
36
37 /* flags setup : we activate the IRQs by default as in user mode */
38 env->eflags |= IF_MASK;
39
40 /* register setup */
41 env->regs[R_EAX] = regs->rax;
42 env->regs[R_EBX] = regs->rbx;
43 env->regs[R_ECX] = regs->rcx;
44 env->regs[R_EDX] = regs->rdx;
45 env->regs[R_ESI] = regs->rsi;
46 env->regs[R_EDI] = regs->rdi;
47 env->regs[R_EBP] = regs->rbp;
48 env->regs[R_ESP] = regs->rsp;
49 env->eip = regs->rip;
50
51 /* interrupt setup */
52 env->idt.limit = 511;
53
54 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
55 PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
56 bsd_x86_64_set_idt_base(env->idt.base);
57 bsd_x86_64_set_idt(0, 0);
58 bsd_x86_64_set_idt(1, 0);
59 bsd_x86_64_set_idt(2, 0);
60 bsd_x86_64_set_idt(3, 3);
61 bsd_x86_64_set_idt(4, 3);
62 bsd_x86_64_set_idt(5, 0);
63 bsd_x86_64_set_idt(6, 0);
64 bsd_x86_64_set_idt(7, 0);
65 bsd_x86_64_set_idt(8, 0);
66 bsd_x86_64_set_idt(9, 0);
67 bsd_x86_64_set_idt(10, 0);
68 bsd_x86_64_set_idt(11, 0);
69 bsd_x86_64_set_idt(12, 0);
70 bsd_x86_64_set_idt(13, 0);
71 bsd_x86_64_set_idt(14, 0);
72 bsd_x86_64_set_idt(15, 0);
73 bsd_x86_64_set_idt(16, 0);
74 bsd_x86_64_set_idt(17, 0);
75 bsd_x86_64_set_idt(18, 0);
76 bsd_x86_64_set_idt(19, 0);
77 bsd_x86_64_set_idt(0x80, 3);
78
79 /* segment setup */
80 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
81 PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
82 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
83 gdt_table = g2h_untagged(env->gdt.base);
84
85 /* 64 bit code segment */
86 bsd_x86_64_write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
87 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | DESC_L_MASK
88 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
89
90 bsd_x86_64_write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
91 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
92 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
93
94 cpu_x86_load_seg(env, R_CS, __USER_CS);
95 cpu_x86_load_seg(env, R_SS, __USER_DS);
96 cpu_x86_load_seg(env, R_DS, 0);
97 cpu_x86_load_seg(env, R_ES, 0);
98 cpu_x86_load_seg(env, R_FS, 0);
99 cpu_x86_load_seg(env, R_GS, 0);
100 }
101
102 static inline G_NORETURN void target_cpu_loop(CPUX86State *env)
103 {
104 CPUState *cs = env_cpu(env);
105 int trapnr;
106 abi_ulong pc;
107 /* target_siginfo_t info; */
108
109 for (;;) {
110 cpu_exec_start(cs);
111 trapnr = cpu_exec(cs);
112 cpu_exec_end(cs);
113 qemu_process_cpu_events(cs);
114
115 switch (trapnr) {
116 case EXCP_SYSCALL:
117 /* syscall from syscall instruction */
118 env->regs[R_EAX] = do_freebsd_syscall(env,
119 env->regs[R_EAX],
120 env->regs[R_EDI],
121 env->regs[R_ESI],
122 env->regs[R_EDX],
123 env->regs[R_ECX],
124 env->regs[8],
125 env->regs[9], 0, 0);
126 env->eip = env->exception_next_eip;
127 if (((abi_ulong)env->regs[R_EAX]) >= (abi_ulong)(-515)) {
128 env->regs[R_EAX] = -env->regs[R_EAX];
129 env->eflags |= CC_C;
130 } else {
131 env->eflags &= ~CC_C;
132 }
133 break;
134
135 case EXCP_INTERRUPT:
136 /* just indicate that signals should be handled asap */
137 break;
138
139 case EXCP_ATOMIC:
140 cpu_exec_step_atomic(cs);
141 break;
142
143 default:
144 pc = env->segs[R_CS].base + env->eip;
145 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - "
146 "aborting\n", (long)pc, trapnr);
147 abort();
148 }
149 process_pending_signals(env);
150 }
151 }
152
153 static inline void target_cpu_clone_regs(CPUX86State *env, target_ulong newsp)
154 {
155 if (newsp) {
156 env->regs[R_ESP] = newsp;
157 }
158 env->regs[R_EAX] = 0;
159 }
160
161 static inline void target_cpu_reset(CPUArchState *env)
162 {
163 cpu_reset(env_cpu(env));
164 }
165
166 #endif /* TARGET_ARCH_CPU_H */