| 1 | /* |
| 2 | * Virtio vhost-user GPU Device |
| 3 | * |
| 4 | * Copyright Red Hat, Inc. 2013-2018 |
| 5 | * |
| 6 | * Authors: |
| 7 | * Dave Airlie <airlied@redhat.com> |
| 8 | * Gerd Hoffmann <kraxel@redhat.com> |
| 9 | * Marc-André Lureau <marcandre.lureau@redhat.com> |
| 10 | * |
| 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 12 | * See the COPYING file in the top-level directory. |
| 13 | */ |
| 14 | |
| 15 | #include "qemu/osdep.h" |
| 16 | #include <virglrenderer.h> |
| 17 | #include "virgl.h" |
| 18 | |
| 19 | #include <epoxy/gl.h> |
| 20 | |
| 21 | void |
| 22 | vg_virgl_update_cursor_data(VuGpu *g, uint32_t resource_id, |
| 23 | gpointer data) |
| 24 | { |
| 25 | uint32_t width, height; |
| 26 | uint32_t *cursor; |
| 27 | |
| 28 | cursor = virgl_renderer_get_cursor_data(resource_id, &width, &height); |
| 29 | g_return_if_fail(cursor != NULL); |
| 30 | g_return_if_fail(width == 64); |
| 31 | g_return_if_fail(height == 64); |
| 32 | |
| 33 | memcpy(data, cursor, 64 * 64 * sizeof(uint32_t)); |
| 34 | free(cursor); |
| 35 | } |
| 36 | |
| 37 | static void |
| 38 | virgl_cmd_context_create(VuGpu *g, |
| 39 | struct virtio_gpu_ctrl_command *cmd) |
| 40 | { |
| 41 | struct virtio_gpu_ctx_create cc; |
| 42 | |
| 43 | VUGPU_FILL_CMD(cc); |
| 44 | |
| 45 | virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, |
| 46 | cc.debug_name); |
| 47 | } |
| 48 | |
| 49 | static void |
| 50 | virgl_cmd_context_destroy(VuGpu *g, |
| 51 | struct virtio_gpu_ctrl_command *cmd) |
| 52 | { |
| 53 | struct virtio_gpu_ctx_destroy cd; |
| 54 | |
| 55 | VUGPU_FILL_CMD(cd); |
| 56 | |
| 57 | virgl_renderer_context_destroy(cd.hdr.ctx_id); |
| 58 | } |
| 59 | |
| 60 | static void |
| 61 | virgl_cmd_create_resource_2d(VuGpu *g, |
| 62 | struct virtio_gpu_ctrl_command *cmd) |
| 63 | { |
| 64 | struct virtio_gpu_resource_create_2d c2d; |
| 65 | struct virgl_renderer_resource_create_args args; |
| 66 | |
| 67 | VUGPU_FILL_CMD(c2d); |
| 68 | |
| 69 | args.handle = c2d.resource_id; |
| 70 | args.target = 2; |
| 71 | args.format = c2d.format; |
| 72 | args.bind = (1 << 1); |
| 73 | args.width = c2d.width; |
| 74 | args.height = c2d.height; |
| 75 | args.depth = 1; |
| 76 | args.array_size = 1; |
| 77 | args.last_level = 0; |
| 78 | args.nr_samples = 0; |
| 79 | args.flags = VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP; |
| 80 | virgl_renderer_resource_create(&args, NULL, 0); |
| 81 | } |
| 82 | |
| 83 | static void |
| 84 | virgl_cmd_create_resource_3d(VuGpu *g, |
| 85 | struct virtio_gpu_ctrl_command *cmd) |
| 86 | { |
| 87 | struct virtio_gpu_resource_create_3d c3d; |
| 88 | struct virgl_renderer_resource_create_args args; |
| 89 | |
| 90 | VUGPU_FILL_CMD(c3d); |
| 91 | |
| 92 | args.handle = c3d.resource_id; |
| 93 | args.target = c3d.target; |
| 94 | args.format = c3d.format; |
| 95 | args.bind = c3d.bind; |
| 96 | args.width = c3d.width; |
| 97 | args.height = c3d.height; |
| 98 | args.depth = c3d.depth; |
| 99 | args.array_size = c3d.array_size; |
| 100 | args.last_level = c3d.last_level; |
| 101 | args.nr_samples = c3d.nr_samples; |
| 102 | args.flags = c3d.flags; |
| 103 | virgl_renderer_resource_create(&args, NULL, 0); |
| 104 | } |
| 105 | |
| 106 | static void |
| 107 | virgl_cmd_resource_unref(VuGpu *g, |
| 108 | struct virtio_gpu_ctrl_command *cmd) |
| 109 | { |
| 110 | struct virtio_gpu_resource_unref unref; |
| 111 | struct iovec *res_iovs = NULL; |
| 112 | int num_iovs = 0; |
| 113 | |
| 114 | VUGPU_FILL_CMD(unref); |
| 115 | |
| 116 | virgl_renderer_resource_detach_iov(unref.resource_id, |
| 117 | &res_iovs, |
| 118 | &num_iovs); |
| 119 | if (res_iovs != NULL && num_iovs != 0) { |
| 120 | vg_cleanup_mapping_iov(g, res_iovs, num_iovs); |
| 121 | } |
| 122 | virgl_renderer_resource_unref(unref.resource_id); |
| 123 | } |
| 124 | |
| 125 | /* Not yet(?) defined in standard-headers, remove when possible */ |
| 126 | #ifndef VIRTIO_GPU_CAPSET_VIRGL2 |
| 127 | #define VIRTIO_GPU_CAPSET_VIRGL2 2 |
| 128 | #endif |
| 129 | |
| 130 | static void |
| 131 | virgl_cmd_get_capset_info(VuGpu *g, |
| 132 | struct virtio_gpu_ctrl_command *cmd) |
| 133 | { |
| 134 | struct virtio_gpu_get_capset_info info; |
| 135 | struct virtio_gpu_resp_capset_info resp; |
| 136 | |
| 137 | VUGPU_FILL_CMD(info); |
| 138 | |
| 139 | memset(&resp, 0, sizeof(resp)); |
| 140 | if (info.capset_index == 0) { |
| 141 | resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL; |
| 142 | virgl_renderer_get_cap_set(resp.capset_id, |
| 143 | &resp.capset_max_version, |
| 144 | &resp.capset_max_size); |
| 145 | } else if (info.capset_index == 1) { |
| 146 | resp.capset_id = VIRTIO_GPU_CAPSET_VIRGL2; |
| 147 | virgl_renderer_get_cap_set(resp.capset_id, |
| 148 | &resp.capset_max_version, |
| 149 | &resp.capset_max_size); |
| 150 | } else { |
| 151 | resp.capset_max_version = 0; |
| 152 | resp.capset_max_size = 0; |
| 153 | } |
| 154 | resp.hdr.type = VIRTIO_GPU_RESP_OK_CAPSET_INFO; |
| 155 | vg_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); |
| 156 | } |
| 157 | |
| 158 | uint32_t |
| 159 | vg_virgl_get_num_capsets(void) |
| 160 | { |
| 161 | uint32_t capset2_max_ver, capset2_max_size; |
| 162 | virgl_renderer_get_cap_set(VIRTIO_GPU_CAPSET_VIRGL2, |
| 163 | &capset2_max_ver, |
| 164 | &capset2_max_size); |
| 165 | |
| 166 | return capset2_max_ver ? 2 : 1; |
| 167 | } |
| 168 | |
| 169 | static void |
| 170 | virgl_cmd_get_capset(VuGpu *g, |
| 171 | struct virtio_gpu_ctrl_command *cmd) |
| 172 | { |
| 173 | struct virtio_gpu_get_capset gc; |
| 174 | struct virtio_gpu_resp_capset *resp; |
| 175 | uint32_t max_ver, max_size; |
| 176 | |
| 177 | VUGPU_FILL_CMD(gc); |
| 178 | |
| 179 | virgl_renderer_get_cap_set(gc.capset_id, &max_ver, |
| 180 | &max_size); |
| 181 | if (!max_size) { |
| 182 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; |
| 183 | return; |
| 184 | } |
| 185 | resp = g_malloc0(sizeof(*resp) + max_size); |
| 186 | |
| 187 | resp->hdr.type = VIRTIO_GPU_RESP_OK_CAPSET; |
| 188 | virgl_renderer_fill_caps(gc.capset_id, |
| 189 | gc.capset_version, |
| 190 | (void *)resp->capset_data); |
| 191 | vg_ctrl_response(g, cmd, &resp->hdr, sizeof(*resp) + max_size); |
| 192 | g_free(resp); |
| 193 | } |
| 194 | |
| 195 | static void |
| 196 | virgl_cmd_submit_3d(VuGpu *g, |
| 197 | struct virtio_gpu_ctrl_command *cmd) |
| 198 | { |
| 199 | struct virtio_gpu_cmd_submit cs; |
| 200 | void *buf; |
| 201 | size_t s; |
| 202 | |
| 203 | VUGPU_FILL_CMD(cs); |
| 204 | |
| 205 | if (cs.size > VIRTIO_GPU_MAX_CMD_SUBMIT_SIZE) { |
| 206 | g_critical("%s: command buffer too large (%u)", |
| 207 | __func__, cs.size); |
| 208 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; |
| 209 | return; |
| 210 | } |
| 211 | |
| 212 | buf = g_try_malloc(cs.size); |
| 213 | if (!buf && cs.size) { |
| 214 | cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; |
| 215 | return; |
| 216 | } |
| 217 | s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, |
| 218 | sizeof(cs), buf, cs.size); |
| 219 | if (s != cs.size) { |
| 220 | g_critical("%s: size mismatch (%zd/%d)", __func__, s, cs.size); |
| 221 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; |
| 222 | goto out; |
| 223 | } |
| 224 | |
| 225 | virgl_renderer_submit_cmd(buf, cs.hdr.ctx_id, cs.size / 4); |
| 226 | |
| 227 | out: |
| 228 | g_free(buf); |
| 229 | } |
| 230 | |
| 231 | static void |
| 232 | virgl_cmd_transfer_to_host_2d(VuGpu *g, |
| 233 | struct virtio_gpu_ctrl_command *cmd) |
| 234 | { |
| 235 | struct virtio_gpu_transfer_to_host_2d t2d; |
| 236 | struct virtio_gpu_box box; |
| 237 | |
| 238 | VUGPU_FILL_CMD(t2d); |
| 239 | |
| 240 | box.x = t2d.r.x; |
| 241 | box.y = t2d.r.y; |
| 242 | box.z = 0; |
| 243 | box.w = t2d.r.width; |
| 244 | box.h = t2d.r.height; |
| 245 | box.d = 1; |
| 246 | |
| 247 | virgl_renderer_transfer_write_iov(t2d.resource_id, |
| 248 | 0, |
| 249 | 0, |
| 250 | 0, |
| 251 | 0, |
| 252 | (struct virgl_box *)&box, |
| 253 | t2d.offset, NULL, 0); |
| 254 | } |
| 255 | |
| 256 | static void |
| 257 | virgl_cmd_transfer_to_host_3d(VuGpu *g, |
| 258 | struct virtio_gpu_ctrl_command *cmd) |
| 259 | { |
| 260 | struct virtio_gpu_transfer_host_3d t3d; |
| 261 | |
| 262 | VUGPU_FILL_CMD(t3d); |
| 263 | |
| 264 | virgl_renderer_transfer_write_iov(t3d.resource_id, |
| 265 | t3d.hdr.ctx_id, |
| 266 | t3d.level, |
| 267 | t3d.stride, |
| 268 | t3d.layer_stride, |
| 269 | (struct virgl_box *)&t3d.box, |
| 270 | t3d.offset, NULL, 0); |
| 271 | } |
| 272 | |
| 273 | static void |
| 274 | virgl_cmd_transfer_from_host_3d(VuGpu *g, |
| 275 | struct virtio_gpu_ctrl_command *cmd) |
| 276 | { |
| 277 | struct virtio_gpu_transfer_host_3d tf3d; |
| 278 | |
| 279 | VUGPU_FILL_CMD(tf3d); |
| 280 | |
| 281 | virgl_renderer_transfer_read_iov(tf3d.resource_id, |
| 282 | tf3d.hdr.ctx_id, |
| 283 | tf3d.level, |
| 284 | tf3d.stride, |
| 285 | tf3d.layer_stride, |
| 286 | (struct virgl_box *)&tf3d.box, |
| 287 | tf3d.offset, NULL, 0); |
| 288 | } |
| 289 | |
| 290 | static void |
| 291 | virgl_resource_attach_backing(VuGpu *g, |
| 292 | struct virtio_gpu_ctrl_command *cmd) |
| 293 | { |
| 294 | struct virtio_gpu_resource_attach_backing att_rb; |
| 295 | struct iovec *res_iovs; |
| 296 | int ret; |
| 297 | |
| 298 | VUGPU_FILL_CMD(att_rb); |
| 299 | |
| 300 | ret = vg_create_mapping_iov(g, &att_rb, cmd, &res_iovs); |
| 301 | if (ret != 0) { |
| 302 | cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; |
| 303 | return; |
| 304 | } |
| 305 | |
| 306 | ret = virgl_renderer_resource_attach_iov(att_rb.resource_id, |
| 307 | res_iovs, att_rb.nr_entries); |
| 308 | if (ret != 0) { |
| 309 | vg_cleanup_mapping_iov(g, res_iovs, att_rb.nr_entries); |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | static void |
| 314 | virgl_resource_detach_backing(VuGpu *g, |
| 315 | struct virtio_gpu_ctrl_command *cmd) |
| 316 | { |
| 317 | struct virtio_gpu_resource_detach_backing detach_rb; |
| 318 | struct iovec *res_iovs = NULL; |
| 319 | int num_iovs = 0; |
| 320 | |
| 321 | VUGPU_FILL_CMD(detach_rb); |
| 322 | |
| 323 | virgl_renderer_resource_detach_iov(detach_rb.resource_id, |
| 324 | &res_iovs, |
| 325 | &num_iovs); |
| 326 | if (res_iovs == NULL || num_iovs == 0) { |
| 327 | return; |
| 328 | } |
| 329 | vg_cleanup_mapping_iov(g, res_iovs, num_iovs); |
| 330 | } |
| 331 | |
| 332 | static int |
| 333 | virgl_get_resource_info_modifiers(uint32_t resource_id, |
| 334 | struct virgl_renderer_resource_info *info, |
| 335 | uint64_t *modifiers) |
| 336 | { |
| 337 | int ret; |
| 338 | #ifdef VIRGL_RENDERER_RESOURCE_INFO_EXT_VERSION |
| 339 | struct virgl_renderer_resource_info_ext info_ext; |
| 340 | ret = virgl_renderer_resource_get_info_ext(resource_id, &info_ext); |
| 341 | if (ret) { |
| 342 | return ret; |
| 343 | } |
| 344 | |
| 345 | *info = info_ext.base; |
| 346 | *modifiers = info_ext.modifiers; |
| 347 | #else |
| 348 | ret = virgl_renderer_resource_get_info(resource_id, info); |
| 349 | if (ret) { |
| 350 | return ret; |
| 351 | } |
| 352 | |
| 353 | /* |
| 354 | * Before virgl_renderer_resource_get_info_ext, |
| 355 | * getting the modifiers was not possible. |
| 356 | */ |
| 357 | *modifiers = 0; |
| 358 | #endif |
| 359 | |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static void |
| 364 | virgl_cmd_set_scanout(VuGpu *g, |
| 365 | struct virtio_gpu_ctrl_command *cmd) |
| 366 | { |
| 367 | struct virtio_gpu_set_scanout ss; |
| 368 | struct virgl_renderer_resource_info info; |
| 369 | int ret; |
| 370 | |
| 371 | VUGPU_FILL_CMD(ss); |
| 372 | |
| 373 | if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUTS) { |
| 374 | g_critical("%s: illegal scanout id specified %d", |
| 375 | __func__, ss.scanout_id); |
| 376 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID; |
| 377 | return; |
| 378 | } |
| 379 | |
| 380 | memset(&info, 0, sizeof(info)); |
| 381 | |
| 382 | if (ss.resource_id && ss.r.width && ss.r.height) { |
| 383 | uint64_t modifiers = 0; |
| 384 | ret = virgl_get_resource_info_modifiers(ss.resource_id, &info, |
| 385 | &modifiers); |
| 386 | if (ret) { |
| 387 | g_critical("%s: illegal resource specified %d\n", |
| 388 | __func__, ss.resource_id); |
| 389 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; |
| 390 | return; |
| 391 | } |
| 392 | |
| 393 | int fd = -1; |
| 394 | if (virgl_renderer_get_fd_for_texture(info.tex_id, &fd) < 0) { |
| 395 | g_critical("%s: failed to get fd for texture\n", __func__); |
| 396 | cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; |
| 397 | return; |
| 398 | } |
| 399 | assert(fd >= 0); |
| 400 | VhostUserGpuMsg msg = { |
| 401 | .payload.dmabuf_scanout.scanout_id = ss.scanout_id, |
| 402 | .payload.dmabuf_scanout.x = ss.r.x, |
| 403 | .payload.dmabuf_scanout.y = ss.r.y, |
| 404 | .payload.dmabuf_scanout.width = ss.r.width, |
| 405 | .payload.dmabuf_scanout.height = ss.r.height, |
| 406 | .payload.dmabuf_scanout.fd_width = info.width, |
| 407 | .payload.dmabuf_scanout.fd_height = info.height, |
| 408 | .payload.dmabuf_scanout.fd_stride = info.stride, |
| 409 | .payload.dmabuf_scanout.fd_flags = info.flags, |
| 410 | .payload.dmabuf_scanout.fd_drm_fourcc = info.drm_fourcc |
| 411 | }; |
| 412 | |
| 413 | if (g->use_modifiers) { |
| 414 | /* |
| 415 | * The message uses all the fields set in dmabuf_scanout plus |
| 416 | * modifiers which is appended after VhostUserGpuDMABUFScanout. |
| 417 | */ |
| 418 | msg.request = VHOST_USER_GPU_DMABUF_SCANOUT2; |
| 419 | msg.size = sizeof(VhostUserGpuDMABUFScanout2); |
| 420 | msg.payload.dmabuf_scanout2.modifier = modifiers; |
| 421 | } else { |
| 422 | msg.request = VHOST_USER_GPU_DMABUF_SCANOUT; |
| 423 | msg.size = sizeof(VhostUserGpuDMABUFScanout); |
| 424 | } |
| 425 | |
| 426 | vg_send_msg(g, &msg, fd); |
| 427 | close(fd); |
| 428 | } else { |
| 429 | VhostUserGpuMsg msg = { |
| 430 | .request = VHOST_USER_GPU_DMABUF_SCANOUT, |
| 431 | .size = sizeof(VhostUserGpuDMABUFScanout), |
| 432 | .payload.dmabuf_scanout.scanout_id = ss.scanout_id, |
| 433 | }; |
| 434 | g_debug("disable scanout"); |
| 435 | vg_send_msg(g, &msg, -1); |
| 436 | } |
| 437 | g->scanout[ss.scanout_id].resource_id = ss.resource_id; |
| 438 | } |
| 439 | |
| 440 | static void |
| 441 | virgl_cmd_resource_flush(VuGpu *g, |
| 442 | struct virtio_gpu_ctrl_command *cmd) |
| 443 | { |
| 444 | struct virtio_gpu_resource_flush rf; |
| 445 | int i; |
| 446 | |
| 447 | VUGPU_FILL_CMD(rf); |
| 448 | |
| 449 | glFlush(); |
| 450 | if (!rf.resource_id) { |
| 451 | g_debug("bad resource id for flush..?"); |
| 452 | return; |
| 453 | } |
| 454 | for (i = 0; i < VIRTIO_GPU_MAX_SCANOUTS; i++) { |
| 455 | if (g->scanout[i].resource_id != rf.resource_id) { |
| 456 | continue; |
| 457 | } |
| 458 | VhostUserGpuMsg msg = { |
| 459 | .request = VHOST_USER_GPU_DMABUF_UPDATE, |
| 460 | .size = sizeof(VhostUserGpuUpdate), |
| 461 | .payload.update.scanout_id = i, |
| 462 | .payload.update.x = rf.r.x, |
| 463 | .payload.update.y = rf.r.y, |
| 464 | .payload.update.width = rf.r.width, |
| 465 | .payload.update.height = rf.r.height |
| 466 | }; |
| 467 | vg_send_msg(g, &msg, -1); |
| 468 | vg_wait_ok(g); |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | static void |
| 473 | virgl_cmd_ctx_attach_resource(VuGpu *g, |
| 474 | struct virtio_gpu_ctrl_command *cmd) |
| 475 | { |
| 476 | struct virtio_gpu_ctx_resource att_res; |
| 477 | |
| 478 | VUGPU_FILL_CMD(att_res); |
| 479 | |
| 480 | virgl_renderer_ctx_attach_resource(att_res.hdr.ctx_id, att_res.resource_id); |
| 481 | } |
| 482 | |
| 483 | static void |
| 484 | virgl_cmd_ctx_detach_resource(VuGpu *g, |
| 485 | struct virtio_gpu_ctrl_command *cmd) |
| 486 | { |
| 487 | struct virtio_gpu_ctx_resource det_res; |
| 488 | |
| 489 | VUGPU_FILL_CMD(det_res); |
| 490 | |
| 491 | virgl_renderer_ctx_detach_resource(det_res.hdr.ctx_id, det_res.resource_id); |
| 492 | } |
| 493 | |
| 494 | void vg_virgl_process_cmd(VuGpu *g, struct virtio_gpu_ctrl_command *cmd) |
| 495 | { |
| 496 | virgl_renderer_force_ctx_0(); |
| 497 | switch (cmd->cmd_hdr.type) { |
| 498 | case VIRTIO_GPU_CMD_CTX_CREATE: |
| 499 | virgl_cmd_context_create(g, cmd); |
| 500 | break; |
| 501 | case VIRTIO_GPU_CMD_CTX_DESTROY: |
| 502 | virgl_cmd_context_destroy(g, cmd); |
| 503 | break; |
| 504 | case VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: |
| 505 | virgl_cmd_create_resource_2d(g, cmd); |
| 506 | break; |
| 507 | case VIRTIO_GPU_CMD_RESOURCE_CREATE_3D: |
| 508 | virgl_cmd_create_resource_3d(g, cmd); |
| 509 | break; |
| 510 | case VIRTIO_GPU_CMD_SUBMIT_3D: |
| 511 | virgl_cmd_submit_3d(g, cmd); |
| 512 | break; |
| 513 | case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: |
| 514 | virgl_cmd_transfer_to_host_2d(g, cmd); |
| 515 | break; |
| 516 | case VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D: |
| 517 | virgl_cmd_transfer_to_host_3d(g, cmd); |
| 518 | break; |
| 519 | case VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D: |
| 520 | virgl_cmd_transfer_from_host_3d(g, cmd); |
| 521 | break; |
| 522 | case VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING: |
| 523 | virgl_resource_attach_backing(g, cmd); |
| 524 | break; |
| 525 | case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: |
| 526 | virgl_resource_detach_backing(g, cmd); |
| 527 | break; |
| 528 | case VIRTIO_GPU_CMD_SET_SCANOUT: |
| 529 | virgl_cmd_set_scanout(g, cmd); |
| 530 | break; |
| 531 | case VIRTIO_GPU_CMD_RESOURCE_FLUSH: |
| 532 | virgl_cmd_resource_flush(g, cmd); |
| 533 | break; |
| 534 | case VIRTIO_GPU_CMD_RESOURCE_UNREF: |
| 535 | virgl_cmd_resource_unref(g, cmd); |
| 536 | break; |
| 537 | case VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE: |
| 538 | /* TODO add security */ |
| 539 | virgl_cmd_ctx_attach_resource(g, cmd); |
| 540 | break; |
| 541 | case VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE: |
| 542 | /* TODO add security */ |
| 543 | virgl_cmd_ctx_detach_resource(g, cmd); |
| 544 | break; |
| 545 | case VIRTIO_GPU_CMD_GET_CAPSET_INFO: |
| 546 | virgl_cmd_get_capset_info(g, cmd); |
| 547 | break; |
| 548 | case VIRTIO_GPU_CMD_GET_CAPSET: |
| 549 | virgl_cmd_get_capset(g, cmd); |
| 550 | break; |
| 551 | case VIRTIO_GPU_CMD_GET_DISPLAY_INFO: |
| 552 | vg_get_display_info(g, cmd); |
| 553 | break; |
| 554 | case VIRTIO_GPU_CMD_GET_EDID: |
| 555 | vg_get_edid(g, cmd); |
| 556 | break; |
| 557 | default: |
| 558 | g_debug("TODO handle ctrl %x\n", cmd->cmd_hdr.type); |
| 559 | cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; |
| 560 | break; |
| 561 | } |
| 562 | |
| 563 | if (cmd->state != VG_CMD_STATE_NEW) { |
| 564 | return; |
| 565 | } |
| 566 | |
| 567 | if (cmd->error) { |
| 568 | g_warning("%s: ctrl 0x%x, error 0x%x\n", __func__, |
| 569 | cmd->cmd_hdr.type, cmd->error); |
| 570 | vg_ctrl_response_nodata(g, cmd, cmd->error); |
| 571 | return; |
| 572 | } |
| 573 | |
| 574 | if (!(cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_FENCE)) { |
| 575 | vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); |
| 576 | return; |
| 577 | } |
| 578 | |
| 579 | g_debug("Creating fence id:%" PRId64 " type:%d", |
| 580 | cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); |
| 581 | virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); |
| 582 | } |
| 583 | |
| 584 | static void |
| 585 | virgl_write_fence(void *opaque, uint32_t fence) |
| 586 | { |
| 587 | VuGpu *g = opaque; |
| 588 | struct virtio_gpu_ctrl_command *cmd, *tmp; |
| 589 | |
| 590 | QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { |
| 591 | /* |
| 592 | * the guest can end up emitting fences out of order |
| 593 | * so we should check all fenced cmds not just the first one. |
| 594 | */ |
| 595 | if (cmd->cmd_hdr.fence_id > fence) { |
| 596 | continue; |
| 597 | } |
| 598 | g_debug("FENCE %" PRIu64, cmd->cmd_hdr.fence_id); |
| 599 | vg_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NODATA); |
| 600 | QTAILQ_REMOVE(&g->fenceq, cmd, next); |
| 601 | free(cmd); |
| 602 | g->inflight--; |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \ |
| 607 | VIRGL_RENDERER_CALLBACKS_VERSION >= 2 |
| 608 | static int |
| 609 | virgl_get_drm_fd(void *opaque) |
| 610 | { |
| 611 | VuGpu *g = opaque; |
| 612 | |
| 613 | return g->drm_rnode_fd; |
| 614 | } |
| 615 | #endif |
| 616 | |
| 617 | static struct virgl_renderer_callbacks virgl_cbs = { |
| 618 | #if defined(VIRGL_RENDERER_CALLBACKS_VERSION) && \ |
| 619 | VIRGL_RENDERER_CALLBACKS_VERSION >= 2 |
| 620 | .get_drm_fd = virgl_get_drm_fd, |
| 621 | .version = 2, |
| 622 | #else |
| 623 | .version = 1, |
| 624 | #endif |
| 625 | .write_fence = virgl_write_fence, |
| 626 | }; |
| 627 | |
| 628 | static void |
| 629 | vg_virgl_poll(VuDev *dev, int condition, void *data) |
| 630 | { |
| 631 | virgl_renderer_poll(); |
| 632 | } |
| 633 | |
| 634 | bool |
| 635 | vg_virgl_init(VuGpu *g) |
| 636 | { |
| 637 | int ret; |
| 638 | |
| 639 | if (g->drm_rnode_fd && virgl_cbs.version == 1) { |
| 640 | g_warning("virgl will use the default rendernode"); |
| 641 | } |
| 642 | |
| 643 | ret = virgl_renderer_init(g, |
| 644 | VIRGL_RENDERER_USE_EGL | |
| 645 | VIRGL_RENDERER_THREAD_SYNC, |
| 646 | &virgl_cbs); |
| 647 | if (ret != 0) { |
| 648 | return false; |
| 649 | } |
| 650 | |
| 651 | ret = virgl_renderer_get_poll_fd(); |
| 652 | if (ret != -1) { |
| 653 | g->renderer_source = |
| 654 | vug_source_new(&g->dev, ret, G_IO_IN, vg_virgl_poll, g); |
| 655 | } |
| 656 | |
| 657 | return true; |
| 658 | } |