| 1 | /* |
| 2 | * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 |
| 3 | * bitmanip extension v0.93. |
| 4 | * |
| 5 | * Copyright (c) 2023 Rivos Inc |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "disas/riscv.h" |
| 12 | #include "disas/riscv-xlrbr.h" |
| 13 | |
| 14 | #define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ }; |
| 15 | #include "riscv-xlrbr-op.c.inc" |
| 16 | #undef OP |
| 17 | |
| 18 | const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa) |
| 19 | { |
| 20 | rv_inst inst = dec->inst; |
| 21 | |
| 22 | switch ((inst >> 0) & 0b1111111) { |
| 23 | case 0b0010011: |
| 24 | switch ((inst >> 12) & 0b111) { |
| 25 | case 0b001: |
| 26 | switch ((inst >> 20 & 0b111111111111)) { |
| 27 | case 0b011000010000: |
| 28 | return &op_crc32_b; |
| 29 | case 0b011000010001: |
| 30 | return &op_crc32_h; |
| 31 | case 0b011000010010: |
| 32 | return &op_crc32_w; |
| 33 | case 0b011000010011: |
| 34 | return &op_crc32_d; |
| 35 | case 0b011000011000: |
| 36 | return &op_crc32c_b; |
| 37 | case 0b011000011001: |
| 38 | return &op_crc32c_h; |
| 39 | case 0b011000011010: |
| 40 | return &op_crc32c_w; |
| 41 | case 0b011000011011: |
| 42 | return &op_crc32c_d; |
| 43 | } |
| 44 | break; |
| 45 | } |
| 46 | break; |
| 47 | } |
| 48 | |
| 49 | return NULL; |
| 50 | } |