| 1 | /* |
| 2 | * QEMU RISC-V Disassembler for xventana. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 5 | */ |
| 6 | |
| 7 | #include "qemu/osdep.h" |
| 8 | #include "disas/riscv.h" |
| 9 | #include "disas/riscv-xventana.h" |
| 10 | |
| 11 | #define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ }; |
| 12 | #include "riscv-xventana-op.c.inc" |
| 13 | #undef OP |
| 14 | |
| 15 | const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa) |
| 16 | { |
| 17 | rv_inst inst = dec->inst; |
| 18 | |
| 19 | switch (((inst >> 0) & 0b11)) { |
| 20 | case 3: |
| 21 | switch (((inst >> 2) & 0b11111)) { |
| 22 | case 30: |
| 23 | switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { |
| 24 | case 6: return &op_vt_maskc; |
| 25 | case 7: return &op_vt_maskcn; |
| 26 | } |
| 27 | break; |
| 28 | } |
| 29 | break; |
| 30 | } |
| 31 | |
| 32 | return NULL; |
| 33 | } |