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1 /*
2 * QEMU disassembler -- RISC-V specific header.
3 *
4 * SPDX-License-Identifier: GPL-2.0-or-later
5 */
6
7 #ifndef DISAS_RISCV_H
8 #define DISAS_RISCV_H
9
10 #include "target/riscv/cpu_cfg.h"
11
12 /* types */
13
14 typedef uint32_t rv_inst;
15 typedef uint16_t rv_opcode;
16
17 /* enums */
18
19 typedef enum {
20 rv32,
21 rv64,
22 rv128
23 } rv_isa;
24
25 typedef enum {
26 rv_rm_rne = 0,
27 rv_rm_rtz = 1,
28 rv_rm_rdn = 2,
29 rv_rm_rup = 3,
30 rv_rm_rmm = 4,
31 rv_rm_dyn = 7,
32 } rv_rm;
33
34 typedef enum {
35 rv_fence_i = 8,
36 rv_fence_o = 4,
37 rv_fence_r = 2,
38 rv_fence_w = 1,
39 } rv_fence;
40
41 typedef enum {
42 rv_ireg_zero,
43 rv_ireg_ra,
44 rv_ireg_sp,
45 rv_ireg_gp,
46 rv_ireg_tp,
47 rv_ireg_t0,
48 rv_ireg_t1,
49 rv_ireg_t2,
50 rv_ireg_s0,
51 rv_ireg_s1,
52 rv_ireg_a0,
53 rv_ireg_a1,
54 rv_ireg_a2,
55 rv_ireg_a3,
56 rv_ireg_a4,
57 rv_ireg_a5,
58 rv_ireg_a6,
59 rv_ireg_a7,
60 rv_ireg_s2,
61 rv_ireg_s3,
62 rv_ireg_s4,
63 rv_ireg_s5,
64 rv_ireg_s6,
65 rv_ireg_s7,
66 rv_ireg_s8,
67 rv_ireg_s9,
68 rv_ireg_s10,
69 rv_ireg_s11,
70 rv_ireg_t3,
71 rv_ireg_t4,
72 rv_ireg_t5,
73 rv_ireg_t6,
74 } rv_ireg;
75
76 typedef enum {
77 rvc_end,
78 rvc_rd_eq_ra,
79 rvc_rd_eq_x0,
80 rvc_rs1_eq_x0,
81 rvc_rs2_eq_x0,
82 rvc_rs2_eq_rs1,
83 rvc_rs1_eq_ra,
84 rvc_imm_eq_zero,
85 rvc_imm_eq_n1,
86 rvc_imm_eq_p1,
87 } rvc_constraint;
88
89 typedef enum {
90 rv_codec_illegal,
91 rv_codec_none,
92 rv_codec_u,
93 rv_codec_uj,
94 rv_codec_i,
95 rv_codec_i_sh5,
96 rv_codec_i_sh6,
97 rv_codec_i_sh7,
98 rv_codec_i_csr,
99 rv_codec_s,
100 rv_codec_sb,
101 rv_codec_r,
102 rv_codec_r_m,
103 rv_codec_r4_m,
104 rv_codec_r_a,
105 rv_codec_r_l,
106 rv_codec_r_f,
107 rv_codec_cb,
108 rv_codec_cb_imm,
109 rv_codec_cb_sh5,
110 rv_codec_cb_sh6,
111 rv_codec_ci,
112 rv_codec_ci_sh5,
113 rv_codec_ci_sh6,
114 rv_codec_ci_16sp,
115 rv_codec_ci_lwsp,
116 rv_codec_ci_ldsp,
117 rv_codec_ci_lqsp,
118 rv_codec_ci_li,
119 rv_codec_ci_lui,
120 rv_codec_ci_none,
121 rv_codec_ciw_4spn,
122 rv_codec_cj,
123 rv_codec_cj_jal,
124 rv_codec_cl_lw,
125 rv_codec_cl_ld,
126 rv_codec_cl_lq,
127 rv_codec_cr,
128 rv_codec_cr_mv,
129 rv_codec_cr_jalr,
130 rv_codec_cr_jr,
131 rv_codec_cs,
132 rv_codec_cs_sw,
133 rv_codec_cs_sd,
134 rv_codec_cs_sq,
135 rv_codec_css_swsp,
136 rv_codec_css_sdsp,
137 rv_codec_css_sqsp,
138 rv_codec_k_bs,
139 rv_codec_k_rnum,
140 rv_codec_v_r,
141 rv_codec_v_ldst,
142 rv_codec_v_i,
143 rv_codec_v_i_u,
144 rv_codec_vsetvli,
145 rv_codec_vsetivli,
146 rv_codec_vror_vi,
147 rv_codec_zcb_ext,
148 rv_codec_zcb_mul,
149 rv_codec_zcb_lb,
150 rv_codec_zcb_lh,
151 rv_codec_zcmp_cm_pushpop,
152 rv_codec_zcmp_cm_mv,
153 rv_codec_zcmt_jt,
154 rv_codec_r2_imm5,
155 rv_codec_r2,
156 rv_codec_r2_imm6,
157 rv_codec_r_imm2,
158 rv_codec_r2_immhl,
159 rv_codec_r2_imm2_imm5,
160 rv_codec_fli,
161 rv_codec_lp,
162 rv_codec_cmop,
163 rv_codec_cmop_ss,
164 rv_codec_mop_r,
165 rv_codec_mop_rr,
166 } rv_codec;
167
168 /* structures */
169
170 typedef struct rv_opcode_data rv_opcode_data;
171
172 typedef struct {
173 const rv_opcode_data *op;
174 const rvc_constraint *constraints;
175 } rv_comp_data;
176
177 struct rv_opcode_data {
178 const char *name;
179 rv_codec codec;
180 const char *format;
181 const rv_comp_data *pseudo;
182 };
183
184 typedef struct {
185 const RISCVCPUConfig *cfg;
186 uint64_t pc;
187 uint64_t inst;
188 int32_t imm;
189 int32_t imm1;
190 uint8_t rd;
191 uint8_t rs1;
192 uint8_t rs2;
193 uint8_t rs3;
194 uint8_t rm;
195 uint8_t pred;
196 uint8_t succ;
197 uint8_t aq;
198 uint8_t rl;
199 uint8_t bs;
200 uint8_t rnum;
201 uint8_t vm;
202 uint32_t vzimm;
203 uint8_t rlist;
204 } rv_decode;
205
206 /* instruction formats */
207
208 #define rv_fmt_none "O\t"
209 #define rv_fmt_rs1 "O\t1"
210 #define rv_fmt_rs2 "O\t2"
211 #define rv_fmt_offset "O\to"
212 #define rv_fmt_pred_succ "O\tp,s"
213 #define rv_fmt_rs1_rs2 "O\t1,2"
214 #define rv_fmt_rd_imm "O\t0,i"
215 #define rv_fmt_rd_uimm "O\t0,Ui"
216 #define rv_fmt_imm "O\ti"
217 #define rv_fmt_rd_offset "O\t0,o"
218 #define rv_fmt_rd_uoffset "O\t0,Uo"
219 #define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
220 #define rv_fmt_frd_rs1 "O\t3,1"
221 #define rv_fmt_frd_rs1_rs2 "O\t3,1,2"
222 #define rv_fmt_frd_frs1 "O\t3,4"
223 #define rv_fmt_rd_frs1 "O\t0,4"
224 #define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
225 #define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
226 #define rv_fmt_rm_frd_frs1 "O\tr,3,4"
227 #define rv_fmt_rm_frd_rs1 "O\tr,3,1"
228 #define rv_fmt_rm_rd_frs1 "O\tr,0,4"
229 #define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5"
230 #define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6"
231 #define rv_fmt_rd_rs1_imm "O\t0,1,i"
232 #define rv_fmt_rd_rs1_offset "O\t0,1,i"
233 #define rv_fmt_rd_offset_rs1 "O\t0,i(1)"
234 #define rv_fmt_frd_offset_rs1 "O\t3,i(1)"
235 #define rv_fmt_rd_csr_rs1 "O\t0,c,1"
236 #define rv_fmt_rd_csr_zimm "O\t0,c,7"
237 #define rv_fmt_rs2_offset_rs1 "O\t2,i(1)"
238 #define rv_fmt_frs2_offset_rs1 "O\t5,i(1)"
239 #define rv_fmt_rs1_rs2_offset "O\t1,2,o"
240 #define rv_fmt_rs2_rs1_offset "O\t2,1,o"
241 #define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)"
242 #define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)"
243 #define rv_fmt_rd "O\t0"
244 #define rv_fmt_rd_zimm "O\t0,7"
245 #define rv_fmt_rd_rs1 "O\t0,1"
246 #define rv_fmt_rd_rs2 "O\t0,2"
247 #define rv_fmt_rs1_offset "O\t1,o"
248 #define rv_fmt_rs2_offset "O\t2,o"
249 #define rv_fmt_rs1_rs2_bs "O\t1,2,b"
250 #define rv_fmt_rd_rs1_rnum "O\t0,1,n"
251 #define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m"
252 #define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m"
253 #define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm"
254 #define rv_fmt_vd_vs2_vs1 "O\tD,F,E"
255 #define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El"
256 #define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em"
257 #define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l"
258 #define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l"
259 #define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m"
260 #define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
261 #define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
262 #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
263 #define rv_fmt_vd_vs2_uimm "O\tD,F,u"
264 #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
265 #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
266 #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
267 #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm"
268 #define rv_fmt_vd_vs1 "O\tD,E"
269 #define rv_fmt_vd_rs1 "O\tD,1"
270 #define rv_fmt_vd_fs1 "O\tD,4"
271 #define rv_fmt_vd_imm "O\tD,i"
272 #define rv_fmt_vd_vs2 "O\tD,F"
273 #define rv_fmt_vd_vs2_vm "O\tD,Fm"
274 #define rv_fmt_rd_vs2_vm "O\t0,Fm"
275 #define rv_fmt_rd_vs2 "O\t0,F"
276 #define rv_fmt_fd_vs2 "O\t3,F"
277 #define rv_fmt_vd_vm "O\tDm"
278 #define rv_fmt_vsetvli "O\t0,1,v"
279 #define rv_fmt_vsetivli "O\t0,i,v"
280 #define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)"
281 #define rv_fmt_push_rlist "O\tx,-i"
282 #define rv_fmt_pop_rlist "O\tx,i"
283 #define rv_fmt_zcmt_index "O\ti"
284 #define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i"
285 #define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i"
286 #define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j"
287 #define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
288 #define rv_fmt_rd2_imm "O\t0,2,(1),i"
289 #define rv_fmt_fli "O\t3,h"
290 #define rv_fmt_cmop "O.i"
291 #define rv_fmt_mop_r "O.i\t0,1"
292 #define rv_fmt_mop_rr "O.i\t0,1,2"
293
294 #endif /* DISAS_RISCV_H */