| 1 | .. SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | |
| 3 | .. _Hexagon-System-arch: |
| 4 | |
| 5 | Hexagon System Architecture |
| 6 | =========================== |
| 7 | |
| 8 | The hexagon architecture has some unique elements which are described here. |
| 9 | |
| 10 | Interrupts |
| 11 | ---------- |
| 12 | When interrupts arrive at a Hexagon DSP core, they are priority-steered to |
| 13 | be handled by an eligible hardware thread with the lowest priority. |
| 14 | |
| 15 | Memory |
| 16 | ------ |
| 17 | Each hardware thread has an ``SSR.ASID`` field that contains its Address |
| 18 | Space Identifier. This value is catenated with a 32-bit virtual address - |
| 19 | the MMU can then resolve this extended virtual address to a physical address. |
| 20 | |
| 21 | TLBs |
| 22 | ---- |
| 23 | The format of a TLB entry is shown below. |
| 24 | |
| 25 | .. note:: |
| 26 | The Small Core DSPs have a different TLB format which is not yet |
| 27 | supported. |
| 28 | |
| 29 | .. admonition:: Diagram |
| 30 | |
| 31 | .. code:: text |
| 32 | |
| 33 | 6 5 4 3 |
| 34 | 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 |
| 35 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 36 | |v|g|x|A|A| | | |
| 37 | |a|l|P|1|0| ASID | Virtual Page | |
| 38 | |l|b| | | | | | |
| 39 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 40 | |
| 41 | 3 2 1 0 |
| 42 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 43 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 44 | | | | | | | | | |
| 45 | |x|w|r|u|Cacheab| Physical Page |S| |
| 46 | | | | | | | | | |
| 47 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 48 | |
| 49 | |
| 50 | * ASID: the address-space identifier |
| 51 | * A1, A0: the behavior of these cache line attributes are not modeled by QEMU. |
| 52 | * xP: the extra-physical bit is the most significant physical address bit. |
| 53 | * S: the S bit and the LSBs of the physical page indicate the page size |
| 54 | * val: this is the 'valid' bit, when set it indicates that page matching |
| 55 | should consider this entry. |
| 56 | |
| 57 | .. list-table:: Page sizes |
| 58 | :widths: 25 25 50 |
| 59 | :header-rows: 1 |
| 60 | |
| 61 | * - S-bit |
| 62 | - Phys page LSBs |
| 63 | - Page size |
| 64 | * - 1 |
| 65 | - N/A |
| 66 | - 4kb |
| 67 | * - 0 |
| 68 | - 0b1 |
| 69 | - 16kb |
| 70 | * - 0 |
| 71 | - 0b10 |
| 72 | - 64kb |
| 73 | * - 0 |
| 74 | - 0b100 |
| 75 | - 256kb |
| 76 | * - 0 |
| 77 | - 0b1000 |
| 78 | - 1MB |
| 79 | * - 0 |
| 80 | - 0b10000 |
| 81 | - 4MB |
| 82 | * - 0 |
| 83 | - 0b100000 |
| 84 | - 16MB |
| 85 | |
| 86 | * glb: if the global bit is set, the ASID is not considered when matching |
| 87 | TLBs. |
| 88 | * Cacheab: the cacheability attributes of TLBs are not modeled, these bits |
| 89 | are ignored. |
| 90 | * RWX: read-, write-, execute-, enable bits. Indicates if user programs |
| 91 | are permitted to read/write/execute the given page. |
| 92 | * U: indicates if user programs can access this page. |
| 93 | |
| 94 | Scheduler |
| 95 | --------- |
| 96 | The Hexagon system architecture has a feature to assist the guest OS |
| 97 | task scheduler. The guest OS can enable this feature by setting |
| 98 | ``SCHEDCFG.EN``. The ``BESTWAIT`` register is programmed by the guest OS |
| 99 | to indicate the priority of the highest priority task waiting to run on a |
| 100 | hardware thread. The reschedule interrupt is triggered when any hardware |
| 101 | thread's priority in ``STID.PRIO`` is worse than the ``BESTWAIT``. When |
| 102 | it is triggered, the ``BESTWAIT.PRIO`` value is reset to 0x1ff. |
| 103 | |
| 104 | HVX Coprocessor |
| 105 | --------------- |
| 106 | The Supervisor Status Register field ``SSR.XA`` binds a DSP hardware thread |
| 107 | to one of the eight possible HVX contexts. The guest OS is responsible for |
| 108 | managing this resource. |
| 109 | |
| 110 | .. seealso:: |
| 111 | |
| 112 | ``target/hexagon/README`` in the QEMU source tree for more info about Hexagon. |