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1 QEMU<->ACPI BIOS CPU hotplug interface
2 ======================================
3
4 QEMU supports CPU hotplug via ACPI. This document
5 describes the interface between QEMU and the ACPI BIOS.
6
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
9
10
11 Modern ACPI CPU hotplug interface registers
12 -------------------------------------------
13
14 Register block base address:
15
16 - ICH9-LPC IO port 0x0cd8
17 - PIIX-PM IO port 0xaf00
18
19 Register block size:
20
21 - ACPI_CPU_HOTPLUG_REG_LEN = 12
22
23 All accesses to registers described below, imply little-endian byte order.
24
25 Reserved registers behavior:
26
27 - write accesses are ignored
28 - read accesses return all bits set to 0.
29
30 The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
31
32 - reads from any register return 0
33 - writes to any other register are ignored until valid value is stored into it
34
35 On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
36 keeps the current value.
37
38 Read access behavior
39 ^^^^^^^^^^^^^^^^^^^^
40
41 offset [0x0-0x3]
42 Command data 2: (DWORD access)
43
44 If value last stored in 'Command field' is:
45
46 0:
47 reads as 0x0
48 3:
49 upper 32 bits of architecture specific CPU ID value
50 other values:
51 reserved
52
53 offset [0x4]
54 CPU device status fields: (1 byte access)
55
56 bits:
57
58 0:
59 Device is enabled and may be used by guest
60 1:
61 Device insert event, used to distinguish device for which
62 no device check event to OSPM was issued.
63 It's valid only when bit 0 is set.
64 2:
65 Device remove event, used to distinguish device for which
66 no device eject request to OSPM was issued. Firmware must
67 ignore this bit.
68 3:
69 reserved and should be ignored by OSPM
70 4:
71 if set to 1, OSPM requests firmware to perform device eject.
72 5-7:
73 reserved and should be ignored by OSPM
74
75 offset [0x5-0x7]
76 reserved
77
78 offset [0x8]
79 Command data: (DWORD access)
80
81 If value last stored in 'Command field' is one of:
82
83 0:
84 contains 'CPU selector' value of a CPU with pending event[s]
85 3:
86 lower 32 bits of architecture specific CPU ID value
87 (in x86 case: APIC ID)
88 otherwise:
89 contains 0
90
91 Write access behavior
92 ^^^^^^^^^^^^^^^^^^^^^
93
94 offset [0x0-0x3]
95 CPU selector: (DWORD access)
96
97 Selects active CPU device. All following accesses to other
98 registers will read/store data from/to selected CPU.
99 Valid values: [0 .. max_cpus)
100
101 offset [0x4]
102 CPU device control fields: (1 byte access)
103
104 bits:
105
106 0:
107 reserved, OSPM must clear it before writing to register.
108 1:
109 if set to 1 clears device insert event, set by OSPM
110 after it has emitted device check event for the
111 selected CPU device
112 2:
113 if set to 1 clears device remove event, set by OSPM
114 after it has emitted device eject request for the
115 selected CPU device.
116 3:
117 if set to 1 initiates device eject, set by OSPM when it
118 triggers CPU device removal and calls _EJ0 method or by firmware
119 when bit #4 is set. In case bit #4 were set, it's cleared as
120 part of device eject.
121 4:
122 if set to 1, OSPM hands over device eject to firmware.
123 Firmware shall issue device eject request as described above
124 (bit #3) and OSPM should not touch device eject bit (#3) in case
125 it's asked firmware to perform CPU device eject.
126 5-7:
127 reserved, OSPM must clear them before writing to register
128
129 offset[0x5]
130 Command field: (1 byte access)
131
132 value:
133
134 0:
135 selects a CPU device with inserting/removing events and
136 following reads from 'Command data' register return
137 selected CPU ('CPU selector' value).
138 If no CPU with events found, the current 'CPU selector' doesn't
139 change and corresponding insert/remove event flags are not modified.
140
141 1:
142 following writes to 'Command data' register set OST event
143 register in QEMU
144 2:
145 following writes to 'Command data' register set OST status
146 register in QEMU
147 3:
148 following reads from 'Command data' and 'Command data 2' return
149 architecture specific CPU ID value for currently selected CPU.
150 other values:
151 reserved
152
153 offset [0x6-0x7]
154 reserved
155
156 offset [0x8]
157 Command data: (DWORD access)
158
159 If last stored 'Command field' value is:
160
161 1:
162 stores value into OST event register
163 2:
164 stores value into OST status register, triggers
165 ACPI_DEVICE_OST QMP event from QEMU to external applications
166 with current values of OST event and status registers.
167 other values:
168 reserved
169
170 Typical usecases
171 ----------------
172
173 (x86) Detecting and enabling modern CPU hotplug interface
174 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
175
176 QEMU starts with modern CPU hotplug interface enabled. Use following steps to
177 detect modern CPU hotplug interface:
178
179 #. Store 0x0 to the 'CPU selector' register, to ensure valid selector value
180 #. Store 0x0 to the 'Command field' register
181 #. Read the 'Command data 2' register.
182 If read value is 0x0, the modern interface is enabled.
183 Otherwise no CPU hotplug interface available
184
185 Get a cpu with pending event
186 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
187
188 #. Store 0x0 to the 'CPU selector' register.
189 #. Store 0x0 to the 'Command field' register.
190 #. Read the 'CPU device status fields' register.
191 #. If both bit #1 and bit #2 are clear in the value read, there is no CPU
192 with a pending event and selected CPU remains unchanged.
193 #. Otherwise, read the 'Command data' register. The value read is the
194 selector of the CPU with the pending event (which is already selected).
195
196 Enumerate CPUs present/non present CPUs
197 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
198
199 #. Set the present CPU count to 0.
200 #. Set the iterator to 0.
201 #. Store 0x0 to the 'CPU selector' register, to ensure that it's in
202 a valid state and that access to other registers won't be ignored.
203 #. Store 0x0 to the 'Command field' register to make 'Command data'
204 register return 'CPU selector' value of selected CPU
205 #. Read the 'CPU device status fields' register.
206 #. If bit #0 is set, increment the present CPU count.
207 #. Increment the iterator.
208 #. Store the iterator to the 'CPU selector' register.
209 #. Read the 'Command data' register.
210 #. If the value read is not zero, goto 05.
211 #. Otherwise store 0x0 to the 'CPU selector' register, to put it
212 into a valid state and exit.
213 The iterator at this point equals "max_cpus".