| 1 | =========================== |
| 2 | ASPEED Interrupt Controller |
| 3 | =========================== |
| 4 | |
| 5 | AST2700 |
| 6 | ------- |
| 7 | There are a total of 480 interrupt sources in AST2700. Due to the limitation of |
| 8 | interrupt numbers of processors, the interrupts are merged every 32 sources for |
| 9 | interrupt numbers greater than 127. |
| 10 | |
| 11 | There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO |
| 12 | (I/O Die). |
| 13 | |
| 14 | Interrupt Mapping |
| 15 | ----------------- |
| 16 | - INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO. |
| 17 | - INTCIO: Handles interrupt sources 128 - 319 independently. |
| 18 | |
| 19 | QEMU Support |
| 20 | ------------ |
| 21 | Currently, only GIC 192 to 201 are supported, and their source interrupts are |
| 22 | from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for |
| 23 | GIC 192-201. |
| 24 | |
| 25 | Design for GICINT 196 |
| 26 | --------------------- |
| 27 | The orgate has interrupt sources ranging from 0 to 31, with its output pin |
| 28 | connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC |
| 29 | "GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196. |
| 30 | |
| 31 | INTC GIC_192_201 Output Pin Mapping |
| 32 | ----------------------------------- |
| 33 | The design of INTC GIC_192_201 have 10 output pins, mapped as following: |
| 34 | |
| 35 | ==== ==== |
| 36 | Bit GIC |
| 37 | ==== ==== |
| 38 | 0 192 |
| 39 | 1 193 |
| 40 | 2 194 |
| 41 | 3 195 |
| 42 | 4 196 |
| 43 | 5 197 |
| 44 | 6 198 |
| 45 | 7 199 |
| 46 | 8 200 |
| 47 | 9 201 |
| 48 | ==== ==== |
| 49 | |
| 50 | Block Diagram of GICINT 196 for AST2700 A1 |
| 51 | ------------------------------------------------------------------------ |
| 52 | |
| 53 | .. code-block:: |
| 54 | |
| 55 | |-------------------------------------------------------------------------------------------------------| |
| 56 | | AST2700 A1 Design | |
| 57 | | To GICINT196 | |
| 58 | | | |
| 59 | | ETH1 |-----------| |--------------------------| |--------------| | |
| 60 | | ------->|0 | | INTCIO | | orgates[0] | | |
| 61 | | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | | |
| 62 | | ------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | | |
| 63 | | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | | |
| 64 | | ------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| | |
| 65 | | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | | |
| 66 | | ------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | | |
| 67 | | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | | |
| 68 | | ------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | | |
| 69 | | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | | |
| 70 | | ------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | | |
| 71 | | UART3 | 26| |--------------------------| |--------------| | | |
| 72 | | ------->|10 27| | | |
| 73 | | UART5 | 28| | | |
| 74 | | ------->|11 29| | | |
| 75 | | UART6 | | | | |
| 76 | | ------->|12 30| |-----------------------------------------------------------------------| | |
| 77 | | UART7 | 31| | | |
| 78 | | ------->|13 | | | |
| 79 | | UART8 | OR[0:31] | | |-----------------------------| |----------| | |
| 80 | | ------->|14 | | | INTC | | GIC | | |
| 81 | | UART9 | | | |inpin[0:0]--------->outpin[0]|--------->|192 | | |
| 82 | | ------->|15 | | |inpin[0:1]--------->outpin[1]|--------->|193 | | |
| 83 | | UART10 | | | |inpin[0:2]--------->outpin[2]|--------->|194 | | |
| 84 | | ------->|16 | | |inpin[0:3]--------->outpin[3]|--------->|195 | | |
| 85 | | UART11 | | |--------------> |inpin[0:4]--------->outpin[4]|--------->|196 | | |
| 86 | | ------->|17 | |inpin[0:5]--------->outpin[5]|--------->|197 | | |
| 87 | | UART12 | | |inpin[0:6]--------->outpin[6]|--------->|198 | | |
| 88 | | ------->|18 | |inpin[0:7]--------->outpin[7]|--------->|199 | | |
| 89 | | |-----------| |inpin[0:8]--------->outpin[8]|--------->|200 | | |
| 90 | | |inpin[0:9]--------->outpin[9]|--------->|201 | | |
| 91 | | |-----------------------------| |----------| | |
| 92 | | | |
| 93 | | | |
| 94 | |-------------------------------------------------------------------------------------------------------| |