| 1 | ==================== |
| 2 | QEMU PCI test device |
| 3 | ==================== |
| 4 | |
| 5 | ``pci-testdev`` is a device used for testing low level IO. |
| 6 | |
| 7 | The device implements up to three BARs: BAR0, BAR1 and BAR2. |
| 8 | Each of BAR 0+1 can be memory or IO. Guests must detect |
| 9 | BAR types and act accordingly. |
| 10 | |
| 11 | BAR 0+1 size is up to 4K bytes each. |
| 12 | BAR 0+1 starts with the following header: |
| 13 | |
| 14 | .. code-block:: c |
| 15 | |
| 16 | typedef struct PCITestDevHdr { |
| 17 | uint8_t test; /* write-only, starts a given test number */ |
| 18 | uint8_t width_type; /* |
| 19 | * read-only, type and width of access for a given test. |
| 20 | * 1,2,4 for byte,word or long write. |
| 21 | * any other value if test not supported on this BAR |
| 22 | */ |
| 23 | uint8_t pad0[2]; |
| 24 | uint32_t offset; /* read-only, offset in this BAR for a given test */ |
| 25 | uint32_t data; /* read-only, data to use for a given test */ |
| 26 | uint32_t count; /* for debugging. number of writes detected. */ |
| 27 | uint8_t name[]; /* for debugging. 0-terminated ASCII string. */ |
| 28 | } PCITestDevHdr; |
| 29 | |
| 30 | All registers are little endian. |
| 31 | |
| 32 | The device is expected to always implement tests 0 to N on each BAR, and to add new |
| 33 | tests with higher numbers. In this way a guest can scan test numbers until it |
| 34 | detects an access type that it does not support on this BAR, then stop. |
| 35 | |
| 36 | BAR2 is a 64bit memory BAR, without backing storage. It is disabled |
| 37 | by default and can be enabled using the ``membar=<size>`` property. This |
| 38 | can be used to test whether guests handle PCI BARs of a specific |
| 39 | (possibly quite large) size correctly. |