| 1 | Arm Musca boards (``musca-a``, ``musca-b1``) |
| 2 | ============================================ |
| 3 | |
| 4 | The Arm Musca development boards are a reference implementation |
| 5 | of a system using the SSE-200 Subsystem for Embedded. They are |
| 6 | dual Cortex-M33 systems. |
| 7 | |
| 8 | QEMU provides models of the A and B1 variants of this board. |
| 9 | |
| 10 | Unimplemented devices: |
| 11 | |
| 12 | - SPI |
| 13 | - |I2C| |
| 14 | - |I2S| |
| 15 | - PWM |
| 16 | - QSPI |
| 17 | - Timer |
| 18 | - SCC |
| 19 | - GPIO |
| 20 | - eFlash |
| 21 | - MHU |
| 22 | - PVT |
| 23 | - SDIO |
| 24 | - CryptoCell |
| 25 | |
| 26 | Note that (like the real hardware) the Musca-A machine is |
| 27 | asymmetric: CPU 0 does not have the FPU or DSP extensions, |
| 28 | but CPU 1 does. Also like the real hardware, the memory maps |
| 29 | for the A and B1 variants differ significantly, so guest |
| 30 | software must be built for the right variant. |
| 31 |