| 1 | CPU Features |
| 2 | ============ |
| 3 | |
| 4 | The QEMU emulation of the OpenRISC architecture provides following built in |
| 5 | features. |
| 6 | |
| 7 | - Shadow GPRs |
| 8 | - MMU TLB with 128 entries, 1 way |
| 9 | - Power Management (PM) |
| 10 | - Programmable Interrupt Controller (PIC) |
| 11 | - Tick Timer |
| 12 | |
| 13 | These features are on by default and the presence can be confirmed by checking |
| 14 | the contents of the Unit Presence Register (``UPR``) and CPU Configuration |
| 15 | Register (``CPUCFGR``). |