| 1 | OpenRISC 1000 CPU architecture support |
| 2 | ====================================== |
| 3 | |
| 4 | QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of |
| 5 | the OpenRISC 1000 cpu architecture. |
| 6 | |
| 7 | The or1200 cpu also has support for the following instruction subsets: |
| 8 | |
| 9 | - ORBIS32 (OpenRISC Basic Instruction Set) |
| 10 | - ORFPX32 (OpenRISC Floating-Point eXtension) |
| 11 | |
| 12 | In addition to the instruction subsets the QEMU TCG emulation also has support |
| 13 | for most Class II (optional) instructions. |
| 14 | |
| 15 | For information on all OpenRISC instructions please refer to the latest |
| 16 | architecture manual available on the OpenRISC website in the |
| 17 | `OpenRISC Architecture <https://openrisc.io/architecture>`_ section. |