| 1 | Boards for RISC-V Processors by MIPS |
| 2 | ==================================== |
| 3 | |
| 4 | RISC-V processors developed by MIPS support Boston-aia board model. The board |
| 5 | model supports up to 64 harts with MIPS CPS, MIPS GCR, MIPS CPC, AIA plic, |
| 6 | and AIA clint devices. The model can create boot code, if there is no |
| 7 | ```-bios``` parameter. Also, we can specify ```-smp x,cores=y,thread=z```. |
| 8 | |
| 9 | Running Linux kernel |
| 10 | -------------------- |
| 11 | |
| 12 | For example, to use 4 cores and 2 threads with each core to have 8 smp cpus, |
| 13 | that runs on the ```mips-p8700``` CPU, run qemu as follows: |
| 14 | |
| 15 | .. code-block:: bash |
| 16 | |
| 17 | qemu-system-riscv64 -cpu mips-p8700 \ |
| 18 | -m 2G -M boston-aia \ |
| 19 | -smp 8,cores=4,threads=2 -kernel fw_payload.bin \ |
| 20 | -drive file=rootfs.ext2,format=raw -serial stdio |