| 1 | .. SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | |
| 3 | .. _Hexagon-System-emulator: |
| 4 | |
| 5 | Hexagon System emulator |
| 6 | ----------------------- |
| 7 | |
| 8 | Use the ``qemu-system-hexagon`` executable to simulate a 32-bit Hexagon |
| 9 | machine. |
| 10 | |
| 11 | Hexagon Machines |
| 12 | ================ |
| 13 | |
| 14 | Hexagon DSPs are suited to various functions and generally appear in a |
| 15 | "DSP subsystem" of a larger system-on-chip (SoC). |
| 16 | |
| 17 | Hexagon DSPs are often included in a subsystem that looks like the diagram |
| 18 | below. Instructions are loaded into DDR before the DSP is brought out of |
| 19 | reset and the first instructions are fetched from DDR via the EVB/reset vector. |
| 20 | |
| 21 | In a real system, a TBU/SMMU would normally arbitrate AXI accesses but |
| 22 | we don't have a need to model that for QEMU. |
| 23 | |
| 24 | Hexagon DSP cores use simultaneous multithreading (SMT) with as many as 8 |
| 25 | hardware threads. |
| 26 | |
| 27 | .. admonition:: Diagram |
| 28 | |
| 29 | .. code:: text |
| 30 | |
| 31 | AHB (local) bus AXI (global) bus |
| 32 | │ │ |
| 33 | │ │ |
| 34 | ┌─────────┐ │ ┌─────────────────┐ │ |
| 35 | │ L2VIC ├──┤ │ │ │ |
| 36 | │ ├──┼───────► ├───────┤ |
| 37 | └─────▲───┘ │ │ Hexagon DSP │ │ |
| 38 | │ │ │ │ │ ┌─────┐ |
| 39 | │ │ │ N threads │ │ │ DDR │ |
| 40 | │ ├───────┤ │ │ │ │ |
| 41 | ┌────┴──┐ │ │ │ ├────────┤ │ |
| 42 | │QTimer ├───┤ │ │ │ │ │ |
| 43 | │ │ │ │ │ │ │ │ |
| 44 | └───────┘ │ │ ┌─────────┐ │ │ │ │ |
| 45 | │ │ ┌─────────┐│ │ │ │ │ |
| 46 | ┌───────┐ │ │ │ HVX xM ││ │ │ │ │ |
| 47 | │QDSP6SS├───┤ │ │ │┘ │ │ │ │ |
| 48 | └───────┘ │ │ └─────────┘ │ │ └─────┘ |
| 49 | │ │ │ │ |
| 50 | ┌───────┐ │ └─────────────────┘ │ |
| 51 | │ CSR ├───┤ |
| 52 | └───────┘ │ ┌──────┐ ┌───────────┐ |
| 53 | │ │ TCM │ │ VTCM │ |
| 54 | │ │ │ │ |
| 55 | └──────┘ │ │ |
| 56 | │ │ |
| 57 | │ │ |
| 58 | │ │ |
| 59 | └───────────┘ |
| 60 | |
| 61 | Components |
| 62 | ---------- |
| 63 | Other than l2vic and HVX, the components below are not implemented in QEMU. |
| 64 | |
| 65 | * L2VIC: the L2 vectored interrupt controller. Supports 1024 input |
| 66 | interrupts, edge- or level-triggered. The core ISA has system registers |
| 67 | ``VID``, ``VID1`` which read through to the L2VIC device. |
| 68 | * QTimer: ARMSSE-based programmable timer device. Its interrupts are |
| 69 | wired to the L2VIC. System registers ``TIMER``, ``UTIMER`` read |
| 70 | through to the QTimer device. |
| 71 | * QDSP6SS: DSP subsystem features, accessible to the entire SoC, including |
| 72 | DSP NMI, watchdog, reset, etc. |
| 73 | * CSR: Configuration/Status Registers. |
| 74 | * TCM: DSP-exclusive tightly-coupled memory. This memory can be used for |
| 75 | DSPs when isolated from DDR and in some bootstrapping modes. |
| 76 | * VTCM: DSP-exclusive vector tightly-coupled memory. This memory is accessed |
| 77 | by some HVX instructions. |
| 78 | * HVX: the vector coprocessor supports 64 and 128-byte vector registers. |
| 79 | 64-byte mode is not implemented in QEMU. |
| 80 | |
| 81 | |
| 82 | Bootstrapping |
| 83 | ------------- |
| 84 | Hexagon systems do not generally have access to a block device. So, for |
| 85 | QEMU the typical use case involves loading a binary or ELF file into memory |
| 86 | and executing from the indicated start address:: |
| 87 | |
| 88 | $ qemu-system-hexagon -kernel ./prog -append 'arg1 arg2' |
| 89 | |
| 90 | Semihosting |
| 91 | ----------- |
| 92 | Hexagon supports a semihosting interface similar to other architectures'. |
| 93 | The ``trap0`` instruction can activate these semihosting calls so that the |
| 94 | guest software can access the host console and filesystem. Semihosting |
| 95 | is not yet implemented in QEMU hexagon. |
| 96 | |
| 97 | |
| 98 | Hexagon Features |
| 99 | ================ |
| 100 | .. toctree:: |
| 101 | hexagon/emulation |
| 102 | hexagon/cdsp |
| 103 |