| 1 | /* |
| 2 | * ACPI implementation |
| 3 | * |
| 4 | * Copyright (c) 2006 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License version 2.1 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This library is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * Lesser General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU Lesser General Public |
| 16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
| 17 | * |
| 18 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 19 | * GNU GPL, version 2 or (at your option) any later version. |
| 20 | */ |
| 21 | |
| 22 | #include "qemu/osdep.h" |
| 23 | #include "hw/core/irq.h" |
| 24 | #include "hw/isa/apm.h" |
| 25 | #include "hw/i2c/pm_smbus.h" |
| 26 | #include "hw/pci/pci.h" |
| 27 | #include "hw/core/qdev-properties.h" |
| 28 | #include "hw/acpi/acpi.h" |
| 29 | #include "hw/acpi/pcihp.h" |
| 30 | #include "hw/acpi/piix4.h" |
| 31 | #include "system/runstate.h" |
| 32 | #include "system/system.h" |
| 33 | #include "system/xen.h" |
| 34 | #include "qapi/error.h" |
| 35 | #include "qemu/range.h" |
| 36 | #include "hw/acpi/cpu.h" |
| 37 | #include "hw/core/hotplug.h" |
| 38 | #include "hw/mem/pc-dimm.h" |
| 39 | #include "hw/mem/nvdimm.h" |
| 40 | #include "hw/acpi/memory_hotplug.h" |
| 41 | #include "hw/acpi/acpi_dev_interface.h" |
| 42 | #include "migration/vmstate.h" |
| 43 | #include "hw/core/cpu.h" |
| 44 | #include "qom/object.h" |
| 45 | #include "hw/acpi/pc-hotplug.h" |
| 46 | |
| 47 | #define GPE_BASE 0xafe0 |
| 48 | #define GPE_LEN 4 |
| 49 | |
| 50 | #define ACPI_PCIHP_ADDR_PIIX4 0xae00 |
| 51 | |
| 52 | struct pci_status { |
| 53 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
| 54 | uint32_t down; |
| 55 | }; |
| 56 | |
| 57 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
| 58 | PCIBus *bus, PIIX4PMState *s); |
| 59 | |
| 60 | #define ACPI_ENABLE 0xf1 |
| 61 | #define ACPI_DISABLE 0xf0 |
| 62 | |
| 63 | static void pm_tmr_timer(ACPIREGS *ar) |
| 64 | { |
| 65 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
| 66 | acpi_update_sci(&s->ar, s->irq); |
| 67 | } |
| 68 | |
| 69 | static void apm_ctrl_changed(uint32_t val, void *arg) |
| 70 | { |
| 71 | PIIX4PMState *s = arg; |
| 72 | PCIDevice *d = PCI_DEVICE(s); |
| 73 | |
| 74 | /* ACPI specs 3.0, 4.7.2.5 */ |
| 75 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
| 76 | if (val == ACPI_ENABLE || val == ACPI_DISABLE) { |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | if (d->config[0x5b] & (1 << 1)) { |
| 81 | if (s->smi_irq) { |
| 82 | qemu_irq_raise(s->smi_irq); |
| 83 | } |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | static void pm_io_space_update(PIIX4PMState *s) |
| 88 | { |
| 89 | PCIDevice *d = PCI_DEVICE(s); |
| 90 | |
| 91 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
| 92 | s->io_base &= 0xffc0; |
| 93 | |
| 94 | memory_region_transaction_begin(); |
| 95 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
| 96 | memory_region_set_address(&s->io, s->io_base); |
| 97 | memory_region_transaction_commit(); |
| 98 | } |
| 99 | |
| 100 | static void smbus_io_space_update(PIIX4PMState *s) |
| 101 | { |
| 102 | PCIDevice *d = PCI_DEVICE(s); |
| 103 | |
| 104 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); |
| 105 | s->smb_io_base &= 0xffc0; |
| 106 | |
| 107 | memory_region_transaction_begin(); |
| 108 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
| 109 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
| 110 | memory_region_transaction_commit(); |
| 111 | } |
| 112 | |
| 113 | static void pm_write_config(PCIDevice *d, |
| 114 | uint32_t address, uint32_t val, int len) |
| 115 | { |
| 116 | pci_default_write_config(d, address, val, len); |
| 117 | if (range_covers_byte(address, len, 0x80) || |
| 118 | ranges_overlap(address, len, 0x40, 4)) { |
| 119 | pm_io_space_update((PIIX4PMState *)d); |
| 120 | } |
| 121 | if (range_covers_byte(address, len, 0xd2) || |
| 122 | ranges_overlap(address, len, 0x90, 4)) { |
| 123 | smbus_io_space_update((PIIX4PMState *)d); |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
| 128 | { |
| 129 | PIIX4PMState *s = opaque; |
| 130 | |
| 131 | pm_io_space_update(s); |
| 132 | smbus_io_space_update(s); |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
| 137 | { \ |
| 138 | .name = (stringify(_field)), \ |
| 139 | .version_id = 0, \ |
| 140 | .info = &vmstate_info_uint16, \ |
| 141 | .size = sizeof(uint16_t), \ |
| 142 | .flags = VMS_SINGLE | VMS_POINTER, \ |
| 143 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
| 144 | } |
| 145 | |
| 146 | static const VMStateDescription vmstate_gpe = { |
| 147 | .name = "gpe", |
| 148 | .version_id = 1, |
| 149 | .minimum_version_id = 1, |
| 150 | .fields = (const VMStateField[]) { |
| 151 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
| 152 | VMSTATE_GPE_ARRAY(en, ACPIGPE), |
| 153 | VMSTATE_END_OF_LIST() |
| 154 | } |
| 155 | }; |
| 156 | |
| 157 | static const VMStateDescription vmstate_pci_status = { |
| 158 | .name = "pci_status", |
| 159 | .version_id = 1, |
| 160 | .minimum_version_id = 1, |
| 161 | .fields = (const VMStateField[]) { |
| 162 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
| 163 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), |
| 164 | VMSTATE_END_OF_LIST() |
| 165 | } |
| 166 | }; |
| 167 | |
| 168 | static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) |
| 169 | { |
| 170 | PIIX4PMState *s = opaque; |
| 171 | return s->acpi_pci_hotplug.use_acpi_hotplug_bridge; |
| 172 | } |
| 173 | |
| 174 | static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, |
| 175 | int version_id) |
| 176 | { |
| 177 | PIIX4PMState *s = opaque; |
| 178 | return !s->acpi_pci_hotplug.use_acpi_hotplug_bridge; |
| 179 | } |
| 180 | |
| 181 | static bool vmstate_test_use_memhp(void *opaque) |
| 182 | { |
| 183 | PIIX4PMState *s = opaque; |
| 184 | return s->acpi_memory_hotplug.is_enabled; |
| 185 | } |
| 186 | |
| 187 | static const VMStateDescription vmstate_memhp_state = { |
| 188 | .name = "piix4_pm/memhp", |
| 189 | .version_id = 1, |
| 190 | .minimum_version_id = 1, |
| 191 | .needed = vmstate_test_use_memhp, |
| 192 | .fields = (const VMStateField[]) { |
| 193 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), |
| 194 | VMSTATE_END_OF_LIST() |
| 195 | } |
| 196 | }; |
| 197 | |
| 198 | static bool cpuhp_needed(void *opaque) |
| 199 | { |
| 200 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
| 201 | |
| 202 | return mc->has_hotpluggable_cpus; |
| 203 | } |
| 204 | |
| 205 | static const VMStateDescription vmstate_cpuhp_state = { |
| 206 | .name = "piix4_pm/cpuhp", |
| 207 | .version_id = 1, |
| 208 | .minimum_version_id = 1, |
| 209 | .needed = cpuhp_needed, |
| 210 | .fields = (const VMStateField[]) { |
| 211 | VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), |
| 212 | VMSTATE_END_OF_LIST() |
| 213 | } |
| 214 | }; |
| 215 | |
| 216 | /* |
| 217 | * This is a fudge to turn off the acpi_index field, |
| 218 | * whose test was always broken on piix4 with 6.2 and older machine types. |
| 219 | */ |
| 220 | static bool vmstate_test_migrate_acpi_index(void *opaque, int version_id) |
| 221 | { |
| 222 | PIIX4PMState *s = PIIX4_PM(opaque); |
| 223 | return s->acpi_pci_hotplug.use_acpi_hotplug_bridge && |
| 224 | !s->not_migrate_acpi_index; |
| 225 | } |
| 226 | |
| 227 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
| 228 | * To support incoming qemu-kvm 1.2 migration, change version_id |
| 229 | * and minimum_version_id to 2 below (which breaks migration from |
| 230 | * qemu 1.2). |
| 231 | * |
| 232 | */ |
| 233 | static const VMStateDescription vmstate_acpi = { |
| 234 | .name = "piix4_pm", |
| 235 | .version_id = 3, |
| 236 | .minimum_version_id = 3, |
| 237 | .post_load = vmstate_acpi_post_load, |
| 238 | .fields = (const VMStateField[]) { |
| 239 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
| 240 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
| 241 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), |
| 242 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), |
| 243 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
| 244 | VMSTATE_STRUCT(smb, PIIX4PMState, 3, pmsmb_vmstate, PMSMBus), |
| 245 | VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), |
| 246 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
| 247 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), |
| 248 | VMSTATE_STRUCT_TEST( |
| 249 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], |
| 250 | PIIX4PMState, |
| 251 | vmstate_test_no_use_acpi_hotplug_bridge, |
| 252 | 2, vmstate_pci_status, |
| 253 | struct AcpiPciHpPciStatus), |
| 254 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
| 255 | vmstate_test_use_acpi_hotplug_bridge, |
| 256 | vmstate_test_migrate_acpi_index), |
| 257 | VMSTATE_END_OF_LIST() |
| 258 | }, |
| 259 | .subsections = (const VMStateDescription * const []) { |
| 260 | &vmstate_memhp_state, |
| 261 | &vmstate_cpuhp_state, |
| 262 | NULL |
| 263 | } |
| 264 | }; |
| 265 | |
| 266 | static void piix4_pm_reset(DeviceState *dev) |
| 267 | { |
| 268 | PIIX4PMState *s = PIIX4_PM(dev); |
| 269 | PCIDevice *d = PCI_DEVICE(s); |
| 270 | uint8_t *pci_conf = d->config; |
| 271 | |
| 272 | pci_conf[0x58] = 0; |
| 273 | pci_conf[0x59] = 0; |
| 274 | pci_conf[0x5a] = 0; |
| 275 | pci_conf[0x5b] = 0; |
| 276 | |
| 277 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
| 278 | pci_conf[0x80] = 0; |
| 279 | |
| 280 | if (!s->smm_enabled) { |
| 281 | /* Mark SMM as already inited (until KVM supports SMM). */ |
| 282 | pci_conf[0x5B] = 0x02; |
| 283 | } |
| 284 | |
| 285 | acpi_pm1_evt_reset(&s->ar); |
| 286 | acpi_pm1_cnt_reset(&s->ar); |
| 287 | acpi_pm_tmr_reset(&s->ar); |
| 288 | acpi_gpe_reset(&s->ar); |
| 289 | acpi_update_sci(&s->ar, s->irq); |
| 290 | |
| 291 | pm_io_space_update(s); |
| 292 | if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || |
| 293 | s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { |
| 294 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
| 299 | { |
| 300 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
| 301 | |
| 302 | assert(s != NULL); |
| 303 | acpi_pm1_evt_power_down(&s->ar); |
| 304 | } |
| 305 | |
| 306 | static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
| 307 | DeviceState *dev, Error **errp) |
| 308 | { |
| 309 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
| 310 | |
| 311 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
| 312 | acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); |
| 313 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
| 314 | if (!s->acpi_memory_hotplug.is_enabled) { |
| 315 | error_setg(errp, |
| 316 | "memory hotplug is not enabled: %s.memory-hotplug-support " |
| 317 | "is not set", object_get_typename(OBJECT(s))); |
| 318 | } |
| 319 | } else if ( |
| 320 | !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
| 321 | error_setg(errp, "acpi: device pre plug request for not supported" |
| 322 | " device type: %s", object_get_typename(OBJECT(dev))); |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, |
| 327 | DeviceState *dev, Error **errp) |
| 328 | { |
| 329 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
| 330 | |
| 331 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
| 332 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
| 333 | nvdimm_acpi_plug_cb(hotplug_dev, dev); |
| 334 | } else { |
| 335 | acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, |
| 336 | dev, errp); |
| 337 | } |
| 338 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
| 339 | acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); |
| 340 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
| 341 | acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); |
| 342 | } else { |
| 343 | g_assert_not_reached(); |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
| 348 | DeviceState *dev, Error **errp) |
| 349 | { |
| 350 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
| 351 | |
| 352 | if (s->acpi_memory_hotplug.is_enabled && |
| 353 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
| 354 | acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, |
| 355 | dev, errp); |
| 356 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
| 357 | acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, |
| 358 | dev, errp); |
| 359 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
| 360 | acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); |
| 361 | } else { |
| 362 | error_setg(errp, "acpi: device unplug request for not supported device" |
| 363 | " type: %s", object_get_typename(OBJECT(dev))); |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, |
| 368 | DeviceState *dev, Error **errp) |
| 369 | { |
| 370 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
| 371 | |
| 372 | if (s->acpi_memory_hotplug.is_enabled && |
| 373 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
| 374 | acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); |
| 375 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
| 376 | acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, |
| 377 | errp); |
| 378 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
| 379 | acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); |
| 380 | } else { |
| 381 | error_setg(errp, "acpi: device unplug for not supported device" |
| 382 | " type: %s", object_get_typename(OBJECT(dev))); |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | static bool piix4_is_hotpluggable_bus(HotplugHandler *hotplug_dev, |
| 387 | BusState *bus) |
| 388 | { |
| 389 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
| 390 | return acpi_pcihp_is_hotpluggable_bus(&s->acpi_pci_hotplug, bus); |
| 391 | } |
| 392 | |
| 393 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
| 394 | { |
| 395 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); |
| 396 | PCIDevice *d = PCI_DEVICE(s); |
| 397 | MemoryRegion *io_as = pci_address_space_io(d); |
| 398 | uint8_t *pci_conf; |
| 399 | |
| 400 | pci_conf = d->config; |
| 401 | pci_conf[0x5f] = 0x10 | |
| 402 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
| 403 | pci_conf[0x63] = 0x60; |
| 404 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
| 405 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); |
| 406 | } |
| 407 | |
| 408 | static void piix4_pm_add_class_properties(ObjectClass *oc) |
| 409 | { |
| 410 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; |
| 411 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; |
| 412 | static const uint32_t gpe0_blk = GPE_BASE; |
| 413 | static const uint32_t gpe0_blk_len = GPE_LEN; |
| 414 | static const uint16_t sci_int = 9; |
| 415 | |
| 416 | object_class_static_property_add_uint8_ptr(oc, |
| 417 | ACPI_PM_PROP_ACPI_ENABLE_CMD, |
| 418 | &acpi_enable_cmd, |
| 419 | OBJ_PROP_FLAG_READ); |
| 420 | object_class_static_property_add_uint8_ptr(oc, |
| 421 | ACPI_PM_PROP_ACPI_DISABLE_CMD, |
| 422 | &acpi_disable_cmd, |
| 423 | OBJ_PROP_FLAG_READ); |
| 424 | object_class_static_property_add_uint32_ptr(oc, |
| 425 | ACPI_PM_PROP_GPE0_BLK, |
| 426 | &gpe0_blk, |
| 427 | OBJ_PROP_FLAG_READ); |
| 428 | object_class_static_property_add_uint32_ptr(oc, |
| 429 | ACPI_PM_PROP_GPE0_BLK_LEN, |
| 430 | &gpe0_blk_len, |
| 431 | OBJ_PROP_FLAG_READ); |
| 432 | object_class_static_property_add_uint16_ptr(oc, |
| 433 | ACPI_PM_PROP_SCI_INT, |
| 434 | &sci_int, |
| 435 | OBJ_PROP_FLAG_READ); |
| 436 | object_class_property_add_uint32_ptr(oc, |
| 437 | ACPI_PM_PROP_PM_IO_BASE, |
| 438 | offsetof(PIIX4PMState, io_base), |
| 439 | OBJ_PROP_FLAG_READ); |
| 440 | } |
| 441 | |
| 442 | static void piix4_pm_realize(PCIDevice *dev, Error **errp) |
| 443 | { |
| 444 | PIIX4PMState *s = PIIX4_PM(dev); |
| 445 | uint8_t *pci_conf; |
| 446 | |
| 447 | pci_conf = dev->config; |
| 448 | pci_conf[0x06] = 0x80; |
| 449 | pci_conf[0x07] = 0x02; |
| 450 | pci_conf[0x09] = 0x00; |
| 451 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
| 452 | |
| 453 | /* APM */ |
| 454 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
| 455 | |
| 456 | if (!s->smm_enabled) { |
| 457 | /* Mark SMM as already inited to prevent SMM from running. KVM does not |
| 458 | * support SMM mode. */ |
| 459 | pci_conf[0x5B] = 0x02; |
| 460 | } |
| 461 | |
| 462 | /* XXX: which specification is used ? The i82731AB has different |
| 463 | mappings */ |
| 464 | pci_conf[0x90] = s->smb_io_base | 1; |
| 465 | pci_conf[0x91] = s->smb_io_base >> 8; |
| 466 | pci_conf[0xd2] = 0x09; |
| 467 | pm_smbus_init(DEVICE(dev), &s->smb, true); |
| 468 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
| 469 | memory_region_add_subregion(pci_address_space_io(dev), |
| 470 | s->smb_io_base, &s->smb.io); |
| 471 | |
| 472 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
| 473 | memory_region_set_enabled(&s->io, false); |
| 474 | memory_region_add_subregion(pci_address_space_io(dev), |
| 475 | 0, &s->io); |
| 476 | |
| 477 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
| 478 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
| 479 | acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val, |
| 480 | !s->smm_compat && !s->smm_enabled); |
| 481 | acpi_gpe_init(&s->ar, GPE_LEN); |
| 482 | |
| 483 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
| 484 | qemu_register_powerdown_notifier(&s->powerdown_notifier); |
| 485 | |
| 486 | s->machine_ready.notify = piix4_pm_machine_ready; |
| 487 | qemu_add_machine_init_done_notifier(&s->machine_ready); |
| 488 | |
| 489 | if (xen_enabled()) { |
| 490 | s->acpi_pci_hotplug.use_acpi_hotplug_bridge = false; |
| 491 | } |
| 492 | |
| 493 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), |
| 494 | pci_get_bus(dev), s); |
| 495 | } |
| 496 | |
| 497 | static void piix4_pm_init(Object *obj) |
| 498 | { |
| 499 | PIIX4PMState *s = PIIX4_PM(obj); |
| 500 | |
| 501 | qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); |
| 502 | qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1); |
| 503 | } |
| 504 | |
| 505 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
| 506 | { |
| 507 | PIIX4PMState *s = opaque; |
| 508 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
| 509 | |
| 510 | return val; |
| 511 | } |
| 512 | |
| 513 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
| 514 | unsigned width) |
| 515 | { |
| 516 | PIIX4PMState *s = opaque; |
| 517 | |
| 518 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
| 519 | acpi_update_sci(&s->ar, s->irq); |
| 520 | } |
| 521 | |
| 522 | static const MemoryRegionOps piix4_gpe_ops = { |
| 523 | .read = gpe_readb, |
| 524 | .write = gpe_writeb, |
| 525 | .valid.min_access_size = 1, |
| 526 | .valid.max_access_size = 4, |
| 527 | .impl.min_access_size = 1, |
| 528 | .impl.max_access_size = 1, |
| 529 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 530 | }; |
| 531 | |
| 532 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
| 533 | PCIBus *bus, PIIX4PMState *s) |
| 534 | { |
| 535 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
| 536 | "acpi-gpe0", GPE_LEN); |
| 537 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
| 538 | |
| 539 | if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || |
| 540 | s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { |
| 541 | object_property_set_link(OBJECT(s), "bus", OBJECT(bus), &error_abort); |
| 542 | acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, parent, |
| 543 | ACPI_PCIHP_ADDR_PIIX4); |
| 544 | qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); |
| 545 | } |
| 546 | |
| 547 | cpu_hotplug_hw_init(parent, OBJECT(s), &s->cpuhp_state, |
| 548 | PIIX4_CPU_HOTPLUG_IO_BASE); |
| 549 | |
| 550 | if (s->acpi_memory_hotplug.is_enabled) { |
| 551 | acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, |
| 552 | ACPI_MEMORY_HOTPLUG_BASE); |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
| 557 | { |
| 558 | PIIX4PMState *s = PIIX4_PM(adev); |
| 559 | |
| 560 | acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); |
| 561 | acpi_cpu_ospm_status(&s->cpuhp_state, list); |
| 562 | } |
| 563 | |
| 564 | static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
| 565 | { |
| 566 | PIIX4PMState *s = PIIX4_PM(adev); |
| 567 | |
| 568 | acpi_send_gpe_event(&s->ar, s->irq, ev); |
| 569 | } |
| 570 | |
| 571 | static const Property piix4_pm_properties[] = { |
| 572 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), |
| 573 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), |
| 574 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), |
| 575 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), |
| 576 | DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState, |
| 577 | acpi_pci_hotplug.use_acpi_hotplug_bridge, true), |
| 578 | DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState, |
| 579 | acpi_pci_hotplug.use_acpi_root_pci_hotplug, true), |
| 580 | DEFINE_PROP_LINK("bus", PIIX4PMState, acpi_pci_hotplug.root, |
| 581 | TYPE_PCI_BUS, PCIBus *), |
| 582 | DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, |
| 583 | acpi_memory_hotplug.is_enabled, true), |
| 584 | DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), |
| 585 | DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false), |
| 586 | DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState, |
| 587 | not_migrate_acpi_index, false), |
| 588 | }; |
| 589 | |
| 590 | static void piix4_pm_class_init(ObjectClass *klass, const void *data) |
| 591 | { |
| 592 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 593 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 594 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
| 595 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
| 596 | |
| 597 | k->realize = piix4_pm_realize; |
| 598 | k->config_write = pm_write_config; |
| 599 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 600 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; |
| 601 | k->revision = 0x03; |
| 602 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
| 603 | device_class_set_legacy_reset(dc, piix4_pm_reset); |
| 604 | dc->desc = "PM"; |
| 605 | dc->vmsd = &vmstate_acpi; |
| 606 | device_class_set_props(dc, piix4_pm_properties); |
| 607 | /* |
| 608 | * Reason: part of PIIX4 southbridge, needs to be wired up, |
| 609 | * e.g. by mips_malta_init() |
| 610 | */ |
| 611 | dc->user_creatable = false; |
| 612 | dc->hotpluggable = false; |
| 613 | hc->pre_plug = piix4_device_pre_plug_cb; |
| 614 | hc->plug = piix4_device_plug_cb; |
| 615 | hc->unplug_request = piix4_device_unplug_request_cb; |
| 616 | hc->unplug = piix4_device_unplug_cb; |
| 617 | hc->is_hotpluggable_bus = piix4_is_hotpluggable_bus; |
| 618 | adevc->ospm_status = piix4_ospm_status; |
| 619 | adevc->send_event = piix4_send_gpe; |
| 620 | |
| 621 | object_class_property_add_uint16_ptr(klass, ACPI_PCIHP_IO_BASE_PROP, |
| 622 | offsetof(PIIX4PMState, |
| 623 | acpi_pci_hotplug.io_base), |
| 624 | OBJ_PROP_FLAG_READ); |
| 625 | object_class_property_add_uint16_ptr(klass, ACPI_PCIHP_IO_LEN_PROP, |
| 626 | offsetof(PIIX4PMState, |
| 627 | acpi_pci_hotplug.io_len), |
| 628 | OBJ_PROP_FLAG_READ); |
| 629 | |
| 630 | piix4_pm_add_class_properties(klass); |
| 631 | } |
| 632 | |
| 633 | static const TypeInfo piix4_pm_info = { |
| 634 | .name = TYPE_PIIX4_PM, |
| 635 | .parent = TYPE_PCI_DEVICE, |
| 636 | .instance_init = piix4_pm_init, |
| 637 | .instance_size = sizeof(PIIX4PMState), |
| 638 | .class_init = piix4_pm_class_init, |
| 639 | .interfaces = (const InterfaceInfo[]) { |
| 640 | { TYPE_HOTPLUG_HANDLER }, |
| 641 | { TYPE_ACPI_DEVICE_IF }, |
| 642 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 643 | { } |
| 644 | } |
| 645 | }; |
| 646 | |
| 647 | static void piix4_pm_register_types(void) |
| 648 | { |
| 649 | type_register_static(&piix4_pm_info); |
| 650 | } |
| 651 | |
| 652 | type_init(piix4_pm_register_types) |