| 1 | /* |
| 2 | * OpenPOWER Palmetto BMC |
| 3 | * |
| 4 | * Andrew Jeffery <andrew@aj.id.au> |
| 5 | * |
| 6 | * Copyright 2016 IBM Corp. |
| 7 | * |
| 8 | * This code is licensed under the GPL version 2 or later. See |
| 9 | * the COPYING file in the top-level directory. |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | #include "qapi/error.h" |
| 14 | #include "hw/arm/boot.h" |
| 15 | #include "hw/arm/aspeed.h" |
| 16 | #include "hw/arm/aspeed_soc.h" |
| 17 | #include "hw/arm/machines-qom.h" |
| 18 | #include "hw/block/flash.h" |
| 19 | #include "hw/gpio/pca9552.h" |
| 20 | #include "hw/gpio/pca9554.h" |
| 21 | #include "system/block-backend.h" |
| 22 | #include "qemu/error-report.h" |
| 23 | #include "qemu/units.h" |
| 24 | #include "hw/core/qdev-clock.h" |
| 25 | #include "system/system.h" |
| 26 | |
| 27 | #define AST_SMP_MAILBOX_BASE 0x1e6e2180 |
| 28 | #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) |
| 29 | #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) |
| 30 | #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) |
| 31 | #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) |
| 32 | #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) |
| 33 | #define AST_SMP_MBOX_GOSIGN 0xabbaab00 |
| 34 | |
| 35 | static void aspeed_write_smpboot(ARMCPU *cpu, |
| 36 | const struct arm_boot_info *info) |
| 37 | { |
| 38 | AddressSpace *as = arm_boot_address_space(cpu, info); |
| 39 | static const ARMInsnFixup poll_mailbox_ready[] = { |
| 40 | /* |
| 41 | * r2 = per-cpu go sign value |
| 42 | * r1 = AST_SMP_MBOX_FIELD_ENTRY |
| 43 | * r0 = AST_SMP_MBOX_FIELD_GOSIGN |
| 44 | */ |
| 45 | { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ |
| 46 | { 0xe21000ff }, /* ands r0, r0, #255 */ |
| 47 | { 0xe59f201c }, /* ldr r2, [pc, #28] */ |
| 48 | { 0xe1822000 }, /* orr r2, r2, r0 */ |
| 49 | |
| 50 | { 0xe59f1018 }, /* ldr r1, [pc, #24] */ |
| 51 | { 0xe59f0018 }, /* ldr r0, [pc, #24] */ |
| 52 | |
| 53 | { 0xe320f002 }, /* wfe */ |
| 54 | { 0xe5904000 }, /* ldr r4, [r0] */ |
| 55 | { 0xe1520004 }, /* cmp r2, r4 */ |
| 56 | { 0x1afffffb }, /* bne <wfe> */ |
| 57 | { 0xe591f000 }, /* ldr pc, [r1] */ |
| 58 | { AST_SMP_MBOX_GOSIGN }, |
| 59 | { AST_SMP_MBOX_FIELD_ENTRY }, |
| 60 | { AST_SMP_MBOX_FIELD_GOSIGN }, |
| 61 | { 0, FIXUP_TERMINATOR } |
| 62 | }; |
| 63 | static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; |
| 64 | |
| 65 | arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, |
| 66 | poll_mailbox_ready, fixupcontext); |
| 67 | } |
| 68 | |
| 69 | static void aspeed_reset_secondary(ARMCPU *cpu, |
| 70 | const struct arm_boot_info *info) |
| 71 | { |
| 72 | AddressSpace *as = arm_boot_address_space(cpu, info); |
| 73 | CPUState *cs = CPU(cpu); |
| 74 | |
| 75 | /* info->smp_bootreg_addr */ |
| 76 | address_space_stl(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, |
| 77 | MEMTXATTRS_UNSPECIFIED, NULL); |
| 78 | cpu_set_pc(cs, info->smp_loader_start); |
| 79 | } |
| 80 | |
| 81 | static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, |
| 82 | bool boot_emmc) |
| 83 | { |
| 84 | DeviceState *card; |
| 85 | |
| 86 | if (!dinfo) { |
| 87 | return; |
| 88 | } |
| 89 | card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); |
| 90 | |
| 91 | /* |
| 92 | * Force the boot properties of the eMMC device only when the |
| 93 | * machine is strapped to boot from eMMC. Without these |
| 94 | * settings, the machine would not boot. |
| 95 | * |
| 96 | * This also allows the machine to use an eMMC device without |
| 97 | * boot areas when booting from the flash device (or -kernel) |
| 98 | * Ideally, the device and its properties should be defined on |
| 99 | * the command line. |
| 100 | */ |
| 101 | if (emmc && boot_emmc) { |
| 102 | qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); |
| 103 | qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); |
| 104 | } |
| 105 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), |
| 106 | &error_fatal); |
| 107 | qdev_realize_and_unref(card, |
| 108 | qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), |
| 109 | &error_fatal); |
| 110 | } |
| 111 | |
| 112 | void aspeed_connect_serial_hds_to_uarts(AspeedMachineState *bmc) |
| 113 | { |
| 114 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| 115 | AspeedSoCState *s = bmc->soc; |
| 116 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 117 | int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; |
| 118 | |
| 119 | aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base, |
| 120 | sc->uarts_num, serial_hd(0)); |
| 121 | for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { |
| 122 | if (uart == uart_chosen) { |
| 123 | continue; |
| 124 | } |
| 125 | aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_num, |
| 126 | serial_hd(i++)); |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static void aspeed_machine_init(MachineState *machine) |
| 131 | { |
| 132 | AspeedMachineState *bmc = ASPEED_MACHINE(machine); |
| 133 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
| 134 | AspeedSoCClass *sc; |
| 135 | int i; |
| 136 | const char *bios_name = NULL; |
| 137 | DriveInfo *emmc0 = NULL; |
| 138 | bool boot_emmc; |
| 139 | |
| 140 | bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); |
| 141 | object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); |
| 142 | object_unref(OBJECT(bmc->soc)); |
| 143 | sc = ASPEED_SOC_GET_CLASS(bmc->soc); |
| 144 | |
| 145 | /* |
| 146 | * This will error out if the RAM size is not supported by the |
| 147 | * memory controller of the SoC. |
| 148 | */ |
| 149 | object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, |
| 150 | &error_fatal); |
| 151 | |
| 152 | for (i = 0; i < sc->macs_num; i++) { |
| 153 | if ((amc->macs_mask & (1 << i)) && |
| 154 | !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), |
| 155 | true, NULL)) { |
| 156 | break; /* No configs left; stop asking */ |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, |
| 161 | &error_abort); |
| 162 | object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, |
| 163 | &error_abort); |
| 164 | object_property_set_link(OBJECT(bmc->soc), "memory", |
| 165 | OBJECT(get_system_memory()), &error_abort); |
| 166 | object_property_set_link(OBJECT(bmc->soc), "dram", |
| 167 | OBJECT(machine->ram), &error_abort); |
| 168 | if (amc->sdhci_wp_inverted) { |
| 169 | for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { |
| 170 | object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), |
| 171 | "wp-inverted", true, &error_abort); |
| 172 | } |
| 173 | } |
| 174 | if (machine->kernel_filename) { |
| 175 | /* |
| 176 | * When booting with a -kernel command line there is no u-boot |
| 177 | * that runs to unlock the SCU. In this case set the default to |
| 178 | * be unlocked as the kernel expects |
| 179 | */ |
| 180 | object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", |
| 181 | ASPEED_SCU_PROT_KEY, &error_abort); |
| 182 | } |
| 183 | aspeed_connect_serial_hds_to_uarts(bmc); |
| 184 | qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); |
| 185 | |
| 186 | if (defaults_enabled()) { |
| 187 | aspeed_board_init_flashes(&bmc->soc->fmc, |
| 188 | bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, |
| 189 | amc->num_cs, 0); |
| 190 | aspeed_board_init_flashes(&bmc->soc->spi[0], |
| 191 | bmc->spi_model ? bmc->spi_model : amc->spi_model, |
| 192 | 1, amc->num_cs); |
| 193 | aspeed_board_init_flashes(&bmc->soc->spi[1], |
| 194 | amc->spi2_model, 1, amc->num_cs2); |
| 195 | } |
| 196 | |
| 197 | if (machine->kernel_filename && sc->num_cpus > 1) { |
| 198 | /* With no u-boot we must set up a boot stub for the secondary CPU */ |
| 199 | MemoryRegion *smpboot = g_new(MemoryRegion, 1); |
| 200 | memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", |
| 201 | 0x80, &error_abort); |
| 202 | memory_region_add_subregion(get_system_memory(), |
| 203 | AST_SMP_MAILBOX_BASE, smpboot); |
| 204 | |
| 205 | bmc->bootinfo.write_secondary_boot = aspeed_write_smpboot; |
| 206 | bmc->bootinfo.secondary_cpu_reset_hook = aspeed_reset_secondary; |
| 207 | bmc->bootinfo.smp_loader_start = AST_SMP_MBOX_CODE; |
| 208 | } |
| 209 | |
| 210 | bmc->bootinfo.board_id = -1; /* device-tree-only board */ |
| 211 | bmc->bootinfo.ram_size = machine->ram_size; |
| 212 | bmc->bootinfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; |
| 213 | |
| 214 | if (amc->i2c_init) { |
| 215 | amc->i2c_init(bmc); |
| 216 | } |
| 217 | |
| 218 | for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { |
| 219 | sdhci_attach_drive(&bmc->soc->sdhci.slots[i], |
| 220 | drive_get(IF_SD, 0, i), false, false); |
| 221 | } |
| 222 | |
| 223 | boot_emmc = sc->boot_from_emmc(bmc->soc); |
| 224 | |
| 225 | if (bmc->soc->emmc.num_slots && defaults_enabled()) { |
| 226 | emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); |
| 227 | sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); |
| 228 | } |
| 229 | |
| 230 | if (!bmc->mmio_exec) { |
| 231 | DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); |
| 232 | BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; |
| 233 | |
| 234 | if (fmc0 && !boot_emmc) { |
| 235 | uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); |
| 236 | aspeed_install_boot_rom(bmc->soc, fmc0, &bmc->boot_rom, rom_size); |
| 237 | } else if (emmc0) { |
| 238 | aspeed_install_boot_rom(bmc->soc, blk_by_legacy_dinfo(emmc0), |
| 239 | &bmc->boot_rom, 64 * KiB); |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | if (amc->vbootrom) { |
| 244 | bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; |
| 245 | aspeed_load_vbootrom(bmc->soc, bios_name, &error_abort); |
| 246 | } |
| 247 | |
| 248 | arm_load_kernel(ARM_CPU(first_cpu), machine, &bmc->bootinfo); |
| 249 | } |
| 250 | |
| 251 | void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr) |
| 252 | { |
| 253 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), |
| 254 | TYPE_PCA9552, addr); |
| 255 | } |
| 256 | |
| 257 | I2CSlave *aspeed_create_pca9554(AspeedSoCState *soc, int bus_id, int addr) |
| 258 | { |
| 259 | return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), |
| 260 | TYPE_PCA9554, addr); |
| 261 | } |
| 262 | |
| 263 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) |
| 264 | { |
| 265 | return ASPEED_MACHINE(obj)->mmio_exec; |
| 266 | } |
| 267 | |
| 268 | static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) |
| 269 | { |
| 270 | ASPEED_MACHINE(obj)->mmio_exec = value; |
| 271 | } |
| 272 | |
| 273 | static void aspeed_machine_instance_init(Object *obj) |
| 274 | { |
| 275 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); |
| 276 | |
| 277 | ASPEED_MACHINE(obj)->mmio_exec = false; |
| 278 | ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; |
| 279 | } |
| 280 | |
| 281 | static char *aspeed_get_fmc_model(Object *obj, Error **errp) |
| 282 | { |
| 283 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 284 | return g_strdup(bmc->fmc_model); |
| 285 | } |
| 286 | |
| 287 | static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) |
| 288 | { |
| 289 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 290 | |
| 291 | g_free(bmc->fmc_model); |
| 292 | bmc->fmc_model = g_strdup(value); |
| 293 | } |
| 294 | |
| 295 | static char *aspeed_get_spi_model(Object *obj, Error **errp) |
| 296 | { |
| 297 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 298 | return g_strdup(bmc->spi_model); |
| 299 | } |
| 300 | |
| 301 | static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) |
| 302 | { |
| 303 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 304 | |
| 305 | g_free(bmc->spi_model); |
| 306 | bmc->spi_model = g_strdup(value); |
| 307 | } |
| 308 | |
| 309 | static char *aspeed_get_bmc_console(Object *obj, Error **errp) |
| 310 | { |
| 311 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 312 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| 313 | int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; |
| 314 | |
| 315 | return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); |
| 316 | } |
| 317 | |
| 318 | static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) |
| 319 | { |
| 320 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 321 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| 322 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); |
| 323 | int val; |
| 324 | int uart_first = aspeed_uart_first(sc->uarts_base); |
| 325 | int uart_last = aspeed_uart_last(sc->uarts_base, sc->uarts_num); |
| 326 | |
| 327 | if (sscanf(value, "uart%d", &val) != 1 || val < 0) { |
| 328 | error_setg(errp, "Bad value for \"uart\" property"); |
| 329 | return; |
| 330 | } |
| 331 | |
| 332 | /* The number of UART depends on the SoC */ |
| 333 | if (val < uart_first || val > uart_last) { |
| 334 | error_setg(errp, "\"uart\" should be in range [%d - %d]", |
| 335 | uart_first, uart_last); |
| 336 | return; |
| 337 | } |
| 338 | bmc->uart_chosen = val + ASPEED_DEV_UART0; |
| 339 | } |
| 340 | |
| 341 | static void aspeed_machine_class_props_init(ObjectClass *oc) |
| 342 | { |
| 343 | object_class_property_add_bool(oc, "execute-in-place", |
| 344 | aspeed_get_mmio_exec, |
| 345 | aspeed_set_mmio_exec); |
| 346 | object_class_property_set_description(oc, "execute-in-place", |
| 347 | "boot directly from CE0 flash device"); |
| 348 | |
| 349 | object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, |
| 350 | aspeed_set_bmc_console); |
| 351 | object_class_property_set_description(oc, "bmc-console", |
| 352 | "Change the default UART to \"uartX\""); |
| 353 | |
| 354 | object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, |
| 355 | aspeed_set_fmc_model); |
| 356 | object_class_property_set_description(oc, "fmc-model", |
| 357 | "Change the FMC Flash model"); |
| 358 | object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, |
| 359 | aspeed_set_spi_model); |
| 360 | object_class_property_set_description(oc, "spi-model", |
| 361 | "Change the SPI Flash model"); |
| 362 | } |
| 363 | |
| 364 | void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) |
| 365 | { |
| 366 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); |
| 367 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); |
| 368 | |
| 369 | mc->default_cpus = sc->num_cpus; |
| 370 | mc->min_cpus = sc->num_cpus; |
| 371 | mc->max_cpus = sc->num_cpus; |
| 372 | mc->valid_cpu_types = sc->valid_cpu_types; |
| 373 | } |
| 374 | |
| 375 | static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) |
| 376 | { |
| 377 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 378 | |
| 379 | return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); |
| 380 | } |
| 381 | |
| 382 | static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, |
| 383 | Error **errp) |
| 384 | { |
| 385 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 386 | |
| 387 | if (value) { |
| 388 | bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; |
| 389 | } else { |
| 390 | bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) |
| 395 | { |
| 396 | object_class_property_add_bool(oc, "boot-emmc", |
| 397 | aspeed_machine_ast2600_get_boot_from_emmc, |
| 398 | aspeed_machine_ast2600_set_boot_from_emmc); |
| 399 | object_class_property_set_description(oc, "boot-emmc", |
| 400 | "Set or unset boot from EMMC"); |
| 401 | } |
| 402 | |
| 403 | static void aspeed_machine_class_init(ObjectClass *oc, const void *data) |
| 404 | { |
| 405 | MachineClass *mc = MACHINE_CLASS(oc); |
| 406 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| 407 | |
| 408 | mc->init = aspeed_machine_init; |
| 409 | mc->no_floppy = 1; |
| 410 | mc->no_cdrom = 1; |
| 411 | mc->no_parallel = 1; |
| 412 | mc->default_ram_id = "ram"; |
| 413 | amc->macs_mask = ASPEED_MAC0_ON; |
| 414 | amc->uart_default = ASPEED_DEV_UART5; |
| 415 | |
| 416 | aspeed_machine_class_props_init(oc); |
| 417 | } |
| 418 | |
| 419 | static void aspeed_machine_instance_finalize(Object *obj) |
| 420 | { |
| 421 | AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| 422 | |
| 423 | g_free(bmc->fmc_model); |
| 424 | g_free(bmc->spi_model); |
| 425 | } |
| 426 | |
| 427 | static const TypeInfo aspeed_machine_types[] = { |
| 428 | { |
| 429 | .name = TYPE_ASPEED_MACHINE, |
| 430 | .parent = TYPE_MACHINE, |
| 431 | .instance_size = sizeof(AspeedMachineState), |
| 432 | .instance_init = aspeed_machine_instance_init, |
| 433 | .instance_finalize = aspeed_machine_instance_finalize, |
| 434 | .class_size = sizeof(AspeedMachineClass), |
| 435 | .class_init = aspeed_machine_class_init, |
| 436 | .abstract = true, |
| 437 | } |
| 438 | }; |
| 439 | |
| 440 | DEFINE_TYPES(aspeed_machine_types) |