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1 /*
2 * ASPEED Ast10x0 SoC
3 *
4 * Copyright (C) 2022 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * Implementation extracted from the AST2600 and adapted for Ast10x0.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "system/address-spaces.h"
15 #include "system/system.h"
16 #include "hw/core/qdev-clock.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19
20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
21
22 static const hwaddr aspeed_soc_ast1030_memmap[] = {
23 [ASPEED_DEV_SRAM0] = 0x00000000,
24 [ASPEED_DEV_SRAM1] = 0x79000000, /* SEC SRAM */
25 [ASPEED_DEV_IOMEM] = 0x7E600000,
26 [ASPEED_DEV_PWM] = 0x7E610000,
27 [ASPEED_DEV_FMC] = 0x7E620000,
28 [ASPEED_DEV_SPI1] = 0x7E630000,
29 [ASPEED_DEV_SPI2] = 0x7E640000,
30 [ASPEED_DEV_UDC] = 0x7E6A2000,
31 [ASPEED_DEV_HACE] = 0x7E6D0000,
32 [ASPEED_DEV_SCU] = 0x7E6E2000,
33 [ASPEED_DEV_JTAG0] = 0x7E6E4000,
34 [ASPEED_DEV_JTAG1] = 0x7E6E4100,
35 [ASPEED_DEV_ADC] = 0x7E6E9000,
36 [ASPEED_DEV_ESPI] = 0x7E6EE000,
37 [ASPEED_DEV_SBC] = 0x7E6F2000,
38 [ASPEED_DEV_GPIO] = 0x7E780000,
39 [ASPEED_DEV_SGPIOM0] = 0x7E780500,
40 [ASPEED_DEV_TIMER1] = 0x7E782000,
41 [ASPEED_DEV_UART1] = 0x7E783000,
42 [ASPEED_DEV_UART2] = 0x7E78D000,
43 [ASPEED_DEV_UART3] = 0x7E78E000,
44 [ASPEED_DEV_UART4] = 0x7E78F000,
45 [ASPEED_DEV_UART5] = 0x7E784000,
46 [ASPEED_DEV_UART6] = 0x7E790000,
47 [ASPEED_DEV_UART7] = 0x7E790100,
48 [ASPEED_DEV_UART8] = 0x7E790200,
49 [ASPEED_DEV_UART9] = 0x7E790300,
50 [ASPEED_DEV_UART10] = 0x7E790400,
51 [ASPEED_DEV_UART11] = 0x7E790500,
52 [ASPEED_DEV_UART12] = 0x7E790600,
53 [ASPEED_DEV_UART13] = 0x7E790700,
54 [ASPEED_DEV_WDT] = 0x7E785000,
55 [ASPEED_DEV_LPC] = 0x7E789000,
56 [ASPEED_DEV_PECI] = 0x7E78B000,
57 [ASPEED_DEV_I3C] = 0x7E7A0000,
58 [ASPEED_DEV_I2C] = 0x7E7B0000,
59 };
60
61 static const int aspeed_soc_ast1030_irqmap[] = {
62 [ASPEED_DEV_UART1] = 47,
63 [ASPEED_DEV_UART2] = 48,
64 [ASPEED_DEV_UART3] = 49,
65 [ASPEED_DEV_UART4] = 50,
66 [ASPEED_DEV_UART5] = 8,
67 [ASPEED_DEV_UART6] = 57,
68 [ASPEED_DEV_UART7] = 58,
69 [ASPEED_DEV_UART8] = 59,
70 [ASPEED_DEV_UART9] = 60,
71 [ASPEED_DEV_UART10] = 61,
72 [ASPEED_DEV_UART11] = 62,
73 [ASPEED_DEV_UART12] = 63,
74 [ASPEED_DEV_UART13] = 64,
75 [ASPEED_DEV_GPIO] = 11,
76 [ASPEED_DEV_TIMER1] = 16,
77 [ASPEED_DEV_TIMER2] = 17,
78 [ASPEED_DEV_TIMER3] = 18,
79 [ASPEED_DEV_TIMER4] = 19,
80 [ASPEED_DEV_TIMER5] = 20,
81 [ASPEED_DEV_TIMER6] = 21,
82 [ASPEED_DEV_TIMER7] = 22,
83 [ASPEED_DEV_TIMER8] = 23,
84 [ASPEED_DEV_WDT] = 24,
85 [ASPEED_DEV_LPC] = 35,
86 [ASPEED_DEV_PECI] = 38,
87 [ASPEED_DEV_FMC] = 39,
88 [ASPEED_DEV_ESPI] = 42,
89 [ASPEED_DEV_PWM] = 44,
90 [ASPEED_DEV_ADC] = 46,
91 [ASPEED_DEV_SPI1] = 65,
92 [ASPEED_DEV_SPI2] = 66,
93 [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
94 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
95 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
96 [ASPEED_DEV_UDC] = 9,
97 [ASPEED_DEV_SGPIOM0] = 51,
98 [ASPEED_DEV_JTAG0] = 27,
99 [ASPEED_DEV_JTAG1] = 53,
100 };
101
102 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
103 {
104 Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
105 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
106
107 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
108 }
109
110 static void aspeed_soc_ast10x0_init(Object *obj, const char *socname)
111 {
112 Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
113 AspeedSoCState *s = ASPEED_SOC(obj);
114 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
115 char typename[64];
116 int i;
117
118 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
119
120 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
121
122 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
123 object_initialize_child(obj, "scu", &s->scu, typename);
124 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
125
126 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
127 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
128
129 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
130 object_initialize_child(obj, "i2c", &s->i2c, typename);
131
132 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
133
134 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
135 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
136
137 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
138 object_initialize_child(obj, "adc", &s->adc, typename);
139
140 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
141 object_initialize_child(obj, "fmc", &s->fmc, typename);
142
143 for (i = 0; i < sc->spis_num; i++) {
144 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
145 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
146 }
147
148 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC);
149
150 for (i = 0; i < sc->wdts_num; i++) {
151 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
152 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
153 }
154
155 for (i = 0; i < sc->uarts_num; i++) {
156 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
157 }
158
159 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
160 object_initialize_child(obj, "gpio", &s->gpio, typename);
161
162 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
163 object_initialize_child(obj, "hace", &s->hace, typename);
164
165 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
166 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
167 TYPE_UNIMPLEMENTED_DEVICE);
168 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
169 object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
170 object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
171 object_initialize_child(obj, "sgpiom", &s->sgpiom,
172 TYPE_UNIMPLEMENTED_DEVICE);
173 object_initialize_child(obj, "jtag[0]", &s->jtag[0],
174 TYPE_UNIMPLEMENTED_DEVICE);
175 object_initialize_child(obj, "jtag[1]", &s->jtag[1],
176 TYPE_UNIMPLEMENTED_DEVICE);
177 }
178
179 static void aspeed_soc_ast1030_init(Object *obj)
180 {
181 AspeedSoCState *s = ASPEED_SOC(obj);
182
183 aspeed_soc_ast10x0_init(obj, "ast1030");
184 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
185 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
186 }
187
188 static void aspeed_soc_ast1060_init(Object *obj)
189 {
190 /*
191 * The AST1060 SoC reuses the AST1030 device models. Since all peripheral
192 * models (e.g. WDT, SCU, TIMER, HACE, ADC, I2C, FMC, SPI) defined for
193 * AST1030 are compatible with AST1060, we simply reuse the existing
194 * AST1030 models for AST1060.
195 *
196 * To simplify the implementation, AST1060 sets its socname to that of
197 * AST1030, avoiding the need to create a full set of new
198 * TYPE_ASPEED_1060_XXX device definitions. This allows the same
199 * TYPE_ASPEED_1030_WDT and other models to be instantiated for both
200 * SoCs.
201 */
202 aspeed_soc_ast10x0_init(obj, "ast1030");
203 }
204
205 static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp)
206 {
207 AspeedSoCState *s = ASPEED_SOC(a);
208 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
209 DeviceState *armv7m;
210 Error *err = NULL;
211 int uart;
212 int i;
213 g_autofree char *sram_name = NULL;
214
215 if (!clock_has_source(s->sysclk)) {
216 error_setg(errp, "sysclk clock must be wired up by the board code");
217 return false;
218 }
219
220 /* General I/O memory space to catch all unimplemented device */
221 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
222 "aspeed.io",
223 sc->memmap[ASPEED_DEV_IOMEM],
224 ASPEED_SOC_IOMEM_SIZE);
225 aspeed_mmio_map_unimplemented(s->memory,
226 SYS_BUS_DEVICE(&s->sbc_unimplemented),
227 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
228 0x40000);
229
230 /* AST10x0 CPU Core */
231 armv7m = DEVICE(&a->armv7m);
232 qdev_prop_set_uint32(armv7m, "num-irq", 256);
233 qdev_prop_set_string(armv7m, "cpu-type",
234 aspeed_soc_cpu_type(sc->valid_cpu_types));
235 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
236 object_property_set_link(OBJECT(&a->armv7m), "memory",
237 OBJECT(s->memory), &error_abort);
238 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
239
240 /* Internal SRAM */
241 sram_name = g_strdup_printf("aspeed.sram.%d",
242 CPU(a->armv7m.cpu)->cpu_index);
243 memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
244 sc->sram_size[0], &err);
245 if (err != NULL) {
246 error_propagate(errp, err);
247 return false;
248 }
249 memory_region_add_subregion(s->memory,
250 sc->memmap[ASPEED_DEV_SRAM0],
251 &s->sram[0]);
252
253 /* Internal SEC SRAM */
254 memory_region_init_ram(&s->sram[1], OBJECT(s), "sec.sram",
255 sc->sram_size[1], &err);
256 if (err != NULL) {
257 error_propagate(errp, err);
258 return false;
259 }
260 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
261 &s->sram[1]);
262
263 /* SCU */
264 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
265 return false;
266 }
267 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
268 sc->memmap[ASPEED_DEV_SCU]);
269
270 /* I2C */
271
272 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
273 &error_abort);
274 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
275 return false;
276 }
277 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
278 sc->memmap[ASPEED_DEV_I2C]);
279 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
280 qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
281 sc->irqmap[ASPEED_DEV_I2C] + i);
282 /* The AST1030 I2C controller has one IRQ per bus. */
283 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
284 }
285
286 /* I3C */
287 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
288 return false;
289 }
290 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0,
291 sc->memmap[ASPEED_DEV_I3C]);
292 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
293 qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
294 sc->irqmap[ASPEED_DEV_I3C] + i);
295 /* The AST1030 I3C controller has one IRQ per bus. */
296 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
297 }
298
299 /* UART */
300 for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
301 if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
302 sc->memmap[uart], errp)) {
303 return false;
304 }
305 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
306 aspeed_soc_ast1030_get_irq(s, uart));
307 }
308
309 /* Timer */
310 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
311 &error_abort);
312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
313 return false;
314 }
315 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
316 sc->memmap[ASPEED_DEV_TIMER1]);
317 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
318 qemu_irq irq = aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_TIMER1 + i);
319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
320 }
321
322 /* ADC */
323 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
324 return false;
325 }
326 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
327 sc->memmap[ASPEED_DEV_ADC]);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
329 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_ADC));
330
331 /* FMC, The number of CS is set at the board level */
332 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
333 &error_abort);
334 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
335 return false;
336 }
337 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
338 sc->memmap[ASPEED_DEV_FMC]);
339 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
340 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
342 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_FMC));
343
344 /* SPI */
345 for (i = 0; i < sc->spis_num; i++) {
346 object_property_set_link(OBJECT(&s->spi[i]), "dram",
347 OBJECT(&s->sram), &error_abort);
348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
349 return false;
350 }
351 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
352 sc->memmap[ASPEED_DEV_SPI1 + i]);
353 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
354 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
356 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 + i));
357 }
358
359 /* Secure Boot Controller */
360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
361 return false;
362 }
363 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0,
364 sc->memmap[ASPEED_DEV_SBC]);
365
366 /* HACE */
367 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
368 &error_abort);
369 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
370 return false;
371 }
372 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
373 sc->memmap[ASPEED_DEV_HACE]);
374 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
375 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_HACE));
376
377 /* Watch dog */
378 for (i = 0; i < sc->wdts_num; i++) {
379 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
380 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
381
382 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
383 &error_abort);
384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
385 return false;
386 }
387 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
388 }
389
390 /* GPIO */
391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
392 return false;
393 }
394 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
395 sc->memmap[ASPEED_DEV_GPIO]);
396 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
397 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_GPIO));
398
399 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),
400 "aspeed.pwm",
401 sc->memmap[ASPEED_DEV_PWM], 0x100);
402
403 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),
404 "aspeed.espi",
405 sc->memmap[ASPEED_DEV_ESPI], 0x800);
406
407 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),
408 "aspeed.udc",
409 sc->memmap[ASPEED_DEV_UDC], 0x1000);
410 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom),
411 "aspeed.sgpiom",
412 sc->memmap[ASPEED_DEV_SGPIOM0], 0x100);
413
414 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),
415 "aspeed.jtag",
416 sc->memmap[ASPEED_DEV_JTAG0], 0x20);
417 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),
418 "aspeed.jtag",
419 sc->memmap[ASPEED_DEV_JTAG1], 0x20);
420
421 return true;
422 }
423
424 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
425 {
426 Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
427 AspeedSoCState *s = ASPEED_SOC(dev_soc);
428 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
429
430 if (!aspeed_soc_ast10x0_realize(a, errp)) {
431 return;
432 }
433
434 /* PECI */
435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
436 return;
437 }
438 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
439 sc->memmap[ASPEED_DEV_PECI]);
440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
441 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI));
442
443 /* LPC */
444 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
445 return;
446 }
447 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
448 sc->memmap[ASPEED_DEV_LPC]);
449
450 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
452 aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC));
453
454 /*
455 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
456 */
457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
458 qdev_get_gpio_in(DEVICE(&a->armv7m),
459 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
460
461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
462 qdev_get_gpio_in(DEVICE(&a->armv7m),
463 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
464
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
466 qdev_get_gpio_in(DEVICE(&a->armv7m),
467 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
468
469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
470 qdev_get_gpio_in(DEVICE(&a->armv7m),
471 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
472 }
473
474 static void aspeed_soc_ast1060_realize(DeviceState *dev_soc, Error **errp)
475 {
476 Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
477
478 if (!aspeed_soc_ast10x0_realize(a, errp)) {
479 return;
480 }
481 }
482
483 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *data)
484 {
485 static const char * const valid_cpu_types[] = {
486 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
487 NULL
488 };
489 DeviceClass *dc = DEVICE_CLASS(klass);
490 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
491
492 /* Reason: The Aspeed SoC can only be instantiated from a board */
493 dc->user_creatable = false;
494 dc->realize = aspeed_soc_ast1030_realize;
495
496 sc->valid_cpu_types = valid_cpu_types;
497 sc->silicon_rev = AST1030_A1_SILICON_REV;
498 sc->sram_size[0] = 0xc0000;
499 sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
500 sc->spis_num = 2;
501 sc->ehcis_num = 0;
502 sc->wdts_num = 4;
503 sc->macs_num = 1;
504 sc->uarts_num = 13;
505 sc->uarts_base = ASPEED_DEV_UART1;
506 sc->irqmap = aspeed_soc_ast1030_irqmap;
507 sc->memmap = aspeed_soc_ast1030_memmap;
508 sc->num_cpus = 1;
509 }
510
511 static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *data)
512 {
513 static const char * const valid_cpu_types[] = {
514 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
515 NULL
516 };
517 DeviceClass *dc = DEVICE_CLASS(klass);
518 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
519
520 /* Reason: The Aspeed SoC can only be instantiated from a board */
521 dc->user_creatable = false;
522 dc->realize = aspeed_soc_ast1060_realize;
523
524 sc->valid_cpu_types = valid_cpu_types;
525 sc->silicon_rev = AST1060_A2_SILICON_REV;
526 sc->sram_size[0] = 0xc0000;
527 sc->sram_size[1] = 0x40000; /* SEC SRAM 256 * KiB */
528 sc->spis_num = 2;
529 sc->wdts_num = 4;
530 sc->uarts_num = 1;
531 sc->uarts_base = ASPEED_DEV_UART5;
532 sc->irqmap = aspeed_soc_ast1030_irqmap;
533 sc->memmap = aspeed_soc_ast1030_memmap;
534 sc->num_cpus = 1;
535 }
536
537 static const TypeInfo aspeed_soc_ast10x0_types[] = {
538 {
539 .name = TYPE_ASPEED10X0_SOC,
540 .parent = TYPE_ASPEED_SOC,
541 .instance_size = sizeof(Aspeed10x0SoCState),
542 .abstract = true,
543 }, {
544 .name = "ast1030-a1",
545 .parent = TYPE_ASPEED10X0_SOC,
546 .instance_init = aspeed_soc_ast1030_init,
547 .class_init = aspeed_soc_ast1030_class_init,
548 }, {
549 .name = "ast1060-a2",
550 .parent = TYPE_ASPEED10X0_SOC,
551 .instance_init = aspeed_soc_ast1060_init,
552 .class_init = aspeed_soc_ast1060_class_init,
553 }
554 };
555
556 DEFINE_TYPES(aspeed_soc_ast10x0_types)