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1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qapi/error.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial-mm.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
22 #include "net/net.h"
23 #include "system/system.h"
24 #include "target/arm/cpu-qom.h"
25
26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27
28 static const hwaddr aspeed_soc_ast2400_memmap[] = {
29 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
30 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_VIC] = 0x1E6C0000,
35 [ASPEED_DEV_SDMC] = 0x1E6E0000,
36 [ASPEED_DEV_SCU] = 0x1E6E2000,
37 [ASPEED_DEV_HACE] = 0x1E6E3000,
38 [ASPEED_DEV_XDMA] = 0x1E6E7000,
39 [ASPEED_DEV_VIDEO] = 0x1E700000,
40 [ASPEED_DEV_ADC] = 0x1E6E9000,
41 [ASPEED_DEV_SRAM0] = 0x1E720000,
42 [ASPEED_DEV_SDHCI] = 0x1E740000,
43 [ASPEED_DEV_GPIO] = 0x1E780000,
44 [ASPEED_DEV_RTC] = 0x1E781000,
45 [ASPEED_DEV_TIMER1] = 0x1E782000,
46 [ASPEED_DEV_WDT] = 0x1E785000,
47 [ASPEED_DEV_PWM] = 0x1E786000,
48 [ASPEED_DEV_LPC] = 0x1E789000,
49 [ASPEED_DEV_IBT] = 0x1E789140,
50 [ASPEED_DEV_I2C] = 0x1E78A000,
51 [ASPEED_DEV_PECI] = 0x1E78B000,
52 [ASPEED_DEV_ETH1] = 0x1E660000,
53 [ASPEED_DEV_ETH2] = 0x1E680000,
54 [ASPEED_DEV_UART1] = 0x1E783000,
55 [ASPEED_DEV_UART2] = 0x1E78D000,
56 [ASPEED_DEV_UART3] = 0x1E78E000,
57 [ASPEED_DEV_UART4] = 0x1E78F000,
58 [ASPEED_DEV_UART5] = 0x1E784000,
59 [ASPEED_DEV_VUART] = 0x1E787000,
60 [ASPEED_DEV_SDRAM] = 0x40000000,
61 };
62
63 static const hwaddr aspeed_soc_ast2500_memmap[] = {
64 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
65 [ASPEED_DEV_IOMEM] = 0x1E600000,
66 [ASPEED_DEV_FMC] = 0x1E620000,
67 [ASPEED_DEV_SPI1] = 0x1E630000,
68 [ASPEED_DEV_SPI2] = 0x1E631000,
69 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
70 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
71 [ASPEED_DEV_VIC] = 0x1E6C0000,
72 [ASPEED_DEV_SDMC] = 0x1E6E0000,
73 [ASPEED_DEV_SCU] = 0x1E6E2000,
74 [ASPEED_DEV_HACE] = 0x1E6E3000,
75 [ASPEED_DEV_XDMA] = 0x1E6E7000,
76 [ASPEED_DEV_ADC] = 0x1E6E9000,
77 [ASPEED_DEV_VIDEO] = 0x1E700000,
78 [ASPEED_DEV_SRAM0] = 0x1E720000,
79 [ASPEED_DEV_SDHCI] = 0x1E740000,
80 [ASPEED_DEV_GPIO] = 0x1E780000,
81 [ASPEED_DEV_RTC] = 0x1E781000,
82 [ASPEED_DEV_TIMER1] = 0x1E782000,
83 [ASPEED_DEV_WDT] = 0x1E785000,
84 [ASPEED_DEV_PWM] = 0x1E786000,
85 [ASPEED_DEV_LPC] = 0x1E789000,
86 [ASPEED_DEV_IBT] = 0x1E789140,
87 [ASPEED_DEV_I2C] = 0x1E78A000,
88 [ASPEED_DEV_PECI] = 0x1E78B000,
89 [ASPEED_DEV_ETH1] = 0x1E660000,
90 [ASPEED_DEV_ETH2] = 0x1E680000,
91 [ASPEED_DEV_UART1] = 0x1E783000,
92 [ASPEED_DEV_UART2] = 0x1E78D000,
93 [ASPEED_DEV_UART3] = 0x1E78E000,
94 [ASPEED_DEV_UART4] = 0x1E78F000,
95 [ASPEED_DEV_UART5] = 0x1E784000,
96 [ASPEED_DEV_VUART] = 0x1E787000,
97 [ASPEED_DEV_SDRAM] = 0x80000000,
98 };
99
100 static const int aspeed_soc_ast2400_irqmap[] = {
101 [ASPEED_DEV_UART1] = 9,
102 [ASPEED_DEV_UART2] = 32,
103 [ASPEED_DEV_UART3] = 33,
104 [ASPEED_DEV_UART4] = 34,
105 [ASPEED_DEV_UART5] = 10,
106 [ASPEED_DEV_VUART] = 8,
107 [ASPEED_DEV_FMC] = 19,
108 [ASPEED_DEV_EHCI1] = 5,
109 [ASPEED_DEV_EHCI2] = 13,
110 [ASPEED_DEV_SDMC] = 0,
111 [ASPEED_DEV_SCU] = 21,
112 [ASPEED_DEV_ADC] = 31,
113 [ASPEED_DEV_GPIO] = 20,
114 [ASPEED_DEV_RTC] = 22,
115 [ASPEED_DEV_TIMER1] = 16,
116 [ASPEED_DEV_TIMER2] = 17,
117 [ASPEED_DEV_TIMER3] = 18,
118 [ASPEED_DEV_TIMER4] = 35,
119 [ASPEED_DEV_TIMER5] = 36,
120 [ASPEED_DEV_TIMER6] = 37,
121 [ASPEED_DEV_TIMER7] = 38,
122 [ASPEED_DEV_TIMER8] = 39,
123 [ASPEED_DEV_WDT] = 27,
124 [ASPEED_DEV_PWM] = 28,
125 [ASPEED_DEV_LPC] = 8,
126 [ASPEED_DEV_I2C] = 12,
127 [ASPEED_DEV_PECI] = 15,
128 [ASPEED_DEV_ETH1] = 2,
129 [ASPEED_DEV_ETH2] = 3,
130 [ASPEED_DEV_XDMA] = 6,
131 [ASPEED_DEV_SDHCI] = 26,
132 [ASPEED_DEV_HACE] = 4,
133 };
134
135 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
136
137 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
138 {
139 Aspeed2400SoCState *a = ASPEED2400_SOC(s);
140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
141
142 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
143 }
144
145 static void aspeed_ast2400_soc_init(Object *obj)
146 {
147 Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
148 AspeedSoCState *s = ASPEED_SOC(obj);
149 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
150 int i;
151 char socname[8];
152 char typename[64];
153
154 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
155 g_assert_not_reached();
156 }
157
158 for (i = 0; i < sc->num_cpus; i++) {
159 object_initialize_child(obj, "cpu[*]", &a->cpu[i],
160 aspeed_soc_cpu_type(sc->valid_cpu_types));
161 }
162
163 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
164 object_initialize_child(obj, "scu", &s->scu, typename);
165 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
166 sc->silicon_rev);
167 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
168 "hw-strap1");
169 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
170 "hw-strap2");
171 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
172 "hw-prot-key");
173
174 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
175
176 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
177
178 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
179 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
180
181 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
182 object_initialize_child(obj, "adc", &s->adc, typename);
183
184 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
185 object_initialize_child(obj, "i2c", &s->i2c, typename);
186
187 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
188
189 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
190 object_initialize_child(obj, "fmc", &s->fmc, typename);
191
192 for (i = 0; i < sc->spis_num; i++) {
193 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
194 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
195 }
196
197 for (i = 0; i < sc->ehcis_num; i++) {
198 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
199 TYPE_PLATFORM_EHCI);
200 }
201
202 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
203 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
204 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
205 "ram-size");
206
207 for (i = 0; i < sc->wdts_num; i++) {
208 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
209 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
210 }
211
212 for (i = 0; i < sc->macs_num; i++) {
213 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
214 TYPE_FTGMAC100);
215 }
216
217 for (i = 0; i < sc->uarts_num; i++) {
218 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
219 }
220
221 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
222 object_initialize_child(obj, "xdma", &s->xdma, typename);
223
224 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
225 object_initialize_child(obj, "gpio", &s->gpio, typename);
226
227 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
228 object_initialize_child(obj, "sdc", &s->sdhci, typename);
229
230 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
231
232 /* Init sd card slot class here so that they're under the correct parent */
233 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
234 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
235 TYPE_SYSBUS_SDHCI);
236 }
237
238 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
239
240 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
241 object_initialize_child(obj, "hace", &s->hace, typename);
242
243 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
244 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
245 }
246
247 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
248 {
249 int i;
250 Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
251 AspeedSoCState *s = ASPEED_SOC(dev);
252 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
253 g_autofree char *sram_name = NULL;
254 int uart;
255
256 /* Default boot region (SPI memory or ROMs) */
257 memory_region_init(&s->spi_boot_container, OBJECT(s),
258 "aspeed.spi_boot_container", 0x10000000);
259 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
260 &s->spi_boot_container);
261
262 /* IO space */
263 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
264 "aspeed.io",
265 sc->memmap[ASPEED_DEV_IOMEM],
266 ASPEED_SOC_IOMEM_SIZE);
267
268 /* Video engine stub */
269 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video),
270 "aspeed.video",
271 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
272
273 /* CPU */
274 for (i = 0; i < sc->num_cpus; i++) {
275 object_property_set_link(OBJECT(&a->cpu[i]), "memory",
276 OBJECT(s->memory), &error_abort);
277 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
278 return;
279 }
280 }
281
282 /* SRAM */
283 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
284 if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,
285 sc->sram_size[0], errp)) {
286 return;
287 }
288 memory_region_add_subregion(s->memory,
289 sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
290
291 /* SCU */
292 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
293 return;
294 }
295 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
296 sc->memmap[ASPEED_DEV_SCU]);
297
298 /* VIC */
299 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
300 return;
301 }
302 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->vic), 0,
303 sc->memmap[ASPEED_DEV_VIC]);
304 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
305 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
306 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
307 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
308
309 /* RTC */
310 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
311 return;
312 }
313 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
314 sc->memmap[ASPEED_DEV_RTC]);
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
316 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_RTC));
317
318 /* Timer */
319 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
320 &error_abort);
321 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
322 return;
323 }
324 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
325 sc->memmap[ASPEED_DEV_TIMER1]);
326 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
327 qemu_irq irq = aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_TIMER1 + i);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
329 }
330
331 /* ADC */
332 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
333 return;
334 }
335 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
336 sc->memmap[ASPEED_DEV_ADC]);
337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
338 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_ADC));
339
340 /* UART */
341 for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
342 if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
343 sc->memmap[uart], errp)) {
344 return;
345 }
346 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
347 aspeed_soc_ast2400_get_irq(s, uart));
348 }
349
350 /* I2C */
351 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
352 &error_abort);
353 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
354 return;
355 }
356 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
357 sc->memmap[ASPEED_DEV_I2C]);
358 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
359 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_I2C));
360
361 /* PECI */
362 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
363 return;
364 }
365 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0,
366 sc->memmap[ASPEED_DEV_PECI]);
367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
368 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_PECI));
369
370 /* FMC, The number of CS is set at the board level */
371 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
372 &error_abort);
373 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
374 return;
375 }
376 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
377 sc->memmap[ASPEED_DEV_FMC]);
378 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
379 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
380 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
381 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_FMC));
382
383 /* Set up an alias on the FMC CE0 region (boot default) */
384 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
385 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
386 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
387 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
388
389 /* SPI */
390 for (i = 0; i < sc->spis_num; i++) {
391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
392 return;
393 }
394 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
395 sc->memmap[ASPEED_DEV_SPI1 + i]);
396 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
397 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
398 }
399
400 /* EHCI */
401 for (i = 0; i < sc->ehcis_num; i++) {
402 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
403 return;
404 }
405 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
406 sc->memmap[ASPEED_DEV_EHCI1 + i]);
407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
408 aspeed_soc_ast2400_get_irq(s,
409 ASPEED_DEV_EHCI1 + i));
410 }
411
412 /* SDMC - SDRAM Memory Controller */
413 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
414 return;
415 }
416 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
417 sc->memmap[ASPEED_DEV_SDMC]);
418
419 /* Watch dog */
420 for (i = 0; i < sc->wdts_num; i++) {
421 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
422 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
423
424 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
425 &error_abort);
426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
427 return;
428 }
429 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
430 }
431
432 /* RAM */
433 if (!aspeed_soc_dram_init(s, errp)) {
434 return;
435 }
436
437 /* Net */
438 for (i = 0; i < sc->macs_num; i++) {
439 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
440 &error_abort);
441 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
442 return;
443 }
444 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
445 sc->memmap[ASPEED_DEV_ETH1 + i]);
446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
447 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_ETH1 + i));
448 }
449
450 /* XDMA */
451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
452 return;
453 }
454 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0,
455 sc->memmap[ASPEED_DEV_XDMA]);
456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
457 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_XDMA));
458
459 /* GPIO */
460 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
461 return;
462 }
463 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
464 sc->memmap[ASPEED_DEV_GPIO]);
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
466 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_GPIO));
467
468 /* SDHCI */
469 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
470 return;
471 }
472 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
473 sc->memmap[ASPEED_DEV_SDHCI]);
474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
475 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_SDHCI));
476
477 /* LPC */
478 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
479 return;
480 }
481 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0,
482 sc->memmap[ASPEED_DEV_LPC]);
483
484 /* Connect the LPC IRQ to the VIC */
485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
486 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_LPC));
487
488 /*
489 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
490 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
491 * contrast, on the AST2600, the subdevice IRQs are connected straight to
492 * the GIC).
493 *
494 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
495 * to the VIC is at offset 0.
496 */
497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
498 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
499
500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
501 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
502
503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
504 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
505
506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
507 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
508
509 /* HACE */
510 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
511 &error_abort);
512 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
513 return;
514 }
515 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
516 sc->memmap[ASPEED_DEV_HACE]);
517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
518 aspeed_soc_ast2400_get_irq(s, ASPEED_DEV_HACE));
519 }
520
521 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data)
522 {
523 static const char * const valid_cpu_types[] = {
524 ARM_CPU_TYPE_NAME("arm926"),
525 NULL
526 };
527 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
528 DeviceClass *dc = DEVICE_CLASS(oc);
529
530 dc->realize = aspeed_ast2400_soc_realize;
531 /* Reason: Uses serial_hds and nd_table in realize() directly */
532 dc->user_creatable = false;
533
534 sc->valid_cpu_types = valid_cpu_types;
535 sc->silicon_rev = AST2400_A1_SILICON_REV;
536 sc->sram_size[0] = 0x8000;
537 sc->spis_num = 1;
538 sc->ehcis_num = 1;
539 sc->wdts_num = 2;
540 sc->macs_num = 2;
541 sc->uarts_num = 5;
542 sc->uarts_base = ASPEED_DEV_UART1;
543 sc->irqmap = aspeed_soc_ast2400_irqmap;
544 sc->memmap = aspeed_soc_ast2400_memmap;
545 sc->num_cpus = 1;
546 }
547
548 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data)
549 {
550 static const char * const valid_cpu_types[] = {
551 ARM_CPU_TYPE_NAME("arm1176"),
552 NULL
553 };
554 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
555 DeviceClass *dc = DEVICE_CLASS(oc);
556
557 dc->realize = aspeed_ast2400_soc_realize;
558 /* Reason: Uses serial_hds and nd_table in realize() directly */
559 dc->user_creatable = false;
560
561 sc->valid_cpu_types = valid_cpu_types;
562 sc->silicon_rev = AST2500_A1_SILICON_REV;
563 sc->sram_size[0] = 0x9000;
564 sc->spis_num = 2;
565 sc->ehcis_num = 2;
566 sc->wdts_num = 3;
567 sc->macs_num = 2;
568 sc->uarts_num = 5;
569 sc->uarts_base = ASPEED_DEV_UART1;
570 sc->irqmap = aspeed_soc_ast2500_irqmap;
571 sc->memmap = aspeed_soc_ast2500_memmap;
572 sc->num_cpus = 1;
573 }
574
575 static const TypeInfo aspeed_soc_ast2400_types[] = {
576 {
577 .name = TYPE_ASPEED2400_SOC,
578 .parent = TYPE_ASPEED_SOC,
579 .instance_init = aspeed_ast2400_soc_init,
580 .instance_size = sizeof(Aspeed2400SoCState),
581 .abstract = true,
582 }, {
583 .name = "ast2400-a1",
584 .parent = TYPE_ASPEED2400_SOC,
585 .class_init = aspeed_soc_ast2400_class_init,
586 }, {
587 .name = "ast2500-a1",
588 .parent = TYPE_ASPEED2400_SOC,
589 .class_init = aspeed_soc_ast2500_class_init,
590 },
591 };
592
593 DEFINE_TYPES(aspeed_soc_ast2400_types)