| 1 | /* |
| 2 | * ASPEED SoC 2600 family |
| 3 | * |
| 4 | * Copyright (c) 2016-2019, IBM Corporation. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See |
| 7 | * the COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qapi/error.h" |
| 12 | #include "hw/misc/unimp.h" |
| 13 | #include "hw/arm/aspeed_soc.h" |
| 14 | #include "qemu/module.h" |
| 15 | #include "qemu/error-report.h" |
| 16 | #include "hw/i2c/aspeed_i2c.h" |
| 17 | #include "net/net.h" |
| 18 | #include "system/system.h" |
| 19 | #include "target/arm/cpu-qom.h" |
| 20 | |
| 21 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 |
| 22 | #define ASPEED_SOC_DPMCU_SIZE 0x00040000 |
| 23 | |
| 24 | static const hwaddr aspeed_soc_ast2600_memmap[] = { |
| 25 | [ASPEED_DEV_SPI_BOOT] = 0x00000000, |
| 26 | [ASPEED_DEV_SRAM0] = 0x10000000, |
| 27 | [ASPEED_DEV_DPMCU] = 0x18000000, |
| 28 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
| 29 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
| 30 | [ASPEED_DEV_PWM] = 0x1E610000, |
| 31 | [ASPEED_DEV_FMC] = 0x1E620000, |
| 32 | [ASPEED_DEV_SPI1] = 0x1E630000, |
| 33 | [ASPEED_DEV_SPI2] = 0x1E631000, |
| 34 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, |
| 35 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, |
| 36 | [ASPEED_DEV_MII1] = 0x1E650000, |
| 37 | [ASPEED_DEV_MII2] = 0x1E650008, |
| 38 | [ASPEED_DEV_MII3] = 0x1E650010, |
| 39 | [ASPEED_DEV_MII4] = 0x1E650018, |
| 40 | [ASPEED_DEV_ETH1] = 0x1E660000, |
| 41 | [ASPEED_DEV_ETH3] = 0x1E670000, |
| 42 | [ASPEED_DEV_ETH2] = 0x1E680000, |
| 43 | [ASPEED_DEV_ETH4] = 0x1E690000, |
| 44 | [ASPEED_DEV_VIC] = 0x1E6C0000, |
| 45 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
| 46 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
| 47 | [ASPEED_DEV_SCU] = 0x1E6E2000, |
| 48 | [ASPEED_DEV_XDMA] = 0x1E6E7000, |
| 49 | [ASPEED_DEV_ADC] = 0x1E6E9000, |
| 50 | [ASPEED_DEV_DP] = 0x1E6EB000, |
| 51 | [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED200, |
| 52 | [ASPEED_DEV_SBC] = 0x1E6F2000, |
| 53 | [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, |
| 54 | [ASPEED_DEV_VIDEO] = 0x1E700000, |
| 55 | [ASPEED_DEV_SDHCI] = 0x1E740000, |
| 56 | [ASPEED_DEV_EMMC] = 0x1E750000, |
| 57 | [ASPEED_DEV_PCIE0] = 0x1E770000, |
| 58 | [ASPEED_DEV_GPIO] = 0x1E780000, |
| 59 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, |
| 60 | [ASPEED_DEV_RTC] = 0x1E781000, |
| 61 | [ASPEED_DEV_TIMER1] = 0x1E782000, |
| 62 | [ASPEED_DEV_WDT] = 0x1E785000, |
| 63 | [ASPEED_DEV_LPC] = 0x1E789000, |
| 64 | [ASPEED_DEV_IBT] = 0x1E789140, |
| 65 | [ASPEED_DEV_I2C] = 0x1E78A000, |
| 66 | [ASPEED_DEV_PECI] = 0x1E78B000, |
| 67 | [ASPEED_DEV_UART1] = 0x1E783000, |
| 68 | [ASPEED_DEV_UART2] = 0x1E78D000, |
| 69 | [ASPEED_DEV_UART3] = 0x1E78E000, |
| 70 | [ASPEED_DEV_UART4] = 0x1E78F000, |
| 71 | [ASPEED_DEV_UART5] = 0x1E784000, |
| 72 | [ASPEED_DEV_UART6] = 0x1E790000, |
| 73 | [ASPEED_DEV_UART7] = 0x1E790100, |
| 74 | [ASPEED_DEV_UART8] = 0x1E790200, |
| 75 | [ASPEED_DEV_UART9] = 0x1E790300, |
| 76 | [ASPEED_DEV_UART10] = 0x1E790400, |
| 77 | [ASPEED_DEV_UART11] = 0x1E790500, |
| 78 | [ASPEED_DEV_UART12] = 0x1E790600, |
| 79 | [ASPEED_DEV_UART13] = 0x1E790700, |
| 80 | [ASPEED_DEV_VUART] = 0x1E787000, |
| 81 | [ASPEED_DEV_FSI1] = 0x1E79B000, |
| 82 | [ASPEED_DEV_FSI2] = 0x1E79B100, |
| 83 | [ASPEED_DEV_I3C] = 0x1E7A0000, |
| 84 | [ASPEED_DEV_PCIE_MMIO1] = 0x60000000, |
| 85 | [ASPEED_DEV_SDRAM] = 0x80000000, |
| 86 | }; |
| 87 | |
| 88 | #define ASPEED_A7MPCORE_ADDR 0x40460000 |
| 89 | |
| 90 | #define AST2600_MAX_IRQ 197 |
| 91 | |
| 92 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
| 93 | static const int aspeed_soc_ast2600_irqmap[] = { |
| 94 | [ASPEED_DEV_UART1] = 47, |
| 95 | [ASPEED_DEV_UART2] = 48, |
| 96 | [ASPEED_DEV_UART3] = 49, |
| 97 | [ASPEED_DEV_UART4] = 50, |
| 98 | [ASPEED_DEV_UART5] = 8, |
| 99 | [ASPEED_DEV_UART6] = 57, |
| 100 | [ASPEED_DEV_UART7] = 58, |
| 101 | [ASPEED_DEV_UART8] = 59, |
| 102 | [ASPEED_DEV_UART9] = 60, |
| 103 | [ASPEED_DEV_UART10] = 61, |
| 104 | [ASPEED_DEV_UART11] = 62, |
| 105 | [ASPEED_DEV_UART12] = 63, |
| 106 | [ASPEED_DEV_UART13] = 64, |
| 107 | [ASPEED_DEV_VUART] = 8, |
| 108 | [ASPEED_DEV_FMC] = 39, |
| 109 | [ASPEED_DEV_SDMC] = 0, |
| 110 | [ASPEED_DEV_SCU] = 12, |
| 111 | [ASPEED_DEV_ADC] = 78, |
| 112 | [ASPEED_DEV_XDMA] = 6, |
| 113 | [ASPEED_DEV_SDHCI] = 43, |
| 114 | [ASPEED_DEV_EHCI1] = 5, |
| 115 | [ASPEED_DEV_EHCI2] = 9, |
| 116 | [ASPEED_DEV_EMMC] = 15, |
| 117 | [ASPEED_DEV_GPIO] = 40, |
| 118 | [ASPEED_DEV_GPIO_1_8V] = 11, |
| 119 | [ASPEED_DEV_RTC] = 13, |
| 120 | [ASPEED_DEV_TIMER1] = 16, |
| 121 | [ASPEED_DEV_TIMER2] = 17, |
| 122 | [ASPEED_DEV_TIMER3] = 18, |
| 123 | [ASPEED_DEV_TIMER4] = 19, |
| 124 | [ASPEED_DEV_TIMER5] = 20, |
| 125 | [ASPEED_DEV_TIMER6] = 21, |
| 126 | [ASPEED_DEV_TIMER7] = 22, |
| 127 | [ASPEED_DEV_TIMER8] = 23, |
| 128 | [ASPEED_DEV_WDT] = 24, |
| 129 | [ASPEED_DEV_PWM] = 44, |
| 130 | [ASPEED_DEV_LPC] = 35, |
| 131 | [ASPEED_DEV_IBT] = 143, |
| 132 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
| 133 | [ASPEED_DEV_PCIE0] = 168, |
| 134 | [ASPEED_DEV_PECI] = 38, |
| 135 | [ASPEED_DEV_ETH1] = 2, |
| 136 | [ASPEED_DEV_ETH2] = 3, |
| 137 | [ASPEED_DEV_HACE] = 4, |
| 138 | [ASPEED_DEV_ETH3] = 32, |
| 139 | [ASPEED_DEV_ETH4] = 33, |
| 140 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
| 141 | [ASPEED_DEV_DP] = 62, |
| 142 | [ASPEED_DEV_FSI1] = 100, |
| 143 | [ASPEED_DEV_FSI2] = 101, |
| 144 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ |
| 145 | }; |
| 146 | |
| 147 | static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) |
| 148 | { |
| 149 | Aspeed2600SoCState *a = ASPEED2600_SOC(s); |
| 150 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 151 | |
| 152 | return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); |
| 153 | } |
| 154 | |
| 155 | static void aspeed_soc_ast2600_init(Object *obj) |
| 156 | { |
| 157 | Aspeed2600SoCState *a = ASPEED2600_SOC(obj); |
| 158 | AspeedSoCState *s = ASPEED_SOC(obj); |
| 159 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 160 | int i; |
| 161 | char socname[8]; |
| 162 | char typename[64]; |
| 163 | |
| 164 | if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { |
| 165 | g_assert_not_reached(); |
| 166 | } |
| 167 | |
| 168 | for (i = 0; i < sc->num_cpus; i++) { |
| 169 | object_initialize_child(obj, "cpu[*]", &a->cpu[i], |
| 170 | aspeed_soc_cpu_type(sc->valid_cpu_types)); |
| 171 | } |
| 172 | |
| 173 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); |
| 174 | object_initialize_child(obj, "scu", &s->scu, typename); |
| 175 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
| 176 | sc->silicon_rev); |
| 177 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), |
| 178 | "hw-strap1"); |
| 179 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
| 180 | "hw-strap2"); |
| 181 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
| 182 | "hw-prot-key"); |
| 183 | |
| 184 | object_initialize_child(obj, "a7mpcore", &a->a7mpcore, |
| 185 | TYPE_A15MPCORE_PRIV); |
| 186 | |
| 187 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
| 188 | |
| 189 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
| 190 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
| 191 | |
| 192 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
| 193 | object_initialize_child(obj, "adc", &s->adc, typename); |
| 194 | |
| 195 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
| 196 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
| 197 | |
| 198 | object_initialize_child(obj, "pcie-cfg", &s->pcie[0], TYPE_ASPEED_PCIE_CFG); |
| 199 | object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[0], |
| 200 | TYPE_ASPEED_PCIE_PHY); |
| 201 | |
| 202 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
| 203 | |
| 204 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
| 205 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
| 206 | |
| 207 | for (i = 0; i < sc->spis_num; i++) { |
| 208 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); |
| 209 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
| 210 | } |
| 211 | |
| 212 | for (i = 0; i < sc->ehcis_num; i++) { |
| 213 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
| 214 | TYPE_PLATFORM_EHCI); |
| 215 | } |
| 216 | |
| 217 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
| 218 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
| 219 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
| 220 | "ram-size"); |
| 221 | |
| 222 | for (i = 0; i < sc->wdts_num; i++) { |
| 223 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); |
| 224 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
| 225 | } |
| 226 | |
| 227 | for (i = 0; i < sc->macs_num; i++) { |
| 228 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
| 229 | TYPE_FTGMAC100); |
| 230 | |
| 231 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
| 232 | } |
| 233 | |
| 234 | for (i = 0; i < sc->uarts_num; i++) { |
| 235 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); |
| 236 | } |
| 237 | |
| 238 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
| 239 | object_initialize_child(obj, "xdma", &s->xdma, typename); |
| 240 | |
| 241 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
| 242 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
| 243 | |
| 244 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); |
| 245 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
| 246 | |
| 247 | snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); |
| 248 | object_initialize_child(obj, "sd-controller", &s->sdhci, typename); |
| 249 | |
| 250 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
| 251 | |
| 252 | /* Init sd card slot class here so that they're under the correct parent */ |
| 253 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { |
| 254 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
| 255 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); |
| 256 | } |
| 257 | |
| 258 | object_initialize_child(obj, "emmc-controller", &s->emmc, typename); |
| 259 | |
| 260 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
| 261 | |
| 262 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
| 263 | TYPE_SYSBUS_SDHCI); |
| 264 | |
| 265 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); |
| 266 | |
| 267 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); |
| 268 | object_initialize_child(obj, "hace", &s->hace, typename); |
| 269 | |
| 270 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); |
| 271 | |
| 272 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); |
| 273 | |
| 274 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); |
| 275 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); |
| 276 | object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); |
| 277 | object_initialize_child(obj, "emmc-boot-controller", |
| 278 | &s->emmc_boot_controller, |
| 279 | TYPE_UNIMPLEMENTED_DEVICE); |
| 280 | |
| 281 | for (i = 0; i < ASPEED_FSI_NUM; i++) { |
| 282 | object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); |
| 283 | } |
| 284 | } |
| 285 | |
| 286 | /* |
| 287 | * ASPEED ast2600 has 0xf as cluster ID |
| 288 | * |
| 289 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
| 290 | */ |
| 291 | static uint64_t aspeed_calc_affinity(int cpu) |
| 292 | { |
| 293 | return (0xf << ARM_AFF1_SHIFT) | cpu; |
| 294 | } |
| 295 | |
| 296 | /* |
| 297 | * PCIe Root Complex (RC) |
| 298 | * |
| 299 | * H2X register space (single block 0x00-0xFF): |
| 300 | * 0x00-0x7F : shared by RC_L (PCIe0) and RC_H (PCIe1) |
| 301 | * 0x80-0xBF : RC_L only |
| 302 | * 0xC0-0xFF : RC_H only |
| 303 | * |
| 304 | * Model scope / limitations: |
| 305 | * - Firmware supports RC_H only; this QEMU model does not support RC_L. |
| 306 | * - RC_H uses PHY1 and the MMIO window [0x60000000, 0x80000000] |
| 307 | * (aka MMIO1). |
| 308 | * |
| 309 | * Indexing convention (this model): |
| 310 | * - Expose a single logical instance at index 0. |
| 311 | * - pcie[0] -> hardware RC_H (PCIe1) |
| 312 | * - phy[0] -> hardware PHY1 |
| 313 | * - mmio.0 -> guest address range MMIO1: 0x60000000-0x80000000 |
| 314 | * - RC_L / PCIe0 is not created and mapped. |
| 315 | */ |
| 316 | static bool aspeed_soc_ast2600_pcie_realize(DeviceState *dev, Error **errp) |
| 317 | { |
| 318 | Aspeed2600SoCState *a = ASPEED2600_SOC(dev); |
| 319 | AspeedSoCState *s = ASPEED_SOC(dev); |
| 320 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 321 | MemoryRegion *mmio_mr = NULL; |
| 322 | qemu_irq irq; |
| 323 | |
| 324 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { |
| 325 | return false; |
| 326 | } |
| 327 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, |
| 328 | sc->memmap[ASPEED_DEV_PCIE_PHY1]); |
| 329 | |
| 330 | object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", |
| 331 | sc->memmap[ASPEED_DEV_SDRAM], |
| 332 | &error_abort); |
| 333 | object_property_set_link(OBJECT(&s->pcie[0]), "dram", OBJECT(s->dram_mr), |
| 334 | &error_abort); |
| 335 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { |
| 336 | return false; |
| 337 | } |
| 338 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[0]), 0, |
| 339 | sc->memmap[ASPEED_DEV_PCIE0]); |
| 340 | |
| 341 | irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 342 | sc->irqmap[ASPEED_DEV_PCIE0]); |
| 343 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[0].rc), 0, irq); |
| 344 | |
| 345 | mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[0].rc), 1); |
| 346 | memory_region_init_alias(&s->pcie_mmio_alias[0], OBJECT(&s->pcie[0].rc), |
| 347 | "aspeed.pcie-mmio", mmio_mr, |
| 348 | sc->memmap[ASPEED_DEV_PCIE_MMIO1], |
| 349 | 0x20000000); |
| 350 | memory_region_add_subregion(s->memory, |
| 351 | sc->memmap[ASPEED_DEV_PCIE_MMIO1], |
| 352 | &s->pcie_mmio_alias[0]); |
| 353 | |
| 354 | return true; |
| 355 | } |
| 356 | |
| 357 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) |
| 358 | { |
| 359 | int i; |
| 360 | Aspeed2600SoCState *a = ASPEED2600_SOC(dev); |
| 361 | AspeedSoCState *s = ASPEED_SOC(dev); |
| 362 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 363 | qemu_irq irq; |
| 364 | g_autofree char *sram_name = NULL; |
| 365 | int uart; |
| 366 | |
| 367 | /* Default boot region (SPI memory or ROMs) */ |
| 368 | memory_region_init(&s->spi_boot_container, OBJECT(s), |
| 369 | "aspeed.spi_boot_container", 0x10000000); |
| 370 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], |
| 371 | &s->spi_boot_container); |
| 372 | |
| 373 | /* IO space */ |
| 374 | aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), |
| 375 | "aspeed.io", |
| 376 | sc->memmap[ASPEED_DEV_IOMEM], |
| 377 | ASPEED_SOC_IOMEM_SIZE); |
| 378 | |
| 379 | /* Video engine stub */ |
| 380 | aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->video), |
| 381 | "aspeed.video", |
| 382 | sc->memmap[ASPEED_DEV_VIDEO], 0x1000); |
| 383 | |
| 384 | /* eMMC Boot Controller stub */ |
| 385 | aspeed_mmio_map_unimplemented(s->memory, |
| 386 | SYS_BUS_DEVICE(&s->emmc_boot_controller), |
| 387 | "aspeed.emmc-boot-controller", |
| 388 | sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); |
| 389 | |
| 390 | /* CPU */ |
| 391 | for (i = 0; i < sc->num_cpus; i++) { |
| 392 | if (sc->num_cpus > 1) { |
| 393 | object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", |
| 394 | ASPEED_A7MPCORE_ADDR, &error_abort); |
| 395 | } |
| 396 | object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", |
| 397 | aspeed_calc_affinity(i), &error_abort); |
| 398 | |
| 399 | object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, |
| 400 | &error_abort); |
| 401 | object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, |
| 402 | &error_abort); |
| 403 | object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, |
| 404 | &error_abort); |
| 405 | object_property_set_link(OBJECT(&a->cpu[i]), "memory", |
| 406 | OBJECT(s->memory), &error_abort); |
| 407 | |
| 408 | if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { |
| 409 | return; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /* A7MPCORE */ |
| 414 | object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, |
| 415 | &error_abort); |
| 416 | object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", |
| 417 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
| 418 | &error_abort); |
| 419 | |
| 420 | sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); |
| 421 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->a7mpcore), 0, |
| 422 | ASPEED_A7MPCORE_ADDR); |
| 423 | |
| 424 | for (i = 0; i < sc->num_cpus; i++) { |
| 425 | SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); |
| 426 | DeviceState *d = DEVICE(&a->cpu[i]); |
| 427 | |
| 428 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); |
| 429 | sysbus_connect_irq(sbd, i, irq); |
| 430 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); |
| 431 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
| 432 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
| 433 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
| 434 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
| 435 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
| 436 | } |
| 437 | |
| 438 | /* SRAM */ |
| 439 | sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); |
| 440 | if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, |
| 441 | sc->sram_size[0], errp)) { |
| 442 | return; |
| 443 | } |
| 444 | memory_region_add_subregion(s->memory, |
| 445 | sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]); |
| 446 | |
| 447 | /* DPMCU */ |
| 448 | aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), |
| 449 | "aspeed.dpmcu", |
| 450 | sc->memmap[ASPEED_DEV_DPMCU], |
| 451 | ASPEED_SOC_DPMCU_SIZE); |
| 452 | |
| 453 | /* SCU */ |
| 454 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
| 455 | return; |
| 456 | } |
| 457 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, |
| 458 | sc->memmap[ASPEED_DEV_SCU]); |
| 459 | |
| 460 | /* RTC */ |
| 461 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
| 462 | return; |
| 463 | } |
| 464 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0, |
| 465 | sc->memmap[ASPEED_DEV_RTC]); |
| 466 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
| 467 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_RTC)); |
| 468 | |
| 469 | /* Timer */ |
| 470 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
| 471 | &error_abort); |
| 472 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
| 473 | return; |
| 474 | } |
| 475 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, |
| 476 | sc->memmap[ASPEED_DEV_TIMER1]); |
| 477 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
| 478 | irq = aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_TIMER1 + i); |
| 479 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
| 480 | } |
| 481 | |
| 482 | /* ADC */ |
| 483 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { |
| 484 | return; |
| 485 | } |
| 486 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, |
| 487 | sc->memmap[ASPEED_DEV_ADC]); |
| 488 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
| 489 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_ADC)); |
| 490 | |
| 491 | /* UART */ |
| 492 | for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { |
| 493 | if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], |
| 494 | sc->memmap[uart], errp)) { |
| 495 | return; |
| 496 | } |
| 497 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 498 | aspeed_soc_ast2600_get_irq(s, uart)); |
| 499 | } |
| 500 | |
| 501 | /* I2C */ |
| 502 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
| 503 | &error_abort); |
| 504 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
| 505 | return; |
| 506 | } |
| 507 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, |
| 508 | sc->memmap[ASPEED_DEV_I2C]); |
| 509 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
| 510 | irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 511 | sc->irqmap[ASPEED_DEV_I2C] + i); |
| 512 | /* The AST2600 I2C controller has one IRQ per bus. */ |
| 513 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); |
| 514 | } |
| 515 | |
| 516 | /* PECI */ |
| 517 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { |
| 518 | return; |
| 519 | } |
| 520 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, |
| 521 | sc->memmap[ASPEED_DEV_PECI]); |
| 522 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, |
| 523 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_PECI)); |
| 524 | |
| 525 | /* PCIe Root Complex (RC) */ |
| 526 | if (!aspeed_soc_ast2600_pcie_realize(dev, errp)) { |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | /* FMC, The number of CS is set at the board level */ |
| 531 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
| 532 | &error_abort); |
| 533 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
| 534 | return; |
| 535 | } |
| 536 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, |
| 537 | sc->memmap[ASPEED_DEV_FMC]); |
| 538 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1, |
| 539 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
| 540 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
| 541 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_FMC)); |
| 542 | |
| 543 | /* Set up an alias on the FMC CE0 region (boot default) */ |
| 544 | MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; |
| 545 | memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", |
| 546 | fmc0_mmio, 0, memory_region_size(fmc0_mmio)); |
| 547 | memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); |
| 548 | |
| 549 | /* SPI */ |
| 550 | for (i = 0; i < sc->spis_num; i++) { |
| 551 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
| 552 | OBJECT(s->dram_mr), &error_abort); |
| 553 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
| 554 | return; |
| 555 | } |
| 556 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 557 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
| 558 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, |
| 559 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
| 560 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 561 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 + i)); |
| 562 | } |
| 563 | |
| 564 | /* EHCI */ |
| 565 | for (i = 0; i < sc->ehcis_num; i++) { |
| 566 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
| 567 | return; |
| 568 | } |
| 569 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0, |
| 570 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
| 571 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
| 572 | aspeed_soc_ast2600_get_irq(s, |
| 573 | ASPEED_DEV_EHCI1 + i)); |
| 574 | } |
| 575 | |
| 576 | /* SDMC - SDRAM Memory Controller */ |
| 577 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
| 578 | return; |
| 579 | } |
| 580 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0, |
| 581 | sc->memmap[ASPEED_DEV_SDMC]); |
| 582 | |
| 583 | /* Watch dog */ |
| 584 | for (i = 0; i < sc->wdts_num; i++) { |
| 585 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); |
| 586 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
| 587 | |
| 588 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
| 589 | &error_abort); |
| 590 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
| 591 | return; |
| 592 | } |
| 593 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
| 594 | } |
| 595 | |
| 596 | /* RAM */ |
| 597 | if (!aspeed_soc_dram_init(s, errp)) { |
| 598 | return; |
| 599 | } |
| 600 | |
| 601 | /* Net */ |
| 602 | for (i = 0; i < sc->macs_num; i++) { |
| 603 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
| 604 | &error_abort); |
| 605 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
| 606 | return; |
| 607 | } |
| 608 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
| 609 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
| 610 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
| 611 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_ETH1 + i)); |
| 612 | |
| 613 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
| 614 | OBJECT(&s->ftgmac100[i]), &error_abort); |
| 615 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
| 616 | return; |
| 617 | } |
| 618 | |
| 619 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0, |
| 620 | sc->memmap[ASPEED_DEV_MII1 + i]); |
| 621 | } |
| 622 | |
| 623 | /* XDMA */ |
| 624 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
| 625 | return; |
| 626 | } |
| 627 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->xdma), 0, |
| 628 | sc->memmap[ASPEED_DEV_XDMA]); |
| 629 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
| 630 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_XDMA)); |
| 631 | |
| 632 | /* GPIO */ |
| 633 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
| 634 | return; |
| 635 | } |
| 636 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, |
| 637 | sc->memmap[ASPEED_DEV_GPIO]); |
| 638 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
| 639 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_GPIO)); |
| 640 | |
| 641 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
| 642 | return; |
| 643 | } |
| 644 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
| 645 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
| 646 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
| 647 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
| 648 | |
| 649 | /* SDHCI */ |
| 650 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
| 651 | return; |
| 652 | } |
| 653 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0, |
| 654 | sc->memmap[ASPEED_DEV_SDHCI]); |
| 655 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
| 656 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SDHCI)); |
| 657 | |
| 658 | /* eMMC */ |
| 659 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
| 660 | return; |
| 661 | } |
| 662 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0, |
| 663 | sc->memmap[ASPEED_DEV_EMMC]); |
| 664 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
| 665 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_EMMC)); |
| 666 | |
| 667 | /* LPC */ |
| 668 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { |
| 669 | return; |
| 670 | } |
| 671 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, |
| 672 | sc->memmap[ASPEED_DEV_LPC]); |
| 673 | |
| 674 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ |
| 675 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
| 676 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_LPC)); |
| 677 | |
| 678 | /* |
| 679 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. |
| 680 | * |
| 681 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters |
| 682 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ |
| 683 | * shared across the subdevices, and the shared IRQ output to the VIC is at |
| 684 | * offset 0. |
| 685 | */ |
| 686 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, |
| 687 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 688 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); |
| 689 | |
| 690 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, |
| 691 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 692 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); |
| 693 | |
| 694 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, |
| 695 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 696 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); |
| 697 | |
| 698 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, |
| 699 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 700 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); |
| 701 | |
| 702 | /* HACE */ |
| 703 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), |
| 704 | &error_abort); |
| 705 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { |
| 706 | return; |
| 707 | } |
| 708 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, |
| 709 | sc->memmap[ASPEED_DEV_HACE]); |
| 710 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, |
| 711 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_HACE)); |
| 712 | |
| 713 | /* I3C */ |
| 714 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { |
| 715 | return; |
| 716 | } |
| 717 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, |
| 718 | sc->memmap[ASPEED_DEV_I3C]); |
| 719 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { |
| 720 | irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
| 721 | sc->irqmap[ASPEED_DEV_I3C] + i); |
| 722 | /* The AST2600 I3C controller has one IRQ per bus. */ |
| 723 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); |
| 724 | } |
| 725 | |
| 726 | /* Secure Boot Controller */ |
| 727 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { |
| 728 | return; |
| 729 | } |
| 730 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, |
| 731 | sc->memmap[ASPEED_DEV_SBC]); |
| 732 | |
| 733 | /* FSI */ |
| 734 | for (i = 0; i < ASPEED_FSI_NUM; i++) { |
| 735 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { |
| 736 | return; |
| 737 | } |
| 738 | aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fsi[i]), 0, |
| 739 | sc->memmap[ASPEED_DEV_FSI1 + i]); |
| 740 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, |
| 741 | aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_FSI1 + i)); |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) |
| 746 | { |
| 747 | uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), |
| 748 | "hw-strap1", &error_abort); |
| 749 | return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); |
| 750 | } |
| 751 | |
| 752 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data) |
| 753 | { |
| 754 | static const char * const valid_cpu_types[] = { |
| 755 | ARM_CPU_TYPE_NAME("cortex-a7"), |
| 756 | NULL |
| 757 | }; |
| 758 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 759 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
| 760 | |
| 761 | dc->realize = aspeed_soc_ast2600_realize; |
| 762 | /* Reason: The Aspeed SoC can only be instantiated from a board */ |
| 763 | dc->user_creatable = false; |
| 764 | |
| 765 | sc->valid_cpu_types = valid_cpu_types; |
| 766 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
| 767 | sc->sram_size[0] = 0x16400; |
| 768 | sc->spis_num = 2; |
| 769 | sc->ehcis_num = 2; |
| 770 | sc->wdts_num = 4; |
| 771 | sc->macs_num = 4; |
| 772 | sc->uarts_num = 13; |
| 773 | sc->uarts_base = ASPEED_DEV_UART1; |
| 774 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
| 775 | sc->memmap = aspeed_soc_ast2600_memmap; |
| 776 | sc->num_cpus = 2; |
| 777 | sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; |
| 778 | } |
| 779 | |
| 780 | static const TypeInfo aspeed_soc_ast2600_types[] = { |
| 781 | { |
| 782 | .name = TYPE_ASPEED2600_SOC, |
| 783 | .parent = TYPE_ASPEED_SOC, |
| 784 | .instance_size = sizeof(Aspeed2600SoCState), |
| 785 | .abstract = true, |
| 786 | }, { |
| 787 | .name = "ast2600-a3", |
| 788 | .parent = TYPE_ASPEED2600_SOC, |
| 789 | .instance_init = aspeed_soc_ast2600_init, |
| 790 | .class_init = aspeed_soc_ast2600_class_init, |
| 791 | }, |
| 792 | }; |
| 793 | |
| 794 | DEFINE_TYPES(aspeed_soc_ast2600_types) |