@samitouri / QOSamiQemu
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1 /*
2 * Nvidia GB200NVL
3 *
4 * Copyright 2016 IBM Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "hw/arm/machines-qom.h"
12 #include "hw/arm/aspeed.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "hw/nvram/eeprom_at24c.h"
15
16 /* GB200NVL hardware value */
17 #define GB200NVL_BMC_HW_STRAP1 0x000000C0
18 #define GB200NVL_BMC_HW_STRAP2 0x00000003
19 #define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
20
21 static const uint8_t gb200nvl_bmc_fruid[] = {
22 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
23 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
24 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
25 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
26 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
27 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
28 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
29 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
30 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
31 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
32 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
33 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
34 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
35 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
36 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
37
38 };
39 static const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
40
41 static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
42 {
43 AspeedSoCState *soc = bmc->soc;
44 I2CBus *i2c[15] = {};
45 DeviceState *dev;
46 for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
47 if ((i == 11) || (i == 12) || (i == 13)) {
48 continue;
49 }
50 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
51 }
52
53 /* Bus 5 Expander */
54 aspeed_create_pca9554(soc, 4, 0x21);
55
56 /* Mux I2c Expanders */
57 i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
58 i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
59 i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
60 i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
61 i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
62 i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
63
64 /* Bus 10 */
65 dev = DEVICE(aspeed_create_pca9554(soc, 9, 0x20));
66
67 /* Set FPGA_READY */
68 object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
69
70 aspeed_create_pca9554(soc, 9, 0x21);
71 at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
72 at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
73
74 /* Bus 11 */
75 at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
76 gb200nvl_bmc_fruid_len);
77 }
78
79 static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
80 const void *data)
81 {
82 MachineClass *mc = MACHINE_CLASS(oc);
83 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
84
85 mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
86 amc->soc_name = "ast2600-a3";
87 amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
88 amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
89 amc->fmc_model = "mx66u51235f";
90 amc->spi_model = "mx66u51235f";
91 amc->num_cs = 2;
92
93 amc->spi2_model = "mx66u51235f";
94 amc->num_cs2 = 1;
95 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
96 amc->i2c_init = gb200nvl_bmc_i2c_init;
97 mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
98 aspeed_machine_class_init_cpus_defaults(mc);
99 aspeed_machine_ast2600_class_emmc_init(oc);
100 }
101
102 static const TypeInfo aspeed_ast2600_gb200nvl_types[] = {
103 {
104 .name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
105 .parent = TYPE_ASPEED_MACHINE,
106 .class_init = aspeed_machine_gb200nvl_class_init,
107 .interfaces = arm_machine_interfaces,
108 }
109 };
110
111 DEFINE_TYPES(aspeed_ast2600_gb200nvl_types)