@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 345 lines 12.7 KB
Raw
1 /*
2 * ASPEED Ast27x0 TSP Coprocessor
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/core/qdev-clock.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_coprocessor.h"
18
19 #define AST2700_TSP_SDRAM_SIZE (512 * MiB)
20
21 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
22 [ASPEED_DEV_SDRAM] = 0x00000000,
23 [ASPEED_DEV_SRAM0] = 0x70000000,
24 [ASPEED_DEV_INTC] = 0x72100000,
25 [ASPEED_DEV_PRIC0] = 0x72140000,
26 [ASPEED_DEV_SCU] = 0x72C02000,
27 [ASPEED_DEV_TIMER1] = 0x72C10000,
28 [ASPEED_DEV_UART4] = 0x72C1A000,
29 [ASPEED_DEV_IPC0] = 0x72C1C000,
30 [ASPEED_DEV_FMC] = 0x74000000,
31 [ASPEED_DEV_PRIC1] = 0x74100000,
32 [ASPEED_DEV_SCUIO] = 0x74C02000,
33 [ASPEED_DEV_OTP] = 0x74C07000,
34 [ASPEED_DEV_INTCIO] = 0x74C18000,
35 [ASPEED_DEV_UART0] = 0x74C33000,
36 [ASPEED_DEV_UART1] = 0x74C33100,
37 [ASPEED_DEV_UART2] = 0x74C33200,
38 [ASPEED_DEV_UART3] = 0x74C33300,
39 [ASPEED_DEV_UART5] = 0x74C33400,
40 [ASPEED_DEV_UART6] = 0x74C33500,
41 [ASPEED_DEV_UART7] = 0x74C33600,
42 [ASPEED_DEV_UART8] = 0x74C33700,
43 [ASPEED_DEV_UART9] = 0x74C33800,
44 [ASPEED_DEV_UART10] = 0x74C33900,
45 [ASPEED_DEV_UART11] = 0x74C33A00,
46 [ASPEED_DEV_UART12] = 0x74C33B00,
47 [ASPEED_DEV_IPC1] = 0x74C39000,
48 };
49
50 static const int aspeed_soc_ast27x0tsp_irqmap[] = {
51 [ASPEED_DEV_UART4] = 8,
52 [ASPEED_DEV_SCU] = 12,
53 [ASPEED_DEV_TIMER1] = 16,
54 [ASPEED_DEV_UART0] = 164,
55 [ASPEED_DEV_UART1] = 164,
56 [ASPEED_DEV_UART2] = 164,
57 [ASPEED_DEV_UART3] = 164,
58 [ASPEED_DEV_UART5] = 164,
59 [ASPEED_DEV_UART6] = 164,
60 [ASPEED_DEV_UART7] = 164,
61 [ASPEED_DEV_UART8] = 164,
62 [ASPEED_DEV_UART9] = 164,
63 [ASPEED_DEV_UART10] = 164,
64 [ASPEED_DEV_UART11] = 164,
65 [ASPEED_DEV_UART12] = 164,
66 };
67
68 /* TSPINT 164 */
69 static const int ast2700_tsp164_intcmap[] = {
70 [ASPEED_DEV_UART0] = 7,
71 [ASPEED_DEV_UART1] = 8,
72 [ASPEED_DEV_UART2] = 9,
73 [ASPEED_DEV_UART3] = 10,
74 [ASPEED_DEV_UART5] = 11,
75 [ASPEED_DEV_UART6] = 12,
76 [ASPEED_DEV_UART7] = 13,
77 [ASPEED_DEV_UART8] = 14,
78 [ASPEED_DEV_UART9] = 15,
79 [ASPEED_DEV_UART10] = 16,
80 [ASPEED_DEV_UART11] = 17,
81 [ASPEED_DEV_UART12] = 18,
82 };
83
84 struct nvic_intc_irq_info {
85 int irq;
86 int intc_idx;
87 int orgate_idx;
88 const int *ptr;
89 };
90
91 static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
92 {160, 1, 0, NULL},
93 {161, 1, 1, NULL},
94 {162, 1, 2, NULL},
95 {163, 1, 3, NULL},
96 {164, 1, 4, ast2700_tsp164_intcmap},
97 {165, 1, 5, NULL},
98 {166, 1, 6, NULL},
99 {167, 1, 7, NULL},
100 {168, 1, 8, NULL},
101 {169, 1, 9, NULL},
102 };
103
104 static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedCoprocessorState *s,
105 int dev)
106 {
107 Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(s);
108 AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
109
110 int or_idx;
111 int idx;
112 int i;
113
114 for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
115 if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
116 assert(ast2700_tsp_intcmap[i].ptr);
117 or_idx = ast2700_tsp_intcmap[i].orgate_idx;
118 idx = ast2700_tsp_intcmap[i].intc_idx;
119 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
120 ast2700_tsp_intcmap[i].ptr[dev]);
121 }
122 }
123
124 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
125 }
126
127 static void aspeed_soc_ast27x0tsp_init(Object *obj)
128 {
129 Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
130 AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
131
132 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
133 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
134
135 object_initialize_child(obj, "intc0", &a->intc[0],
136 TYPE_ASPEED_2700TSP_INTC);
137 object_initialize_child(obj, "intc1", &a->intc[1],
138 TYPE_ASPEED_2700TSP_INTCIO);
139
140 object_initialize_child(obj, "timerctrl", &s->timerctrl,
141 TYPE_UNIMPLEMENTED_DEVICE);
142 object_initialize_child(obj, "ipc0", &a->ipc[0],
143 TYPE_UNIMPLEMENTED_DEVICE);
144 object_initialize_child(obj, "ipc1", &a->ipc[1],
145 TYPE_UNIMPLEMENTED_DEVICE);
146 object_initialize_child(obj, "pric0", &a->pric[0],
147 TYPE_UNIMPLEMENTED_DEVICE);
148 object_initialize_child(obj, "pric1", &a->pric[1],
149 TYPE_UNIMPLEMENTED_DEVICE);
150 object_initialize_child(obj, "otp", &a->otp,
151 TYPE_UNIMPLEMENTED_DEVICE);
152 }
153
154 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
155 {
156 Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(dev_soc);
157 AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
158 AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
159 DeviceState *armv7m;
160 MemoryRegion *mr;
161 g_autofree char *sdram_name = NULL;
162 int i;
163
164 if (!clock_has_source(s->sysclk)) {
165 error_setg(errp, "sysclk clock must be wired up by the board code");
166 return;
167 }
168
169 if (!a->scu) {
170 error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
171 ": 'scu' link is not set");
172 return;
173 }
174
175 if (!a->scuio) {
176 error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
177 ": 'scuio' link is not set");
178 return;
179 }
180
181 if (!a->fmc) {
182 error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
183 ": 'fmc' link is not set");
184 return;
185 }
186
187 /* AST27X0 TSP Core */
188 armv7m = DEVICE(&a->armv7m);
189 qdev_prop_set_uint32(armv7m, "num-irq", 256);
190 qdev_prop_set_string(armv7m, "cpu-type",
191 aspeed_soc_cpu_type(sc->valid_cpu_types));
192 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
193 object_property_set_link(OBJECT(&a->armv7m), "memory",
194 OBJECT(s->memory), &error_abort);
195 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
196
197 /* SDRAM */
198 sdram_name = g_strdup_printf("aspeed.sdram.%d",
199 CPU(a->armv7m.cpu)->cpu_index);
200 if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
201 AST2700_TSP_SDRAM_SIZE, errp)) {
202 return;
203 }
204 memory_region_add_subregion(s->memory,
205 sc->memmap[ASPEED_DEV_SDRAM],
206 &s->sdram);
207
208 /* SRAM */
209 memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
210 s->sram, 0, memory_region_size(s->sram));
211 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],
212 &s->sram_alias);
213
214 /* SCU */
215 memory_region_init_alias(&a->scu_alias, OBJECT(a), "scu.alias",
216 &a->scu->parent_obj.iomem, 0,
217 memory_region_size(&a->scu->parent_obj.iomem));
218 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
219 &a->scu_alias);
220
221 /* SCUIO */
222 memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
223 &a->scuio->iomem, 0,
224 memory_region_size(&a->scuio->iomem));
225 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
226 &a->scuio_alias);
227
228 /* INTC */
229 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
230 return;
231 }
232
233 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
234 sc->memmap[ASPEED_DEV_INTC]);
235
236 /* INTCIO */
237 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
238 return;
239 }
240
241 aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
242 sc->memmap[ASPEED_DEV_INTCIO]);
243
244 /* irq source orgates -> INTC */
245 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
246 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
247 qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
248 }
249 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
250 assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
251 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
252 qdev_get_gpio_in(DEVICE(&a->armv7m),
253 ast2700_tsp_intcmap[i].irq));
254 }
255 /* irq source orgates -> INTC */
256 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
257 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
258 qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
259 }
260 /* INTCIO -> INTC */
261 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
262 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
263 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
264 }
265
266 /* UART */
267 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(s->uart), 0);
268 memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias", mr, 0,
269 memory_region_size(mr));
270 memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
271 &s->uart_alias);
272 /*
273 * Redirect the UART interrupt to the NVIC, replacing the default routing
274 * to the PSP's GIC.
275 */
276 sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
277 aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
278
279 /* FMC */
280 memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
281 &a->fmc->mmio, 0,
282 memory_region_size(&a->fmc->mmio));
283 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
284 &a->fmc_alias);
285
286 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
287 "aspeed.timerctrl",
288 sc->memmap[ASPEED_DEV_TIMER1], 0x200);
289 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[0]),
290 "aspeed.ipc0",
291 sc->memmap[ASPEED_DEV_IPC0], 0x1000);
292 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
293 "aspeed.ipc1",
294 sc->memmap[ASPEED_DEV_IPC1], 0x1000);
295 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
296 "aspeed.pric0",
297 sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
298 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
299 "aspeed.pric1",
300 sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
301 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->otp),
302 "aspeed.otp",
303 sc->memmap[ASPEED_DEV_OTP], 0x800);
304 }
305
306 static const Property aspeed_27x0_coprocessor_properties[] = {
307 DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
308 TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
309 DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
310 TYPE_ASPEED_SCU, AspeedSCUState *),
311 DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
312 AspeedSMCState *),
313 };
314
315 static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
316 const void *data)
317 {
318 static const char * const valid_cpu_types[] = {
319 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
320 NULL
321 };
322 DeviceClass *dc = DEVICE_CLASS(klass);
323 AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_CLASS(dc);
324
325 /* Reason: The Aspeed Coprocessor can only be instantiated from a board */
326 dc->user_creatable = false;
327 dc->realize = aspeed_soc_ast27x0tsp_realize;
328 device_class_set_props(dc, aspeed_27x0_coprocessor_properties);
329
330 sc->valid_cpu_types = valid_cpu_types;
331 sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
332 sc->memmap = aspeed_soc_ast27x0tsp_memmap;
333 }
334
335 static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
336 {
337 .name = TYPE_ASPEED27X0TSP_COPROCESSOR,
338 .parent = TYPE_ASPEED_COPROCESSOR,
339 .instance_size = sizeof(Aspeed27x0CoprocessorState),
340 .instance_init = aspeed_soc_ast27x0tsp_init,
341 .class_init = aspeed_soc_ast27x0tsp_class_init,
342 },
343 };
344
345 DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)