aspeed_ast27x0.c · samitouri/QOSamiQemu

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1	/*
2	* ASPEED SoC 27x0 family
3	*
4	* Copyright (C) 2024 ASPEED Technology Inc.
5	*
6	* This code is licensed under the GPL version 2 or later. See
7	* the COPYING file in the top-level directory.
8	*
9	* Implementation extracted from the AST2600 and adapted for AST27x0.
10	*/
11
12	#include "qemu/osdep.h"
13	#include "qapi/error.h"
14	#include "hw/misc/unimp.h"
15	#include "hw/arm/aspeed_soc.h"
16	#include "hw/arm/bsa.h"
17	#include "qemu/module.h"
18	#include "qemu/error-report.h"
19	#include "hw/i2c/aspeed_i2c.h"
20	#include "net/net.h"
21	#include "system/qtest.h"
22	#include "system/system.h"
23	#include "hw/intc/arm_gicv3.h"
24	#include "qobject/qlist.h"
25	#include "qemu/log.h"
26
27	#define AST2700_SOC_IO_SIZE 0x00FE0000
28	#define AST2700_SOC_IOMEM_SIZE 0x01000000
29	#define AST2700_SOC_DPMCU_SIZE 0x00040000
30
31	static const hwaddr aspeed_soc_ast2700_memmap[] = {
32	[ASPEED_DEV_VBOOTROM] = 0x00000000,
33	[ASPEED_DEV_IOMEM] = 0x00020000,
34	[ASPEED_DEV_SRAM0] = 0x10000000,
35	[ASPEED_DEV_DPMCU] = 0x11000000,
36	[ASPEED_DEV_IOMEM0] = 0x12000000,
37	[ASPEED_DEV_EHCI1] = 0x12061000,
38	[ASPEED_DEV_EHCI2] = 0x12063000,
39	[ASPEED_DEV_HACE] = 0x12070000,
40	[ASPEED_DEV_EMMC] = 0x12090000,
41	[ASPEED_DEV_PCIE0] = 0x120E0000,
42	[ASPEED_DEV_PCIE1] = 0x120F0000,
43	[ASPEED_DEV_INTC] = 0x12100000,
44	[ASPEED_GIC_DIST] = 0x12200000,
45	[ASPEED_GIC_REDIST] = 0x12280000,
46	[ASPEED_DEV_SDMC] = 0x12C00000,
47	[ASPEED_DEV_SCU] = 0x12C02000,
48	[ASPEED_DEV_RTC] = 0x12C0F000,
49	[ASPEED_DEV_TIMER1] = 0x12C10000,
50	[ASPEED_DEV_PCIE_PHY0] = 0x12C15000,
51	[ASPEED_DEV_PCIE_PHY1] = 0x12C15800,
52	[ASPEED_DEV_SLI] = 0x12C17000,
53	[ASPEED_DEV_UART4] = 0x12C1A000,
54	[ASPEED_DEV_IOMEM1] = 0x14000000,
55	[ASPEED_DEV_FMC] = 0x14000000,
56	[ASPEED_DEV_SPI0] = 0x14010000,
57	[ASPEED_DEV_SPI1] = 0x14020000,
58	[ASPEED_DEV_SPI2] = 0x14030000,
59	[ASPEED_DEV_MII1] = 0x14040000,
60	[ASPEED_DEV_MII2] = 0x14040008,
61	[ASPEED_DEV_MII3] = 0x14040010,
62	[ASPEED_DEV_ETH1] = 0x14050000,
63	[ASPEED_DEV_ETH2] = 0x14060000,
64	[ASPEED_DEV_ETH3] = 0x14070000,
65	[ASPEED_DEV_SDHCI] = 0x14080000,
66	[ASPEED_DEV_PCIE2] = 0x140D0000,
67	[ASPEED_DEV_EHCI3] = 0x14121000,
68	[ASPEED_DEV_EHCI4] = 0x14123000,
69	[ASPEED_DEV_ADC] = 0x14C00000,
70	[ASPEED_DEV_SCUIO] = 0x14C02000,
71	[ASPEED_DEV_GPIO] = 0x14C0B000,
72	[ASPEED_DEV_SGPIOM0] = 0x14C0C000,
73	[ASPEED_DEV_SGPIOM1] = 0x14C0D000,
74	[ASPEED_DEV_I2C] = 0x14C0F000,
75	[ASPEED_DEV_INTCIO] = 0x14C18000,
76	[ASPEED_DEV_PCIE_PHY2] = 0x14C1C000,
77	[ASPEED_DEV_SLIIO] = 0x14C1E000,
78	[ASPEED_DEV_VUART] = 0x14C30000,
79	[ASPEED_DEV_UART0] = 0x14C33000,
80	[ASPEED_DEV_UART1] = 0x14C33100,
81	[ASPEED_DEV_UART2] = 0x14C33200,
82	[ASPEED_DEV_UART3] = 0x14C33300,
83	[ASPEED_DEV_UART5] = 0x14C33400,
84	[ASPEED_DEV_UART6] = 0x14C33500,
85	[ASPEED_DEV_UART7] = 0x14C33600,
86	[ASPEED_DEV_UART8] = 0x14C33700,
87	[ASPEED_DEV_UART9] = 0x14C33800,
88	[ASPEED_DEV_UART10] = 0x14C33900,
89	[ASPEED_DEV_UART11] = 0x14C33A00,
90	[ASPEED_DEV_UART12] = 0x14C33B00,
91	[ASPEED_DEV_LTPI_CTRL1] = 0x14C34000,
92	[ASPEED_DEV_LTPI_CTRL2] = 0x14C35000,
93	[ASPEED_DEV_WDT] = 0x14C37000,
94	[ASPEED_DEV_LTPI_IO0] = 0x30000000,
95	[ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
96	[ASPEED_DEV_LTPI_IO1] = 0x50000000,
97	[ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
98	[ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
99	[ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
100	[ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
101	[ASPEED_DEV_SPI_BOOT] = 0x100000000,
102	[ASPEED_DEV_SDRAM] = 0x400000000,
103	};
104
105	#define AST2700_MAX_IRQ 256
106
107	/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
108	static const int aspeed_soc_ast2700a1_irqmap[] = {
109	[ASPEED_DEV_SDMC] = 0,
110	[ASPEED_DEV_HACE] = 4,
111	[ASPEED_DEV_XDMA] = 5,
112	[ASPEED_DEV_UART4] = 8,
113	[ASPEED_DEV_SCU] = 12,
114	[ASPEED_DEV_RTC] = 13,
115	[ASPEED_DEV_EMMC] = 15,
116	[ASPEED_DEV_TIMER1] = 16,
117	[ASPEED_DEV_TIMER2] = 17,
118	[ASPEED_DEV_TIMER3] = 18,
119	[ASPEED_DEV_TIMER4] = 19,
120	[ASPEED_DEV_TIMER5] = 20,
121	[ASPEED_DEV_TIMER6] = 21,
122	[ASPEED_DEV_TIMER7] = 22,
123	[ASPEED_DEV_TIMER8] = 23,
124	[ASPEED_DEV_DP] = 28,
125	[ASPEED_DEV_EHCI1] = 33,
126	[ASPEED_DEV_EHCI2] = 37,
127	[ASPEED_DEV_PCIE0] = 56,
128	[ASPEED_DEV_PCIE1] = 57,
129	[ASPEED_DEV_LPC] = 192,
130	[ASPEED_DEV_IBT] = 192,
131	[ASPEED_DEV_KCS] = 192,
132	[ASPEED_DEV_I2C] = 194,
133	[ASPEED_DEV_ADC] = 194,
134	[ASPEED_DEV_GPIO] = 194,
135	[ASPEED_DEV_SGPIOM0] = 194,
136	[ASPEED_DEV_SGPIOM1] = 194,
137	[ASPEED_DEV_FMC] = 195,
138	[ASPEED_DEV_WDT] = 195,
139	[ASPEED_DEV_PWM] = 195,
140	[ASPEED_DEV_I3C] = 195,
141	[ASPEED_DEV_PCIE2] = 196,
142	[ASPEED_DEV_UART0] = 196,
143	[ASPEED_DEV_UART1] = 196,
144	[ASPEED_DEV_UART2] = 196,
145	[ASPEED_DEV_UART3] = 196,
146	[ASPEED_DEV_UART5] = 196,
147	[ASPEED_DEV_UART6] = 196,
148	[ASPEED_DEV_UART7] = 196,
149	[ASPEED_DEV_UART8] = 196,
150	[ASPEED_DEV_UART9] = 196,
151	[ASPEED_DEV_UART10] = 196,
152	[ASPEED_DEV_UART11] = 196,
153	[ASPEED_DEV_UART12] = 196,
154	[ASPEED_DEV_ETH1] = 196,
155	[ASPEED_DEV_ETH2] = 196,
156	[ASPEED_DEV_ETH3] = 196,
157	[ASPEED_DEV_EHCI3] = 196,
158	[ASPEED_DEV_EHCI4] = 196,
159	[ASPEED_DEV_PECI] = 197,
160	[ASPEED_DEV_SDHCI] = 197,
161	[ASPEED_DEV_IOEXP0_I2C] = 198,
162	[ASPEED_DEV_IOEXP0_I3C] = 199,
163	[ASPEED_DEV_IOEXP1_I2C] = 200,
164	[ASPEED_DEV_IOEXP1_I3C] = 201,
165	};
166
167	/* GICINT 192 */
168	static const int ast2700_gic192_intcmap[] = {
169	[ASPEED_DEV_LPC] = 0,
170	[ASPEED_DEV_IBT] = 2,
171	[ASPEED_DEV_KCS] = 4,
172	};
173
174	/* GICINT 193 */
175
176	/* GICINT 194 */
177	static const int ast2700_gic194_intcmap[] = {
178	[ASPEED_DEV_I2C] = 0,
179	[ASPEED_DEV_ADC] = 16,
180	[ASPEED_DEV_GPIO] = 18,
181	[ASPEED_DEV_SGPIOM0] = 21,
182	[ASPEED_DEV_SGPIOM1] = 24,
183	};
184
185	/* GICINT 195 */
186	static const int ast2700_gic195_intcmap[] = {
187	[ASPEED_DEV_I3C] = 0,
188	[ASPEED_DEV_WDT] = 16,
189	[ASPEED_DEV_FMC] = 25,
190	[ASPEED_DEV_PWM] = 29,
191	};
192
193	/* GICINT 196 */
194	static const int ast2700_gic196_intcmap[] = {
195	[ASPEED_DEV_ETH1] = 0,
196	[ASPEED_DEV_ETH2] = 1,
197	[ASPEED_DEV_ETH3] = 2,
198	[ASPEED_DEV_UART0] = 7,
199	[ASPEED_DEV_UART1] = 8,
200	[ASPEED_DEV_UART2] = 9,
201	[ASPEED_DEV_UART3] = 10,
202	[ASPEED_DEV_UART5] = 11,
203	[ASPEED_DEV_UART6] = 12,
204	[ASPEED_DEV_UART7] = 13,
205	[ASPEED_DEV_UART8] = 14,
206	[ASPEED_DEV_UART9] = 15,
207	[ASPEED_DEV_UART10] = 16,
208	[ASPEED_DEV_UART11] = 17,
209	[ASPEED_DEV_UART12] = 18,
210	[ASPEED_DEV_EHCI3] = 28,
211	[ASPEED_DEV_EHCI4] = 29,
212	[ASPEED_DEV_PCIE2] = 31,
213	};
214
215	/* GICINT 197 */
216	static const int ast2700_gic197_intcmap[] = {
217	[ASPEED_DEV_SDHCI] = 1,
218	[ASPEED_DEV_PECI] = 4,
219	};
220
221	/* Primary AST1700 Interrupts */
222	/* A1: GICINT 198 */
223	static const int ast2700_gic198_intcmap[] = {
224	[ASPEED_DEV_IOEXP0_I2C] = 0, /* 0 - 15 */
225	};
226
227	/* Primary AST1700 Interrupts */
228	/* A1: GINTC 199 */
229	static const int ast2700_gic199_intcmap[] = {
230	[ASPEED_DEV_IOEXP0_I3C] = 0, /* 0 - 15 */
231	};
232
233	/* Secondary AST1700 Interrupts */
234	/* A1: GINTC 200 */
235	static const int ast2700_gic200_intcmap[] = {
236	[ASPEED_DEV_IOEXP1_I2C] = 0, /* 0 - 15 */
237	};
238
239	/* Secondary AST1700 Interrupts */
240	/* A1: GINTC 201 */
241	static const int ast2700_gic201_intcmap[] = {
242	[ASPEED_DEV_IOEXP1_I3C] = 0, /* 0 - 15 */
243	};
244
245	/* GICINT 192 ~ 201 */
246	struct gic_intc_irq_info {
247	int irq;
248	int intc_idx;
249	int orgate_idx;
250	const int *ptr;
251	};
252
253	static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
254	{192, 1, 0, ast2700_gic192_intcmap},
255	{193, 1, 1, NULL},
256	{194, 1, 2, ast2700_gic194_intcmap},
257	{195, 1, 3, ast2700_gic195_intcmap},
258	{196, 1, 4, ast2700_gic196_intcmap},
259	{197, 1, 5, ast2700_gic197_intcmap},
260	{198, 2, 0, ast2700_gic198_intcmap},
261	{199, 2, 1, ast2700_gic199_intcmap},
262	{200, 3, 0, ast2700_gic200_intcmap},
263	{201, 3, 1, ast2700_gic201_intcmap},
264	};
265
266	static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
267	{
268	Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
269	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
270	int or_idx;
271	int idx;
272	int i;
273
274	for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
275	if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
276	assert(ast2700_gic_intcmap[i].ptr);
277	or_idx = ast2700_gic_intcmap[i].orgate_idx;
278	idx = ast2700_gic_intcmap[i].intc_idx;
279	return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
280	ast2700_gic_intcmap[i].ptr[dev]);
281	}
282	}
283
284	return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
285	}
286
287	static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
288	int index)
289	{
290	Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
291	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
292	int or_idx;
293	int idx;
294	int i;
295	OrIRQState *porgates;
296
297	for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
298	if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
299	assert(ast2700_gic_intcmap[i].ptr);
300	or_idx = ast2700_gic_intcmap[i].orgate_idx;
301	idx = ast2700_gic_intcmap[i].intc_idx;
302	if (idx < ASPEED_INTC_NUM) {
303	porgates = &a->intc[idx].orgates[or_idx];
304	return qdev_get_gpio_in(DEVICE(porgates),
305	ast2700_gic_intcmap[i].ptr[dev] + index);
306	} else {
307	idx -= ASPEED_INTC_NUM;
308	porgates = &a->intcioexp[idx].orgates[or_idx];
309	return qdev_get_gpio_in(DEVICE(porgates),
310	ast2700_gic_intcmap[i].ptr[dev] + index);
311	}
312	}
313	}
314
315	/*
316	* Invalid OR gate index, device IRQ should be between 192 to 201.
317	*/
318	g_assert_not_reached();
319	}
320
321	static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
322	unsigned int size)
323	{
324	qemu_log_mask(LOG_GUEST_ERROR,
325	"%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",
326	__func__, addr);
327	return 0;
328	}
329
330	static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
331	unsigned int size)
332	{
333	AspeedSoCState *s = ASPEED_SOC(opaque);
334	ram_addr_t ram_size;
335	MemTxResult result;
336
337	ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
338	&error_abort);
339
340	assert(ram_size > 0);
341
342	/*
343	* Emulate ddr capacity hardware behavior.
344	* If writes the data to the address which is beyond the ram size,
345	* it would write the data to the "address % ram_size".
346	*/
347	address_space_stl_le(&s->dram_as, addr % ram_size, data,
348	MEMTXATTRS_UNSPECIFIED, &result);
349
350	if (result != MEMTX_OK) {
351	qemu_log_mask(LOG_GUEST_ERROR,
352	"%s: DRAM write failed, addr:0x%" HWADDR_PRIx
353	", data :0x%" PRIx64 "\n",
354	__func__, addr % ram_size, data);
355	}
356	}
357
358	static const MemoryRegionOps aspeed_ram_capacity_ops = {
359	.read = aspeed_ram_capacity_read,
360	.write = aspeed_ram_capacity_write,
361	.endianness = DEVICE_LITTLE_ENDIAN,
362	.impl.min_access_size = 4,
363	.valid = {
364	.min_access_size = 4,
365	.max_access_size = 4,
366	},
367	};
368
369	/*
370	* SDMC should be realized first to get correct RAM size and max size
371	* values
372	*/
373	static bool aspeed_soc_ast2700_dram_init(DeviceState dev, Error *errp)
374	{
375	ram_addr_t ram_size, max_ram_size;
376	Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
377	AspeedSoCState *s = ASPEED_SOC(dev);
378	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
379
380	ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
381	&error_abort);
382	max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
383	&error_abort);
384
385	memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
386	ram_size);
387	memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
388	address_space_init(&s->dram_as, s->dram_mr, "dram");
389
390	/*
391	* Add a memory region beyond the RAM region to emulate
392	* ddr capacity hardware behavior.
393	*/
394	if (ram_size < max_ram_size) {
395	memory_region_init_io(&a->dram_empty, OBJECT(s),
396	&aspeed_ram_capacity_ops, s,
397	"ram-empty", max_ram_size - ram_size);
398
399	memory_region_add_subregion(s->memory,
400	sc->memmap[ASPEED_DEV_SDRAM] + ram_size,
401	&a->dram_empty);
402	}
403
404	memory_region_add_subregion(s->memory,
405	sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
406	return true;
407	}
408
409	static void aspeed_soc_ast2700_init(Object *obj)
410	{
411	Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
412	AspeedSoCState *s = ASPEED_SOC(obj);
413	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
414	int i;
415	char socname[8];
416	char typename[64];
417
418	if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
419	g_assert_not_reached();
420	}
421
422	for (i = 0; i < sc->num_cpus; i++) {
423	if (qtest_enabled() && !target_aarch64()) {
424	/*
425	* Introspection qtest just want to create this object
426	* without realizing it. ARM_CPU_TYPE_NAME("cortex-a35")
427	* is not available on 32-bit binary: skip it since we
428	* won't even realize it.
429	*/
430	continue;
431	}
432	object_initialize_child(obj, "cpu[*]", &a->cpu[i],
433	aspeed_soc_cpu_type(sc->valid_cpu_types));
434	}
435
436	object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
437
438	object_initialize_child(obj, "scu", &a->scu, TYPE_ASPEED_2700_SCU);
439	qdev_prop_set_uint32(DEVICE(&a->scu), "silicon-rev",
440	sc->silicon_rev);
441	object_property_add_alias(obj, "hw-strap1", OBJECT(&a->scu),
442	"hw-strap1");
443	object_property_add_alias(obj, "hw-prot-key", OBJECT(&a->scu),
444	"hw-prot-key");
445
446	object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
447	qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
448	sc->silicon_rev);
449	/*
450	* There is one hw-strap1 register in the SCU (CPU DIE) and another
451	* hw-strap1 register in the SCUIO (IO DIE). To reuse the current design
452	* of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the
453	* SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and
454	* sets the value in the SCUIO hw-strap1 register.
455	*/
456	object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio),
457	"hw-strap1");
458
459	snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
460	object_initialize_child(obj, "fmc", &s->fmc, typename);
461
462	for (i = 0; i < sc->spis_num; i++) {
463	snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname);
464	object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
465	}
466
467	for (i = 0; i < sc->ehcis_num; i++) {
468	object_initialize_child(obj, "ehci[*]", &s->ehci[i],
469	TYPE_PLATFORM_EHCI);
470	}
471
472	snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
473	object_initialize_child(obj, "sdmc", &s->sdmc, typename);
474	object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
475	"ram-size");
476
477	for (i = 0; i < sc->wdts_num; i++) {
478	snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
479	object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
480	}
481
482	for (i = 0; i < sc->macs_num; i++) {
483	object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
484	TYPE_FTGMAC100);
485
486	object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
487	}
488
489	for (i = 0; i < sc->uarts_num; i++) {
490	object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
491	}
492
493	object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
494	object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
495	object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
496	object_initialize_child(obj, "intcio", &a->intc[1],
497	TYPE_ASPEED_2700_INTCIO);
498	object_initialize_child(obj, "intc-ioexp0", &a->intcioexp[0],
499	TYPE_ASPEED_2700_INTCIOEXP1);
500	object_initialize_child(obj, "intc-ioexp1", &a->intcioexp[1],
501	TYPE_ASPEED_2700_INTCIOEXP2);
502
503	snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
504	object_initialize_child(obj, "adc", &s->adc, typename);
505
506	snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
507	object_initialize_child(obj, "i2c", &s->i2c, typename);
508
509	snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
510	object_initialize_child(obj, "gpio", &s->gpio, typename);
511
512	snprintf(typename, sizeof(typename), "aspeed.sgpio-%s", socname);
513	for (i = 0; i < sc->sgpio_num; i++) {
514	object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i], typename);
515	}
516
517	object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
518
519	snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
520	object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
521	object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort);
522
523	/* Init sd card slot class here so that they're under the correct parent */
524	object_initialize_child(obj, "sd-controller.sdhci",
525	&s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
526
527	object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
528	object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
529
530	object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
531	TYPE_SYSBUS_SDHCI);
532
533	snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
534	object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
535
536	snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
537	object_initialize_child(obj, "hace", &s->hace, typename);
538
539	for (i = 0; i < sc->pcie_num; i++) {
540	snprintf(typename, sizeof(typename), "aspeed.pcie-phy-%s", socname);
541	object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i], typename);
542	object_property_set_int(OBJECT(&s->pcie_phy[i]), "id", i, &error_abort);
543
544	snprintf(typename, sizeof(typename), "aspeed.pcie-cfg-%s", socname);
545	object_initialize_child(obj, "pcie-cfg[*]", &s->pcie[i], typename);
546	object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
547	}
548
549	for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
550	object_initialize_child(obj, "ltpi-ctrl[*]",
551	&s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
552	}
553
554	for (i = 0; i < sc->ioexp_num; i++) {
555	/* AST1700 IOEXP */
556	object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
557	TYPE_ASPEED_AST1700);
558	qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev",
559	sc->silicon_rev);
560	}
561
562	object_initialize_child(obj, "dpmcu", &s->dpmcu,
563	TYPE_UNIMPLEMENTED_DEVICE);
564	object_initialize_child(obj, "iomem", &s->iomem,
565	TYPE_UNIMPLEMENTED_DEVICE);
566	object_initialize_child(obj, "iomem0", &s->iomem0,
567	TYPE_UNIMPLEMENTED_DEVICE);
568	object_initialize_child(obj, "iomem1", &s->iomem1,
569	TYPE_UNIMPLEMENTED_DEVICE);
570	}
571
572	/*
573	* ASPEED ast2700 has 0x0 as cluster ID
574	*
575	* https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1
576	*/
577	static uint64_t aspeed_calc_affinity(int cpu)
578	{
579	return (0x0 << ARM_AFF1_SHIFT) \| cpu;
580	}
581
582	static bool aspeed_soc_ast2700_gic_realize(DeviceState dev, Error *errp)
583	{
584	Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
585	AspeedSoCState *s = ASPEED_SOC(dev);
586	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
587	SysBusDevice *gicbusdev;
588	DeviceState *gicdev;
589	QList *redist_region_count;
590	int i;
591
592	gicbusdev = SYS_BUS_DEVICE(&a->gic);
593	gicdev = DEVICE(&a->gic);
594	qdev_prop_set_uint32(gicdev, "revision", 3);
595	qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
596	qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);
597
598	redist_region_count = qlist_new();
599	qlist_append_int(redist_region_count, sc->num_cpus);
600	qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
601
602	if (!sysbus_realize(gicbusdev, errp)) {
603	return false;
604	}
605
606	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 0,
607	sc->memmap[ASPEED_GIC_DIST]);
608	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 1,
609	sc->memmap[ASPEED_GIC_REDIST]);
610
611	for (i = 0; i < sc->num_cpus; i++) {
612	DeviceState *cpudev = DEVICE(&a->cpu[i]);
613	int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;
614
615	const int timer_irq[] = {
616	[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
617	[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
618	[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
619	[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
620	};
621	int j;
622
623	for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
624	qdev_connect_gpio_out(cpudev, j,
625	qdev_get_gpio_in(gicdev, intidbase + timer_irq[j]));
626	}
627
628	qemu_irq irq = qdev_get_gpio_in(gicdev,
629	intidbase + ARCH_GIC_MAINT_IRQ);
630	qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
631	0, irq);
632	qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
633	qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ));
634
635	sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
636	sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
637	qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
638	sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
639	qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
640	sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
641	qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
642	sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus,
643	qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
644	sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus,
645	qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
646	}
647
648	return true;
649	}
650
651	static bool aspeed_soc_ast2700_pcie_realize(DeviceState dev, Error *errp)
652	{
653	AspeedSoCState *s = ASPEED_SOC(dev);
654	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
655	MemoryRegion *mmio_mr = NULL;
656	char name[64];
657	qemu_irq irq;
658	int i;
659
660	for (i = 0; i < sc->pcie_num; i++) {
661	if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) {
662	return false;
663	}
664	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0,
665	sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]);
666
667	object_property_set_int(OBJECT(&s->pcie[i]), "dram-base",
668	sc->memmap[ASPEED_DEV_SDRAM],
669	&error_abort);
670	object_property_set_link(OBJECT(&s->pcie[i]), "dram",
671	OBJECT(s->dram_mr), &error_abort);
672	if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) {
673	return false;
674	}
675	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0,
676	sc->memmap[ASPEED_DEV_PCIE0 + i]);
677	irq = aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_PCIE0 + i);
678	sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq);
679
680	mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc), 1);
681	snprintf(name, sizeof(name), "aspeed.pcie-mmio.%d", i);
682	memory_region_init_alias(&s->pcie_mmio_alias[i], OBJECT(&s->pcie[i].rc),
683	name, mmio_mr,
684	sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i],
685	0x20000000);
686	memory_region_add_subregion(s->memory,
687	sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i],
688	&s->pcie_mmio_alias[i]);
689	}
690
691	return true;
692	}
693
694	static void aspeed_soc_ast2700_realize(DeviceState dev, Error *errp)
695	{
696	int i;
697	Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
698	AspeedSoCState *s = ASPEED_SOC(dev);
699	AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
700	AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]);
701	AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]);
702	g_autofree char *name = NULL;
703	qemu_irq irq;
704	int uart;
705
706	if (qtest_enabled() && !target_aarch64()) {
707	g_assert_not_reached();
708	}
709
710	/* Default boot region (SPI memory or ROMs) */
711	memory_region_init(&s->spi_boot_container, OBJECT(s),
712	"aspeed.spi_boot_container", 0x400000000);
713	memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
714	&s->spi_boot_container);
715
716	/* CPU */
717	for (i = 0; i < sc->num_cpus; i++) {
718	object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
719	aspeed_calc_affinity(i), &error_abort);
720
721	object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
722	&error_abort);
723	object_property_set_link(OBJECT(&a->cpu[i]), "memory",
724	OBJECT(s->memory), &error_abort);
725
726	if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
727	return;
728	}
729	}
730
731	/* GIC */
732	if (!aspeed_soc_ast2700_gic_realize(dev, errp)) {
733	return;
734	}
735
736	/* INTC */
737	if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
738	return;
739	}
740
741	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
742	sc->memmap[ASPEED_DEV_INTC]);
743
744	/* INTCIO */
745	if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
746	return;
747	}
748
749	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
750	sc->memmap[ASPEED_DEV_INTCIO]);
751
752	/* INTCIOEXP0 */
753	if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
754	return;
755	}
756
757	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
758	sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);
759
760	/* INTCIOEXP1 */
761	if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
762	return;
763	}
764
765	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
766	sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);
767
768	/* irq sources -> orgates -> INTC */
769	for (i = 0; i < ic->num_inpins; i++) {
770	qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
771	qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
772	}
773
774	/* INTC -> GIC192 - GIC201 */
775	for (i = 0; i < ic->num_outpins; i++) {
776	sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
777	qdev_get_gpio_in(DEVICE(&a->gic),
778	ast2700_gic_intcmap[i].irq));
779	}
780
781	/* irq source -> orgates -> INTCIO */
782	for (i = 0; i < icio->num_inpins; i++) {
783	qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
784	qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
785	}
786
787	/* INTCIO -> INTC */
788	for (i = 0; i < icio->num_outpins; i++) {
789	sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
790	qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
791	}
792
793	/* SRAM */
794	name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
795	if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,
796	sc->sram_size[0], errp)) {
797	return;
798	}
799	memory_region_add_subregion(s->memory,
800	sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
801
802	/* VBOOTROM */
803	if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
804	0x20000, errp)) {
805	return;
806	}
807	memory_region_add_subregion(s->memory,
808	sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
809
810	/* SCU */
811	if (!sysbus_realize(SYS_BUS_DEVICE(&a->scu), errp)) {
812	return;
813	}
814	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->scu), 0,
815	sc->memmap[ASPEED_DEV_SCU]);
816
817	/* SCU1 */
818	if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
819	return;
820	}
821	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scuio), 0,
822	sc->memmap[ASPEED_DEV_SCUIO]);
823
824	/* UART */
825	for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
826	if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
827	sc->memmap[uart], errp)) {
828	return;
829	}
830	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
831	aspeed_soc_ast2700_get_irq(s, uart));
832	}
833
834	/* FMC, The number of CS is set at the board level */
835	object_property_set_int(OBJECT(&s->fmc), "dram-base",
836	sc->memmap[ASPEED_DEV_SDRAM],
837	&error_abort);
838	object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
839	&error_abort);
840	if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
841	return;
842	}
843	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
844	sc->memmap[ASPEED_DEV_FMC]);
845	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
846	ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
847	sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
848	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_FMC));
849
850	/* Set up an alias on the FMC CE0 region (boot default) */
851	MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
852	memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
853	fmc0_mmio, 0, memory_region_size(fmc0_mmio));
854	memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
855
856	/* SPI */
857	for (i = 0; i < sc->spis_num; i++) {
858	object_property_set_link(OBJECT(&s->spi[i]), "dram",
859	OBJECT(s->dram_mr), &error_abort);
860	if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
861	return;
862	}
863	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
864	sc->memmap[ASPEED_DEV_SPI0 + i]);
865	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
866	ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
867	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
868	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i));
869	}
870
871	/* EHCI */
872	for (i = 0; i < sc->ehcis_num; i++) {
873	object_property_set_int(OBJECT(&s->ehci[i]), "ctrldssegment-default",
874	sc->memmap[ASPEED_DEV_SDRAM] >> 32,
875	&error_abort);
876	object_property_set_bool(OBJECT(&s->ehci[i]), "caps-64bit-addr", true,
877	&error_abort);
878	if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
879	return;
880	}
881	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
882	sc->memmap[ASPEED_DEV_EHCI1 + i]);
883	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
884	aspeed_soc_ast2700_get_irq(s,
885	ASPEED_DEV_EHCI1 + i));
886	}
887
888	/*
889	* SDMC - SDRAM Memory Controller
890	* The SDMC controller is unlocked at SPL stage.
891	* At present, only supports to emulate booting
892	* start from u-boot stage. Set SDMC controller
893	* unlocked by default. It is a temporarily solution.
894	*/
895	object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
896	&error_abort);
897	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
898	return;
899	}
900	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
901	sc->memmap[ASPEED_DEV_SDMC]);
902
903	/* RAM */
904	if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
905	return;
906	}
907
908	/* Net */
909	for (i = 0; i < sc->macs_num; i++) {
910	object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
911	&error_abort);
912	object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
913	&error_abort);
914	if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
915	return;
916	}
917	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
918	sc->memmap[ASPEED_DEV_ETH1 + i]);
919	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
920	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ETH1 + i));
921
922	object_property_set_link(OBJECT(&s->mii[i]), "nic",
923	OBJECT(&s->ftgmac100[i]), &error_abort);
924	if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
925	return;
926	}
927
928	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0,
929	sc->memmap[ASPEED_DEV_MII1 + i]);
930	}
931
932	/* Watch dog */
933	for (i = 0; i < sc->wdts_num; i++) {
934	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
935	hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
936
937	object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&a->scu),
938	&error_abort);
939	if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
940	return;
941	}
942	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
943	}
944
945	/* SLI */
946	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
947	return;
948	}
949	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sli), 0,
950	sc->memmap[ASPEED_DEV_SLI]);
951
952	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
953	return;
954	}
955	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sliio), 0,
956	sc->memmap[ASPEED_DEV_SLIIO]);
957
958	/* ADC */
959	if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
960	return;
961	}
962	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
963	sc->memmap[ASPEED_DEV_ADC]);
964	sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
965	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
966
967	/* I2C */
968	object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
969	&error_abort);
970	if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
971	return;
972	}
973	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
974	sc->memmap[ASPEED_DEV_I2C]);
975	for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
976	/*
977	* The AST2700 I2C controller has one source INTC per bus.
978	*
979	* I2C bus interrupts are connected to the OR gate from bit 0 to bit
980	* 15, and the OR gate output pin is connected to the input pin of
981	* GICINT194 of INTCIO (IO Die). Then, the output pin is connected
982	* to the INTC (CPU Die) input pin, and its output pin is connected
983	* to the GIC.
984	*
985	* I2C bus 0 is connected to the OR gate at bit 0.
986	* I2C bus 15 is connected to the OR gate at bit 15.
987	*/
988	irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
989	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
990	}
991
992	/* GPIO */
993	if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
994	return;
995	}
996	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
997	sc->memmap[ASPEED_DEV_GPIO]);
998	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
999	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
1000
1001	/* SGPIO */
1002	for (i = 0; i < sc->sgpio_num; i++) {
1003	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {
1004	return;
1005	}
1006	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0,
1007	sc->memmap[ASPEED_DEV_SGPIOM0 + i]);
1008	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sgpiom[i]), 0,
1009	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SGPIOM0 + i));
1010	}
1011
1012	/* RTC */
1013	if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
1014	return;
1015	}
1016	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
1017	sc->memmap[ASPEED_DEV_RTC]);
1018	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
1019	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_RTC));
1020
1021	/* SDHCI */
1022	if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
1023	return;
1024	}
1025	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
1026	sc->memmap[ASPEED_DEV_SDHCI]);
1027	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
1028	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SDHCI));
1029
1030	/* eMMC */
1031	if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
1032	return;
1033	}
1034	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
1035	sc->memmap[ASPEED_DEV_EMMC]);
1036	sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
1037	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC));
1038
1039	/* Timer */
1040	object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&a->scu),
1041	&error_abort);
1042	if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
1043	return;
1044	}
1045	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
1046	sc->memmap[ASPEED_DEV_TIMER1]);
1047	for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
1048	irq = aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_TIMER1 + i);
1049	sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
1050	}
1051
1052	/* HACE */
1053	object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
1054	&error_abort);
1055	if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
1056	return;
1057	}
1058	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
1059	sc->memmap[ASPEED_DEV_HACE]);
1060	sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
1061	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_HACE));
1062
1063	/* PCIe Root Complex (RC) */
1064	if (!aspeed_soc_ast2700_pcie_realize(dev, errp)) {
1065	return;
1066	}
1067
1068	/* LTPI controller */
1069	for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
1070	AspeedLTPIState *ltpi_ctrl;
1071	hwaddr ltpi_base;
1072
1073	ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
1074	ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];
1075
1076	if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
1077	return;
1078	}
1079	aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
1080	}
1081
1082	/* IO Expander */
1083	for (i = 0; i < sc->ioexp_num; i++) {
1084	AspeedI2CClass *i2c_ctl;
1085
1086	qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
1087	object_property_set_link(OBJECT(&s->ioexp[i]), "dram",
1088	OBJECT(s->dram_mr), &error_abort);
1089	if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
1090	return;
1091	}
1092	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
1093	sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);
1094
1095	icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
1096	/* INTC_IOEXP internal: orgate[i] -> input[i] */
1097	for (int j = 0; j < icio->num_inpins; j++) {
1098	irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
1099	qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
1100	irq);
1101	}
1102
1103	/* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
1104	for (int j = 0; j < icio->num_outpins; j++) {
1105	irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
1106	sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
1107	irq);
1108	}
1109
1110	/* ADC */
1111	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
1112	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));
1113
1114	/* GPIO */
1115	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
1116	aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));
1117
1118	/* I2C */
1119	i2c_ctl = ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c);
1120	for (int j = 0; j < i2c_ctl->num_busses; j++) {
1121	/*
1122	* For I2C on AST1700:
1123	* I2C bus interrupts are connected to the OR gate from bit 0 to bit
1124	* 15, and the OR gate output pin is connected to the input pin of
1125	* GICINT192 of IO expander Interrupt controller (INTC2/3). Then,
1126	* the output pin is connected to the INTC (CPU Die) input pin, and
1127	* its output pin is connected to the GIC.
1128	*
1129	* I2C bus 0 is connected to the OR gate at bit 0.
1130	* I2C bus 15 is connected to the OR gate at bit 15.
1131	*/
1132	irq = aspeed_soc_ast2700_get_irq_index(s,
1133	ASPEED_DEV_IOEXP0_I2C + i,
1134	j);
1135	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]),
1136	0, irq);
1137	}
1138	}
1139
1140	aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
1141	"aspeed.dpmcu",
1142	sc->memmap[ASPEED_DEV_DPMCU],
1143	AST2700_SOC_DPMCU_SIZE);
1144	aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
1145	"aspeed.io",
1146	sc->memmap[ASPEED_DEV_IOMEM],
1147	AST2700_SOC_IO_SIZE);
1148	aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem0),
1149	"aspeed.iomem0",
1150	sc->memmap[ASPEED_DEV_IOMEM0],
1151	AST2700_SOC_IOMEM_SIZE);
1152	aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem1),
1153	"aspeed.iomem1",
1154	sc->memmap[ASPEED_DEV_IOMEM1],
1155	AST2700_SOC_IOMEM_SIZE);
1156	}
1157
1158	static void aspeed_soc_ast2700a1_class_init(ObjectClass oc, const void data)
1159	{
1160	static const char * const valid_cpu_types[] = {
1161	ARM_CPU_TYPE_NAME("cortex-a35"),
1162	NULL
1163	};
1164	DeviceClass *dc = DEVICE_CLASS(oc);
1165	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
1166
1167	/* Reason: The Aspeed SoC can only be instantiated from a board */
1168	dc->user_creatable = false;
1169	dc->realize = aspeed_soc_ast2700_realize;
1170
1171	sc->valid_cpu_types = valid_cpu_types;
1172	sc->silicon_rev = AST2700_A1_SILICON_REV;
1173	sc->sram_size[0] = 0x20000;
1174	sc->pcie_num = 3;
1175	sc->spis_num = 3;
1176	sc->sgpio_num = 2;
1177	sc->ehcis_num = 4;
1178	sc->wdts_num = 8;
1179	sc->macs_num = 3;
1180	sc->uarts_num = 13;
1181	sc->num_cpus = 4;
1182	sc->ioexp_num = 2;
1183	sc->uarts_base = ASPEED_DEV_UART0;
1184	sc->irqmap = aspeed_soc_ast2700a1_irqmap;
1185	sc->memmap = aspeed_soc_ast2700_memmap;
1186	}
1187
1188	static void aspeed_soc_ast2700a2_class_init(ObjectClass oc, const void data)
1189	{
1190	static const char * const valid_cpu_types[] = {
1191	ARM_CPU_TYPE_NAME("cortex-a35"),
1192	NULL
1193	};
1194	DeviceClass *dc = DEVICE_CLASS(oc);
1195	AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
1196
1197	/* Reason: The Aspeed SoC can only be instantiated from a board */
1198	dc->user_creatable = false;
1199	dc->realize = aspeed_soc_ast2700_realize;
1200
1201	sc->valid_cpu_types = valid_cpu_types;
1202	sc->silicon_rev = AST2700_A2_SILICON_REV;
1203	sc->sram_size[0] = 0x20000;
1204	sc->pcie_num = 3;
1205	sc->spis_num = 3;
1206	sc->sgpio_num = 2;
1207	sc->ehcis_num = 4;
1208	sc->wdts_num = 8;
1209	sc->macs_num = 3;
1210	sc->uarts_num = 13;
1211	sc->num_cpus = 4;
1212	sc->ioexp_num = 2;
1213	sc->uarts_base = ASPEED_DEV_UART0;
1214	sc->irqmap = aspeed_soc_ast2700a1_irqmap;
1215	sc->memmap = aspeed_soc_ast2700_memmap;
1216	}
1217
1218	static const TypeInfo aspeed_soc_ast27x0_types[] = {
1219	{
1220	.name = TYPE_ASPEED27X0_SOC,
1221	.parent = TYPE_ASPEED_SOC,
1222	.instance_size = sizeof(Aspeed27x0SoCState),
1223	.abstract = true,
1224	},
1225	{
1226	.name = "ast2700-a1",
1227	.parent = TYPE_ASPEED27X0_SOC,
1228	.instance_init = aspeed_soc_ast2700_init,
1229	.class_init = aspeed_soc_ast2700a1_class_init,
1230	},
1231	{
1232	.name = "ast2700-a2",
1233	.parent = TYPE_ASPEED27X0_SOC,
1234	.instance_init = aspeed_soc_ast2700_init,
1235	.class_init = aspeed_soc_ast2700a2_class_init,
1236	},
1237	};
1238
1239	DEFINE_TYPES(aspeed_soc_ast27x0_types)