| 1 | /* |
| 2 | * ASPEED SoC family |
| 3 | * |
| 4 | * Andrew Jeffery <andrew@aj.id.au> |
| 5 | * Jeremy Kerr <jk@ozlabs.org> |
| 6 | * |
| 7 | * Copyright 2016 IBM Corp. |
| 8 | * |
| 9 | * This code is licensed under the GPL version 2 or later. See |
| 10 | * the COPYING file in the top-level directory. |
| 11 | */ |
| 12 | |
| 13 | #include "qemu/osdep.h" |
| 14 | #include "qapi/error.h" |
| 15 | #include "hw/core/qdev-properties.h" |
| 16 | #include "hw/misc/unimp.h" |
| 17 | #include "hw/arm/aspeed_soc.h" |
| 18 | #include "hw/char/serial-mm.h" |
| 19 | #include "system/blockdev.h" |
| 20 | #include "system/block-backend.h" |
| 21 | #include "hw/core/loader.h" |
| 22 | #include "qemu/datadir.h" |
| 23 | |
| 24 | |
| 25 | const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types) |
| 26 | { |
| 27 | assert(valid_cpu_types); |
| 28 | assert(valid_cpu_types[0]); |
| 29 | assert(!valid_cpu_types[1]); |
| 30 | return valid_cpu_types[0]; |
| 31 | } |
| 32 | |
| 33 | bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm, |
| 34 | const hwaddr addr, Error **errp) |
| 35 | { |
| 36 | /* Chardev property is set by the machine. */ |
| 37 | qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); |
| 38 | qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); |
| 39 | qdev_set_legacy_instance_id(DEVICE(smm), addr, 2); |
| 40 | qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); |
| 41 | if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { |
| 42 | return false; |
| 43 | } |
| 44 | |
| 45 | aspeed_mmio_map(memory, SYS_BUS_DEVICE(smm), 0, addr); |
| 46 | return true; |
| 47 | } |
| 48 | |
| 49 | void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base, |
| 50 | int uarts_num, Chardev *chr) |
| 51 | { |
| 52 | int uart_first = aspeed_uart_first(uarts_base); |
| 53 | int uart_index = aspeed_uart_index(dev); |
| 54 | int i = uart_index - uart_first; |
| 55 | |
| 56 | g_assert(0 <= i && i < ASPEED_UARTS_NUM && i < uarts_num); |
| 57 | qdev_prop_set_chr(DEVICE(&uart[i]), "chardev", chr); |
| 58 | } |
| 59 | |
| 60 | /* |
| 61 | * SDMC should be realized first to get correct RAM size and max size |
| 62 | * values |
| 63 | */ |
| 64 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) |
| 65 | { |
| 66 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| 67 | ram_addr_t ram_size, max_ram_size; |
| 68 | |
| 69 | ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", |
| 70 | &error_abort); |
| 71 | max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", |
| 72 | &error_abort); |
| 73 | |
| 74 | memory_region_init(&s->dram_container, OBJECT(s), "ram-container", |
| 75 | max_ram_size); |
| 76 | memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); |
| 77 | |
| 78 | /* |
| 79 | * Add a memory region beyond the RAM region to let firmwares scan |
| 80 | * the address space with load/store and guess how much RAM the |
| 81 | * SoC has. |
| 82 | */ |
| 83 | if (ram_size < max_ram_size) { |
| 84 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); |
| 85 | |
| 86 | qdev_prop_set_string(dev, "name", "ram-empty"); |
| 87 | qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); |
| 88 | if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { |
| 89 | return false; |
| 90 | } |
| 91 | |
| 92 | memory_region_add_subregion_overlap(&s->dram_container, ram_size, |
| 93 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); |
| 94 | } |
| 95 | |
| 96 | memory_region_add_subregion(s->memory, |
| 97 | sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); |
| 98 | return true; |
| 99 | } |
| 100 | |
| 101 | void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n, |
| 102 | hwaddr addr) |
| 103 | { |
| 104 | memory_region_add_subregion(memory, addr, sysbus_mmio_get_region(dev, n)); |
| 105 | } |
| 106 | |
| 107 | void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, |
| 108 | const char *name, hwaddr addr, uint64_t size) |
| 109 | { |
| 110 | qdev_prop_set_string(DEVICE(dev), "name", name); |
| 111 | qdev_prop_set_uint64(DEVICE(dev), "size", size); |
| 112 | sysbus_realize(dev, &error_abort); |
| 113 | |
| 114 | memory_region_add_subregion_overlap(memory, addr, |
| 115 | sysbus_mmio_get_region(dev, 0), -1000); |
| 116 | } |
| 117 | |
| 118 | void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
| 119 | unsigned int count, int unit0) |
| 120 | { |
| 121 | int i; |
| 122 | |
| 123 | if (!flashtype) { |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | for (i = 0; i < count; ++i) { |
| 128 | DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); |
| 129 | DeviceState *dev; |
| 130 | |
| 131 | dev = qdev_new(flashtype); |
| 132 | if (dinfo) { |
| 133 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
| 134 | } |
| 135 | qdev_prop_set_uint8(dev, "cs", i); |
| 136 | qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, |
| 141 | Error **errp) |
| 142 | { |
| 143 | g_autofree void *storage = NULL; |
| 144 | int64_t size; |
| 145 | |
| 146 | /* |
| 147 | * The block backend size should have already been 'validated' by |
| 148 | * the creation of the m25p80 object. |
| 149 | */ |
| 150 | size = blk_getlength(blk); |
| 151 | if (size <= 0) { |
| 152 | error_setg(errp, "failed to get flash size"); |
| 153 | return; |
| 154 | } |
| 155 | |
| 156 | if (rom_size > size) { |
| 157 | rom_size = size; |
| 158 | } |
| 159 | |
| 160 | storage = g_malloc0(rom_size); |
| 161 | if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { |
| 162 | error_setg(errp, "failed to read the initial flash content"); |
| 163 | return; |
| 164 | } |
| 165 | |
| 166 | rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); |
| 167 | } |
| 168 | |
| 169 | /* |
| 170 | * Create a ROM and copy the flash contents at the expected address |
| 171 | * (0x0). Boots faster than execute-in-place. |
| 172 | */ |
| 173 | void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk, |
| 174 | MemoryRegion *boot_rom, uint64_t rom_size) |
| 175 | { |
| 176 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); |
| 177 | |
| 178 | memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size, |
| 179 | &error_abort); |
| 180 | memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, |
| 181 | boot_rom, 1); |
| 182 | aspeed_write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], rom_size, |
| 183 | &error_abort); |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * This function locates the vbootrom image file specified via the command line |
| 188 | * using the -bios option. It loads the specified image into the vbootrom |
| 189 | * memory region and handles errors if the file cannot be found or loaded. |
| 190 | */ |
| 191 | void aspeed_load_vbootrom(AspeedSoCState *soc, const char *bios_name, |
| 192 | Error **errp) |
| 193 | { |
| 194 | g_autofree char *filename = NULL; |
| 195 | int ret; |
| 196 | |
| 197 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 198 | if (!filename) { |
| 199 | error_setg(errp, "Could not find vbootrom image '%s'", bios_name); |
| 200 | return; |
| 201 | } |
| 202 | |
| 203 | ret = load_image_mr(filename, &soc->vbootrom); |
| 204 | if (ret < 0) { |
| 205 | error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); |
| 206 | return; |
| 207 | } |
| 208 | } |
| 209 | |
| 210 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) |
| 211 | { |
| 212 | AspeedSoCState *s = ASPEED_SOC(dev); |
| 213 | |
| 214 | if (!s->memory) { |
| 215 | error_setg(errp, "'memory' link is not set"); |
| 216 | return; |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | static bool aspeed_soc_boot_from_emmc(AspeedSoCState *s) |
| 221 | { |
| 222 | return false; |
| 223 | } |
| 224 | |
| 225 | static const Property aspeed_soc_properties[] = { |
| 226 | DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, |
| 227 | MemoryRegion *), |
| 228 | DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, |
| 229 | MemoryRegion *), |
| 230 | }; |
| 231 | |
| 232 | static void aspeed_soc_class_init(ObjectClass *oc, const void *data) |
| 233 | { |
| 234 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 235 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); |
| 236 | |
| 237 | dc->realize = aspeed_soc_realize; |
| 238 | device_class_set_props(dc, aspeed_soc_properties); |
| 239 | sc->boot_from_emmc = aspeed_soc_boot_from_emmc; |
| 240 | } |
| 241 | |
| 242 | static const TypeInfo aspeed_soc_types[] = { |
| 243 | { |
| 244 | .name = TYPE_ASPEED_SOC, |
| 245 | .parent = TYPE_DEVICE, |
| 246 | .instance_size = sizeof(AspeedSoCState), |
| 247 | .class_size = sizeof(AspeedSoCClass), |
| 248 | .class_init = aspeed_soc_class_init, |
| 249 | .abstract = true, |
| 250 | }, |
| 251 | }; |
| 252 | |
| 253 | DEFINE_TYPES(aspeed_soc_types) |