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1 /*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
4 *
5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
6 * Written by Andrew Baumann
7 *
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "qemu/module.h"
15 #include "hw/arm/bcm2835_peripherals.h"
16 #include "hw/misc/bcm2835_mbox_defs.h"
17 #include "hw/arm/raspi_platform.h"
18 #include "system/system.h"
19
20 /* Peripheral base address on the VC (GPU) system bus */
21 #define BCM2835_VC_PERI_BASE 0x7e000000
22
23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
24 #define BCM2835_SDHC_CAPAREG 0x52134b4
25
26 /*
27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ,
28 * while channels 11--14 share one IRQ:
29 */
30 #define SEPARATE_DMA_IRQ_MAX 10
31 #define ORGATED_DMA_IRQ_COUNT 4
32
33 /* All three I2C controllers share the same IRQ */
34 #define ORGATED_I2C_IRQ_COUNT 3
35
36 void create_unimp(BCMSocPeripheralBaseState *ps,
37 UnimplementedDeviceState *uds,
38 const char *name, hwaddr ofs, hwaddr size)
39 {
40 object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
41 qdev_prop_set_string(DEVICE(uds), "name", name);
42 qdev_prop_set_uint64(DEVICE(uds), "size", size);
43 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
44 memory_region_add_subregion_overlap(&ps->peri_mr, ofs,
45 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000);
46 }
47
48 static void bcm2835_peripherals_init(Object *obj)
49 {
50 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj);
51 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(obj);
52
53 /* Random Number Generator */
54 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG);
55
56 /* Thermal */
57 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL);
58
59 /* GPIO */
60 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO);
61
62 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
63 OBJECT(&s_base->sdhci.sdbus));
64 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
65 OBJECT(&s_base->sdhost.sdbus));
66
67 /* Gated DMA interrupts */
68 object_initialize_child(obj, "orgated-dma-irq",
69 &s_base->orgated_dma_irq, TYPE_OR_IRQ);
70 object_property_set_int(OBJECT(&s_base->orgated_dma_irq), "num-lines",
71 ORGATED_DMA_IRQ_COUNT, &error_abort);
72 }
73
74 static void raspi_peripherals_base_init(Object *obj)
75 {
76 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(obj);
77 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_GET_CLASS(obj);
78
79 /* Memory region for peripheral devices, which we export to our parent */
80 memory_region_init(&s->peri_mr, obj, "bcm2835-peripherals", bc->peri_size);
81 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr);
82
83 /* Internal memory region for peripheral bus addresses (not exported) */
84 memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32);
85
86 /* Internal memory region for request/response communication with
87 * mailbox-addressable peripherals (not exported)
88 */
89 memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox",
90 MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT);
91
92 /* Interrupt Controller */
93 object_initialize_child(obj, "ic", &s->ic, TYPE_BCM2835_IC);
94
95 /* SYS Timer */
96 object_initialize_child(obj, "systimer", &s->systmr,
97 TYPE_BCM2835_SYSTIMER);
98
99 /* UART0 */
100 object_initialize_child(obj, "uart0", &s->uart0, TYPE_PL011);
101
102 /* AUX / UART1 */
103 object_initialize_child(obj, "aux", &s->aux, TYPE_BCM2835_AUX);
104
105 /* Mailboxes */
106 object_initialize_child(obj, "mbox", &s->mboxes, TYPE_BCM2835_MBOX);
107
108 object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr",
109 OBJECT(&s->mbox_mr));
110
111 /* Framebuffer */
112 object_initialize_child(obj, "fb", &s->fb, TYPE_BCM2835_FB);
113 object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size");
114 object_property_add_alias(obj, "vcram-base", OBJECT(&s->fb), "vcram-base");
115
116 object_property_add_const_link(OBJECT(&s->fb), "dma-mr",
117 OBJECT(&s->gpu_bus_mr));
118
119 /* OTP */
120 object_initialize_child(obj, "bcm2835-otp", &s->otp,
121 TYPE_BCM2835_OTP);
122
123 /* Property channel */
124 object_initialize_child(obj, "property", &s->property,
125 TYPE_BCM2835_PROPERTY);
126 object_property_add_alias(obj, "board-rev", OBJECT(&s->property),
127 "board-rev");
128 object_property_add_alias(obj, "command-line", OBJECT(&s->property),
129 "command-line");
130
131 object_property_add_const_link(OBJECT(&s->property), "fb",
132 OBJECT(&s->fb));
133 object_property_add_const_link(OBJECT(&s->property), "dma-mr",
134 OBJECT(&s->gpu_bus_mr));
135 object_property_add_const_link(OBJECT(&s->property), "otp",
136 OBJECT(&s->otp));
137
138 /* Extended Mass Media Controller */
139 object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI);
140
141 /* SDHOST */
142 object_initialize_child(obj, "sdhost", &s->sdhost, TYPE_BCM2835_SDHOST);
143
144 /* DMA Channels */
145 object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA);
146
147 object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
148 OBJECT(&s->gpu_bus_mr));
149
150 /* Mphi */
151 object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI);
152
153 /* DWC2 */
154 object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
155
156 /* CPRMAN clock manager */
157 object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN);
158
159 object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
160 OBJECT(&s->gpu_bus_mr));
161
162 /* Power Management */
163 object_initialize_child(obj, "powermgt", &s->powermgt,
164 TYPE_BCM2835_POWERMGT);
165
166 /* SPI */
167 object_initialize_child(obj, "bcm2835-spi0", &s->spi[0],
168 TYPE_BCM2835_SPI);
169
170 /* I2C */
171 object_initialize_child(obj, "bcm2835-i2c0", &s->i2c[0],
172 TYPE_BCM2835_I2C);
173 object_initialize_child(obj, "bcm2835-i2c1", &s->i2c[1],
174 TYPE_BCM2835_I2C);
175 object_initialize_child(obj, "bcm2835-i2c2", &s->i2c[2],
176 TYPE_BCM2835_I2C);
177
178 object_initialize_child(obj, "orgated-i2c-irq",
179 &s->orgated_i2c_irq, TYPE_OR_IRQ);
180 object_property_set_int(OBJECT(&s->orgated_i2c_irq), "num-lines",
181 ORGATED_I2C_IRQ_COUNT, &error_abort);
182 object_initialize_child(obj, "orgated-i2c-irq-splitter",
183 &s->orgated_i2c_irq_splitter, TYPE_SPLIT_IRQ);
184 }
185
186 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
187 {
188 MemoryRegion *mphi_mr;
189 BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev);
190 BCMSocPeripheralBaseState *s_base = BCM_SOC_PERIPHERALS_BASE(dev);
191 int n;
192
193 bcm_soc_peripherals_common_realize(dev, errp);
194
195 /* Extended Mass Media Controller */
196 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0,
197 qdev_get_gpio_in_named(DEVICE(&s_base->ic), BCM2835_IC_GPU_IRQ,
198 INTERRUPT_ARASANSDIO));
199
200 /* Connect DMA 0-12 to the interrupt controller */
201 for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) {
202 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma), n,
203 qdev_get_gpio_in_named(DEVICE(&s_base->ic),
204 BCM2835_IC_GPU_IRQ,
205 INTERRUPT_DMA0 + n));
206 }
207
208 if (!qdev_realize(DEVICE(&s_base->orgated_dma_irq), NULL, errp)) {
209 return;
210 }
211 for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) {
212 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->dma),
213 SEPARATE_DMA_IRQ_MAX + 1 + n,
214 qdev_get_gpio_in(DEVICE(&s_base->orgated_dma_irq), n));
215 }
216 qdev_connect_gpio_out(DEVICE(&s_base->orgated_dma_irq), 0,
217 qdev_get_gpio_in_named(DEVICE(&s_base->ic),
218 BCM2835_IC_GPU_IRQ,
219 INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1));
220
221 /* Random Number Generator */
222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) {
223 return;
224 }
225 memory_region_add_subregion(
226 &s_base->peri_mr, RNG_OFFSET,
227 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));
228
229 /* THERMAL */
230 if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) {
231 return;
232 }
233 memory_region_add_subregion(&s_base->peri_mr, THERMAL_OFFSET,
234 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0));
235
236 /* Map MPHI to the peripherals memory map */
237 mphi_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s_base->mphi), 0);
238 memory_region_add_subregion(&s_base->peri_mr, MPHI_OFFSET, mphi_mr);
239
240 /* GPIO */
241 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
242 return;
243 }
244 memory_region_add_subregion(
245 &s_base->peri_mr, GPIO_OFFSET,
246 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
247
248 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
249 }
250
251 void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp)
252 {
253 BCMSocPeripheralBaseState *s = BCM_SOC_PERIPHERALS_BASE(dev);
254 Object *obj;
255 MemoryRegion *ram;
256 Error *err = NULL;
257 uint64_t ram_size, vcram_size, vcram_base;
258 int n;
259
260 obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
261
262 ram = MEMORY_REGION(obj);
263 ram_size = memory_region_size(ram);
264
265 /* Map peripherals and RAM into the GPU address space. */
266 memory_region_init_alias(&s->peri_mr_alias, OBJECT(s),
267 "bcm2835-peripherals", &s->peri_mr, 0,
268 memory_region_size(&s->peri_mr));
269
270 memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE,
271 &s->peri_mr_alias, 1);
272
273 /* RAM is aliased four times (different cache configurations) on the GPU */
274 for (n = 0; n < 4; n++) {
275 memory_region_init_alias(&s->ram_alias[n], OBJECT(s),
276 "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size);
277 memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30,
278 &s->ram_alias[n], 0);
279 }
280
281 /* Interrupt Controller */
282 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ic), errp)) {
283 return;
284 }
285
286 /* CPRMAN clock manager */
287 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) {
288 return;
289 }
290 memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
291 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
292 qdev_connect_clock_in(DEVICE(&s->uart0), "clk",
293 qdev_get_clock_out(DEVICE(&s->cprman), "uart-out"));
294
295 memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
296 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
297 sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
298
299 /* Sys Timer */
300 if (!sysbus_realize(SYS_BUS_DEVICE(&s->systmr), errp)) {
301 return;
302 }
303 memory_region_add_subregion(&s->peri_mr, ST_OFFSET,
304 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0));
305 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0,
306 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
307 INTERRUPT_TIMER0));
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 1,
309 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
310 INTERRUPT_TIMER1));
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 2,
312 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
313 INTERRUPT_TIMER2));
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 3,
315 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
316 INTERRUPT_TIMER3));
317
318 /* UART0 */
319 qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
320 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart0), errp)) {
321 return;
322 }
323
324 memory_region_add_subregion(&s->peri_mr, UART0_OFFSET,
325 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0));
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0,
327 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
328 INTERRUPT_UART0));
329
330 /* AUX / UART1 */
331 qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1));
332
333 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aux), errp)) {
334 return;
335 }
336
337 memory_region_add_subregion(&s->peri_mr, AUX_OFFSET,
338 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->aux), 0));
339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aux), 0,
340 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
341 INTERRUPT_AUX));
342
343 /* Mailboxes */
344 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mboxes), errp)) {
345 return;
346 }
347
348 memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET,
349 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0));
350 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0,
351 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
352 INTERRUPT_ARM_MAILBOX));
353
354 /* Framebuffer */
355 vcram_size = object_property_get_uint(OBJECT(s), "vcram-size", &err);
356 if (err) {
357 error_propagate(errp, err);
358 return;
359 }
360
361 vcram_base = object_property_get_uint(OBJECT(s), "vcram-base", &err);
362 if (err) {
363 error_propagate(errp, err);
364 return;
365 }
366
367 if (vcram_base == 0) {
368 vcram_base = ram_size - vcram_size;
369 }
370 vcram_base = MIN(vcram_base, UPPER_RAM_BASE - vcram_size);
371
372 if (!object_property_set_uint(OBJECT(&s->fb), "vcram-base", vcram_base,
373 errp)) {
374 return;
375 }
376 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fb), errp)) {
377 return;
378 }
379
380 memory_region_add_subregion(&s->mbox_mr, MBOX_CHAN_FB << MBOX_AS_CHAN_SHIFT,
381 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->fb), 0));
382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0,
383 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
384
385 /* OTP */
386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
387 return;
388 }
389
390 memory_region_add_subregion(&s->peri_mr, OTP_OFFSET,
391 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->otp), 0));
392
393 /* Property channel */
394 if (!sysbus_realize(SYS_BUS_DEVICE(&s->property), errp)) {
395 return;
396 }
397
398 memory_region_add_subregion(&s->mbox_mr,
399 MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT,
400 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0));
401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,
402 qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
403
404 /* Extended Mass Media Controller
405 *
406 * Compatible with:
407 * - SD Host Controller Specification Version 3.0 Draft 1.0
408 * - SDIO Specification Version 3.0
409 * - MMC Specification Version 4.4
410 *
411 * For the exact details please refer to the Arasan documentation:
412 * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf
413 */
414 object_property_set_uint(OBJECT(&s->sdhci), "sd-spec-version", 3,
415 &error_abort);
416 object_property_set_uint(OBJECT(&s->sdhci), "capareg",
417 BCM2835_SDHC_CAPAREG, &error_abort);
418 object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true,
419 &error_abort);
420 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
421 return;
422 }
423
424 memory_region_add_subregion(&s->peri_mr, EMMC1_OFFSET,
425 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0));
426
427 /* SDHOST */
428 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhost), errp)) {
429 return;
430 }
431
432 memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
433 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
435 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
436 INTERRUPT_SDIO));
437
438 /* DMA Channels */
439 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) {
440 return;
441 }
442
443 memory_region_add_subregion(&s->peri_mr, DMA_OFFSET,
444 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0));
445 memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET,
446 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1));
447
448 /* Mphi */
449 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mphi), errp)) {
450 return;
451 }
452
453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
454 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
455 INTERRUPT_HOSTPORT));
456
457 /* DWC2 */
458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dwc2), errp)) {
459 return;
460 }
461
462 memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET,
463 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0));
464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0,
465 qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
466 INTERRUPT_USB));
467
468 /* Power Management */
469 if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
470 return;
471 }
472
473 memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
474 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
475
476 /* SPI */
477 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[0]), errp)) {
478 return;
479 }
480
481 memory_region_add_subregion(&s->peri_mr, SPI0_OFFSET,
482 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi[0]), 0));
483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[0]), 0,
484 qdev_get_gpio_in_named(DEVICE(&s->ic),
485 BCM2835_IC_GPU_IRQ,
486 INTERRUPT_SPI));
487
488 /* I2C */
489 for (n = 0; n < 3; n++) {
490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[n]), errp)) {
491 return;
492 }
493 }
494
495 memory_region_add_subregion(&s->peri_mr, BSC0_OFFSET,
496 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[0]), 0));
497 memory_region_add_subregion(&s->peri_mr, BSC1_OFFSET,
498 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[1]), 0));
499 memory_region_add_subregion(&s->peri_mr, BSC2_OFFSET,
500 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c[2]), 0));
501
502 if (!qdev_realize(DEVICE(&s->orgated_i2c_irq), NULL, errp)) {
503 return;
504 }
505 for (n = 0; n < ORGATED_I2C_IRQ_COUNT; n++) {
506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[n]), 0,
507 qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq), n));
508 }
509
510 qdev_prop_set_uint32(DEVICE(&s->orgated_i2c_irq_splitter), "num-lines", 2);
511 if (!qdev_realize(DEVICE(&s->orgated_i2c_irq_splitter), NULL, errp)) {
512 return;
513 }
514 qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq), 0,
515 qdev_get_gpio_in(DEVICE(&s->orgated_i2c_irq_splitter), 0));
516 qdev_connect_gpio_out(DEVICE(&s->orgated_i2c_irq_splitter), 0,
517 qdev_get_gpio_in_named(DEVICE(&s->ic),
518 BCM2835_IC_GPU_IRQ,
519 INTERRUPT_I2C));
520
521 create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
522 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
523 create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
524 create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
525 create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100);
526 create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
527 create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
528 create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
529 create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
530 }
531
532 static void bcm2835_peripherals_class_init(ObjectClass *oc, const void *data)
533 {
534 DeviceClass *dc = DEVICE_CLASS(oc);
535 BCMSocPeripheralBaseClass *bc = BCM_SOC_PERIPHERALS_BASE_CLASS(oc);
536
537 bc->peri_size = 0x1000000;
538 dc->realize = bcm2835_peripherals_realize;
539 }
540
541 static const TypeInfo bcm2835_peripherals_types[] = {
542 {
543 .name = TYPE_BCM2835_PERIPHERALS,
544 .parent = TYPE_BCM_SOC_PERIPHERALS_BASE,
545 .instance_size = sizeof(BCM2835PeripheralState),
546 .instance_init = bcm2835_peripherals_init,
547 .class_init = bcm2835_peripherals_class_init,
548 }, {
549 .name = TYPE_BCM_SOC_PERIPHERALS_BASE,
550 .parent = TYPE_SYS_BUS_DEVICE,
551 .instance_size = sizeof(BCMSocPeripheralBaseState),
552 .instance_init = raspi_peripherals_base_init,
553 .class_size = sizeof(BCMSocPeripheralBaseClass),
554 .abstract = true,
555 }
556 };
557
558 DEFINE_TYPES(bcm2835_peripherals_types)