| 1 | /* |
| 2 | * Samsung exynos4210 SoC emulation |
| 3 | * |
| 4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. |
| 5 | * Maksim Kozlov <m.kozlov@samsung.com> |
| 6 | * Evgeny Voevodin <e.voevodin@samsung.com> |
| 7 | * Igor Mitsyanko <i.mitsyanko@samsung.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 17 | * for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include "qemu/osdep.h" |
| 25 | #include "qapi/error.h" |
| 26 | #include "exec/tswap.h" |
| 27 | #include "target/arm/cpu.h" |
| 28 | #include "hw/cpu/a9mpcore.h" |
| 29 | #include "hw/core/irq.h" |
| 30 | #include "system/blockdev.h" |
| 31 | #include "system/system.h" |
| 32 | #include "hw/core/sysbus.h" |
| 33 | #include "hw/arm/boot.h" |
| 34 | #include "hw/core/loader.h" |
| 35 | #include "hw/core/qdev-properties.h" |
| 36 | #include "hw/arm/exynos4210.h" |
| 37 | #include "hw/sd/sdhci.h" |
| 38 | #include "hw/usb/hcd-ehci.h" |
| 39 | #include "target/arm/cpu-qom.h" |
| 40 | |
| 41 | #define EXYNOS4210_CHIPID_ADDR 0x10000000 |
| 42 | |
| 43 | /* PWM */ |
| 44 | #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 |
| 45 | |
| 46 | /* RTC */ |
| 47 | #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 |
| 48 | |
| 49 | /* MCT */ |
| 50 | #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 |
| 51 | |
| 52 | /* I2C */ |
| 53 | #define EXYNOS4210_I2C_SHIFT 0x00010000 |
| 54 | #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 |
| 55 | /* Interrupt Group of External Interrupt Combiner for I2C */ |
| 56 | #define EXYNOS4210_I2C_INTG 27 |
| 57 | #define EXYNOS4210_HDMI_INTG 16 |
| 58 | |
| 59 | /* UART's definitions */ |
| 60 | #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 |
| 61 | #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 |
| 62 | #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 |
| 63 | #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 |
| 64 | #define EXYNOS4210_UART0_FIFO_SIZE 256 |
| 65 | #define EXYNOS4210_UART1_FIFO_SIZE 64 |
| 66 | #define EXYNOS4210_UART2_FIFO_SIZE 16 |
| 67 | #define EXYNOS4210_UART3_FIFO_SIZE 16 |
| 68 | /* Interrupt Group of External Interrupt Combiner for UART */ |
| 69 | #define EXYNOS4210_UART_INT_GRP 26 |
| 70 | |
| 71 | /* External GIC */ |
| 72 | #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 |
| 73 | #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 |
| 74 | |
| 75 | /* Combiner */ |
| 76 | #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 |
| 77 | #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 |
| 78 | |
| 79 | /* SD/MMC host controllers */ |
| 80 | #define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 |
| 81 | #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 |
| 82 | #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ |
| 83 | 0x00010000 * (n)) |
| 84 | #define EXYNOS4210_SDHCI_NUMBER 4 |
| 85 | |
| 86 | /* PMU SFR base address */ |
| 87 | #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 |
| 88 | |
| 89 | /* Clock controller SFR base address */ |
| 90 | #define EXYNOS4210_CLK_BASE_ADDR 0x10030000 |
| 91 | |
| 92 | /* PRNG/HASH SFR base address */ |
| 93 | #define EXYNOS4210_RNG_BASE_ADDR 0x10830400 |
| 94 | |
| 95 | /* Display controllers (FIMD) */ |
| 96 | #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 |
| 97 | |
| 98 | /* EHCI */ |
| 99 | #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 |
| 100 | |
| 101 | /* DMA */ |
| 102 | #define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 |
| 103 | #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 |
| 104 | #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 |
| 105 | |
| 106 | #define GIC_EXT_IRQS 64 /* FIXME: verify for this SoC */ |
| 107 | |
| 108 | enum ExtGicId { |
| 109 | EXT_GIC_ID_MDMA_LCD0 = 66, |
| 110 | EXT_GIC_ID_PDMA0, |
| 111 | EXT_GIC_ID_PDMA1, |
| 112 | EXT_GIC_ID_TIMER0, |
| 113 | EXT_GIC_ID_TIMER1, |
| 114 | EXT_GIC_ID_TIMER2, |
| 115 | EXT_GIC_ID_TIMER3, |
| 116 | EXT_GIC_ID_TIMER4, |
| 117 | EXT_GIC_ID_MCT_L0, |
| 118 | EXT_GIC_ID_WDT, |
| 119 | EXT_GIC_ID_RTC_ALARM, |
| 120 | EXT_GIC_ID_RTC_TIC, |
| 121 | EXT_GIC_ID_GPIO_XB, |
| 122 | EXT_GIC_ID_GPIO_XA, |
| 123 | EXT_GIC_ID_MCT_L1, |
| 124 | EXT_GIC_ID_IEM_APC, |
| 125 | EXT_GIC_ID_IEM_IEC, |
| 126 | EXT_GIC_ID_NFC, |
| 127 | EXT_GIC_ID_UART0, |
| 128 | EXT_GIC_ID_UART1, |
| 129 | EXT_GIC_ID_UART2, |
| 130 | EXT_GIC_ID_UART3, |
| 131 | EXT_GIC_ID_UART4, |
| 132 | EXT_GIC_ID_MCT_G0, |
| 133 | EXT_GIC_ID_I2C0, |
| 134 | EXT_GIC_ID_I2C1, |
| 135 | EXT_GIC_ID_I2C2, |
| 136 | EXT_GIC_ID_I2C3, |
| 137 | EXT_GIC_ID_I2C4, |
| 138 | EXT_GIC_ID_I2C5, |
| 139 | EXT_GIC_ID_I2C6, |
| 140 | EXT_GIC_ID_I2C7, |
| 141 | EXT_GIC_ID_SPI0, |
| 142 | EXT_GIC_ID_SPI1, |
| 143 | EXT_GIC_ID_SPI2, |
| 144 | EXT_GIC_ID_MCT_G1, |
| 145 | EXT_GIC_ID_USB_HOST, |
| 146 | EXT_GIC_ID_USB_DEVICE, |
| 147 | EXT_GIC_ID_MODEMIF, |
| 148 | EXT_GIC_ID_HSMMC0, |
| 149 | EXT_GIC_ID_HSMMC1, |
| 150 | EXT_GIC_ID_HSMMC2, |
| 151 | EXT_GIC_ID_HSMMC3, |
| 152 | EXT_GIC_ID_SDMMC, |
| 153 | EXT_GIC_ID_MIPI_CSI_4LANE, |
| 154 | EXT_GIC_ID_MIPI_DSI_4LANE, |
| 155 | EXT_GIC_ID_MIPI_CSI_2LANE, |
| 156 | EXT_GIC_ID_MIPI_DSI_2LANE, |
| 157 | EXT_GIC_ID_ONENAND_AUDI, |
| 158 | EXT_GIC_ID_ROTATOR, |
| 159 | EXT_GIC_ID_FIMC0, |
| 160 | EXT_GIC_ID_FIMC1, |
| 161 | EXT_GIC_ID_FIMC2, |
| 162 | EXT_GIC_ID_FIMC3, |
| 163 | EXT_GIC_ID_JPEG, |
| 164 | EXT_GIC_ID_2D, |
| 165 | EXT_GIC_ID_PCIe, |
| 166 | EXT_GIC_ID_MIXER, |
| 167 | EXT_GIC_ID_HDMI, |
| 168 | EXT_GIC_ID_HDMI_I2C, |
| 169 | EXT_GIC_ID_MFC, |
| 170 | EXT_GIC_ID_TVENC, |
| 171 | }; |
| 172 | |
| 173 | enum ExtInt { |
| 174 | EXT_GIC_ID_EXTINT0 = 48, |
| 175 | EXT_GIC_ID_EXTINT1, |
| 176 | EXT_GIC_ID_EXTINT2, |
| 177 | EXT_GIC_ID_EXTINT3, |
| 178 | EXT_GIC_ID_EXTINT4, |
| 179 | EXT_GIC_ID_EXTINT5, |
| 180 | EXT_GIC_ID_EXTINT6, |
| 181 | EXT_GIC_ID_EXTINT7, |
| 182 | EXT_GIC_ID_EXTINT8, |
| 183 | EXT_GIC_ID_EXTINT9, |
| 184 | EXT_GIC_ID_EXTINT10, |
| 185 | EXT_GIC_ID_EXTINT11, |
| 186 | EXT_GIC_ID_EXTINT12, |
| 187 | EXT_GIC_ID_EXTINT13, |
| 188 | EXT_GIC_ID_EXTINT14, |
| 189 | EXT_GIC_ID_EXTINT15 |
| 190 | }; |
| 191 | |
| 192 | /* |
| 193 | * External GIC sources which are not from External Interrupt Combiner or |
| 194 | * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ, |
| 195 | * which is INTG16 in Internal Interrupt Combiner. |
| 196 | */ |
| 197 | |
| 198 | static const uint32_t |
| 199 | combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { |
| 200 | /* int combiner groups 16-19 */ |
| 201 | { }, { }, { }, { }, |
| 202 | /* int combiner group 20 */ |
| 203 | { 0, EXT_GIC_ID_MDMA_LCD0 }, |
| 204 | /* int combiner group 21 */ |
| 205 | { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, |
| 206 | /* int combiner group 22 */ |
| 207 | { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, |
| 208 | EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, |
| 209 | /* int combiner group 23 */ |
| 210 | { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, |
| 211 | /* int combiner group 24 */ |
| 212 | { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, |
| 213 | /* int combiner group 25 */ |
| 214 | { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, |
| 215 | /* int combiner group 26 */ |
| 216 | { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3, |
| 217 | EXT_GIC_ID_UART4 }, |
| 218 | /* int combiner group 27 */ |
| 219 | { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, |
| 220 | EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, |
| 221 | EXT_GIC_ID_I2C7 }, |
| 222 | /* int combiner group 28 */ |
| 223 | { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST}, |
| 224 | /* int combiner group 29 */ |
| 225 | { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, |
| 226 | EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, |
| 227 | /* int combiner group 30 */ |
| 228 | { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, |
| 229 | /* int combiner group 31 */ |
| 230 | { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, |
| 231 | /* int combiner group 32 */ |
| 232 | { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, |
| 233 | /* int combiner group 33 */ |
| 234 | { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, |
| 235 | /* int combiner group 34 */ |
| 236 | { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, |
| 237 | /* int combiner group 35 */ |
| 238 | { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, |
| 239 | /* int combiner group 36 */ |
| 240 | { EXT_GIC_ID_MIXER }, |
| 241 | /* int combiner group 37 */ |
| 242 | { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, |
| 243 | EXT_GIC_ID_EXTINT7 }, |
| 244 | /* groups 38-50 */ |
| 245 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, |
| 246 | /* int combiner group 51 */ |
| 247 | { EXT_GIC_ID_MCT_L0 }, |
| 248 | /* group 52 */ |
| 249 | { }, |
| 250 | /* int combiner group 53 */ |
| 251 | { EXT_GIC_ID_WDT }, |
| 252 | /* groups 54-63 */ |
| 253 | { }, { }, { }, { }, { }, { }, { }, { }, { }, { } |
| 254 | }; |
| 255 | |
| 256 | #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) |
| 257 | #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) |
| 258 | #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ |
| 259 | ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) |
| 260 | |
| 261 | /* |
| 262 | * Some interrupt lines go to multiple combiner inputs. |
| 263 | * This data structure defines those: each array element is |
| 264 | * a list of combiner inputs which are connected together; |
| 265 | * the one with the smallest interrupt ID value must be first. |
| 266 | * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being |
| 267 | * wired to anything so we can use 0 as a terminator. |
| 268 | */ |
| 269 | #define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) |
| 270 | #define IRQNONE 0 |
| 271 | |
| 272 | #define COMBINERMAP_SIZE 16 |
| 273 | |
| 274 | static const int combinermap[COMBINERMAP_SIZE][6] = { |
| 275 | /* MDNIE_LCD1 */ |
| 276 | { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, |
| 277 | { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, |
| 278 | { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, |
| 279 | { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, |
| 280 | /* TMU */ |
| 281 | { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, |
| 282 | { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, |
| 283 | { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, |
| 284 | { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, |
| 285 | /* LCD1 */ |
| 286 | { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, |
| 287 | { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, |
| 288 | { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, |
| 289 | { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, |
| 290 | /* Multi-core timer */ |
| 291 | { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE }, |
| 292 | { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE }, |
| 293 | { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE }, |
| 294 | { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE }, |
| 295 | }; |
| 296 | |
| 297 | #undef IRQNO |
| 298 | |
| 299 | static const int *combinermap_entry(int irq) |
| 300 | { |
| 301 | /* |
| 302 | * If the interrupt number passed in is the first entry in some |
| 303 | * line of the combinermap, return a pointer to that line; |
| 304 | * otherwise return NULL. |
| 305 | */ |
| 306 | int i; |
| 307 | for (i = 0; i < COMBINERMAP_SIZE; i++) { |
| 308 | if (combinermap[i][0] == irq) { |
| 309 | return combinermap[i]; |
| 310 | } |
| 311 | } |
| 312 | return NULL; |
| 313 | } |
| 314 | |
| 315 | static int mapline_size(const int *mapline) |
| 316 | { |
| 317 | /* Return number of entries in this mapline in total */ |
| 318 | int i = 0; |
| 319 | |
| 320 | if (!mapline) { |
| 321 | /* Not in the map? IRQ goes to exactly one combiner input */ |
| 322 | return 1; |
| 323 | } |
| 324 | while (*mapline != IRQNONE) { |
| 325 | mapline++; |
| 326 | i++; |
| 327 | } |
| 328 | return i; |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * Initialize board IRQs. |
| 333 | * These IRQs contain split Int/External Combiner and External Gic IRQs. |
| 334 | */ |
| 335 | static void exynos4210_init_board_irqs(Exynos4210State *s) |
| 336 | { |
| 337 | uint32_t grp, bit, irq_id, n; |
| 338 | DeviceState *extgicdev = DEVICE(&s->ext_gic); |
| 339 | DeviceState *intcdev = DEVICE(&s->int_combiner); |
| 340 | DeviceState *extcdev = DEVICE(&s->ext_combiner); |
| 341 | int splitcount = 0; |
| 342 | DeviceState *splitter; |
| 343 | const int *mapline; |
| 344 | int numlines, splitin, in; |
| 345 | |
| 346 | for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { |
| 347 | irq_id = 0; |
| 348 | if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { |
| 349 | /* MCT_G0 is passed to External GIC */ |
| 350 | irq_id = EXT_GIC_ID_MCT_G0; |
| 351 | } |
| 352 | if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { |
| 353 | /* MCT_G1 is passed to External and GIC */ |
| 354 | irq_id = EXT_GIC_ID_MCT_G1; |
| 355 | } |
| 356 | |
| 357 | if (s->irq_table[n]) { |
| 358 | /* |
| 359 | * This must be some non-first entry in a combinermap line, |
| 360 | * and we've already filled it in. |
| 361 | */ |
| 362 | continue; |
| 363 | } |
| 364 | mapline = combinermap_entry(n); |
| 365 | /* |
| 366 | * We need to connect the IRQ to multiple inputs on both combiners |
| 367 | * and possibly also to the external GIC. |
| 368 | */ |
| 369 | numlines = 2 * mapline_size(mapline); |
| 370 | if (irq_id) { |
| 371 | numlines++; |
| 372 | } |
| 373 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
| 374 | splitter = DEVICE(&s->splitter[splitcount]); |
| 375 | qdev_prop_set_uint16(splitter, "num-lines", numlines); |
| 376 | qdev_realize(splitter, NULL, &error_abort); |
| 377 | splitcount++; |
| 378 | |
| 379 | in = n; |
| 380 | splitin = 0; |
| 381 | for (;;) { |
| 382 | s->irq_table[in] = qdev_get_gpio_in(splitter, 0); |
| 383 | qdev_connect_gpio_out(splitter, splitin, |
| 384 | qdev_get_gpio_in(intcdev, in)); |
| 385 | qdev_connect_gpio_out(splitter, splitin + 1, |
| 386 | qdev_get_gpio_in(extcdev, in)); |
| 387 | splitin += 2; |
| 388 | if (!mapline) { |
| 389 | break; |
| 390 | } |
| 391 | mapline++; |
| 392 | in = *mapline; |
| 393 | if (in == IRQNONE) { |
| 394 | break; |
| 395 | } |
| 396 | } |
| 397 | if (irq_id) { |
| 398 | qdev_connect_gpio_out(splitter, splitin, |
| 399 | qdev_get_gpio_in(extgicdev, |
| 400 | irq_id - GIC_INTERNAL)); |
| 401 | } |
| 402 | } |
| 403 | for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { |
| 404 | /* these IDs are passed to Internal Combiner and External GIC */ |
| 405 | grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n); |
| 406 | bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n); |
| 407 | irq_id = combiner_grp_to_gic_id[grp - |
| 408 | EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; |
| 409 | |
| 410 | if (s->irq_table[n]) { |
| 411 | /* |
| 412 | * This must be some non-first entry in a combinermap line, |
| 413 | * and we've already filled it in. |
| 414 | */ |
| 415 | continue; |
| 416 | } |
| 417 | |
| 418 | if (irq_id) { |
| 419 | assert(splitcount < EXYNOS4210_NUM_SPLITTERS); |
| 420 | splitter = DEVICE(&s->splitter[splitcount]); |
| 421 | qdev_prop_set_uint16(splitter, "num-lines", 2); |
| 422 | qdev_realize(splitter, NULL, &error_abort); |
| 423 | splitcount++; |
| 424 | s->irq_table[n] = qdev_get_gpio_in(splitter, 0); |
| 425 | qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n)); |
| 426 | qdev_connect_gpio_out(splitter, 1, |
| 427 | qdev_get_gpio_in(extgicdev, |
| 428 | irq_id - GIC_INTERNAL)); |
| 429 | } else { |
| 430 | s->irq_table[n] = qdev_get_gpio_in(intcdev, n); |
| 431 | } |
| 432 | } |
| 433 | /* |
| 434 | * We check this here to avoid a more obscure assert later when |
| 435 | * qdev_assert_realized_properly() checks that we realized every |
| 436 | * child object we initialized. |
| 437 | */ |
| 438 | assert(splitcount == EXYNOS4210_NUM_SPLITTERS); |
| 439 | } |
| 440 | |
| 441 | /* |
| 442 | * Get IRQ number from exynos4210 IRQ subsystem stub. |
| 443 | * To identify IRQ source use internal combiner group and bit number |
| 444 | * grp - group number |
| 445 | * bit - bit number inside group |
| 446 | */ |
| 447 | uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) |
| 448 | { |
| 449 | return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); |
| 450 | } |
| 451 | |
| 452 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
| 453 | 0x09, 0x00, 0x00, 0x00 }; |
| 454 | |
| 455 | static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset, |
| 456 | unsigned size) |
| 457 | { |
| 458 | assert(offset < sizeof(chipid_and_omr)); |
| 459 | return chipid_and_omr[offset]; |
| 460 | } |
| 461 | |
| 462 | static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset, |
| 463 | uint64_t value, unsigned size) |
| 464 | { |
| 465 | } |
| 466 | |
| 467 | static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { |
| 468 | .read = exynos4210_chipid_and_omr_read, |
| 469 | .write = exynos4210_chipid_and_omr_write, |
| 470 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 471 | .impl = { |
| 472 | .max_access_size = 1, |
| 473 | } |
| 474 | }; |
| 475 | |
| 476 | void exynos4210_write_secondary(ARMCPU *cpu, |
| 477 | const struct arm_boot_info *info) |
| 478 | { |
| 479 | int n; |
| 480 | uint32_t smpboot[] = { |
| 481 | 0xe59f3034, /* ldr r3, External gic_cpu_if */ |
| 482 | 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ |
| 483 | 0xe59f0034, /* ldr r0, startaddr */ |
| 484 | 0xe3a01001, /* mov r1, #1 */ |
| 485 | 0xe5821000, /* str r1, [r2] */ |
| 486 | 0xe5831000, /* str r1, [r3] */ |
| 487 | 0xe3a010ff, /* mov r1, #0xff */ |
| 488 | 0xe5821004, /* str r1, [r2, #4] */ |
| 489 | 0xe5831004, /* str r1, [r3, #4] */ |
| 490 | 0xf57ff04f, /* dsb */ |
| 491 | 0xe320f003, /* wfi */ |
| 492 | 0xe5901000, /* ldr r1, [r0] */ |
| 493 | 0xe1110001, /* tst r1, r1 */ |
| 494 | 0x0afffffb, /* beq <wfi> */ |
| 495 | 0xe12fff11, /* bx r1 */ |
| 496 | EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, |
| 497 | 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ |
| 498 | 0 /* bootreg: Boot register address is held here */ |
| 499 | }; |
| 500 | smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; |
| 501 | smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; |
| 502 | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
| 503 | smpboot[n] = tswap32(smpboot[n]); |
| 504 | } |
| 505 | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), |
| 506 | info->smp_loader_start); |
| 507 | } |
| 508 | |
| 509 | static uint64_t exynos4210_calc_affinity(int cpu) |
| 510 | { |
| 511 | /* Exynos4210 has 0x9 as cluster ID */ |
| 512 | return (0x9 << ARM_AFF1_SHIFT) | cpu; |
| 513 | } |
| 514 | |
| 515 | static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, |
| 516 | qemu_irq irq, int nreq, int nevents, int width) |
| 517 | { |
| 518 | SysBusDevice *busdev; |
| 519 | DeviceState *dev; |
| 520 | int i; |
| 521 | |
| 522 | dev = qdev_new("pl330"); |
| 523 | object_property_set_link(OBJECT(dev), "memory", |
| 524 | OBJECT(get_system_memory()), |
| 525 | &error_fatal); |
| 526 | qdev_prop_set_uint8(dev, "num_events", nevents); |
| 527 | qdev_prop_set_uint8(dev, "num_chnls", 8); |
| 528 | qdev_prop_set_uint8(dev, "num_periph_req", nreq); |
| 529 | |
| 530 | qdev_prop_set_uint8(dev, "wr_cap", 4); |
| 531 | qdev_prop_set_uint8(dev, "wr_q_dep", 8); |
| 532 | qdev_prop_set_uint8(dev, "rd_cap", 4); |
| 533 | qdev_prop_set_uint8(dev, "rd_q_dep", 8); |
| 534 | qdev_prop_set_uint8(dev, "data_width", width); |
| 535 | qdev_prop_set_uint16(dev, "data_buffer_dep", width); |
| 536 | busdev = SYS_BUS_DEVICE(dev); |
| 537 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 538 | sysbus_mmio_map(busdev, 0, base); |
| 539 | |
| 540 | object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, |
| 541 | &error_abort); |
| 542 | qdev_realize(DEVICE(orgate), NULL, &error_abort); |
| 543 | |
| 544 | for (i = 0; i < nevents + 1; i++) { |
| 545 | sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i)); |
| 546 | } |
| 547 | qdev_connect_gpio_out(DEVICE(orgate), 0, irq); |
| 548 | return dev; |
| 549 | } |
| 550 | |
| 551 | static void exynos4210_realize(DeviceState *socdev, Error **errp) |
| 552 | { |
| 553 | Exynos4210State *s = EXYNOS4210_SOC(socdev); |
| 554 | MemoryRegion *system_mem = get_system_memory(); |
| 555 | SysBusDevice *busdev; |
| 556 | DeviceState *dev, *uart[4], *pl330[3]; |
| 557 | int i, n; |
| 558 | |
| 559 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
| 560 | Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); |
| 561 | |
| 562 | object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); |
| 563 | /* By default A9 CPUs have EL3 enabled. This board does not currently |
| 564 | * support EL3 so the CPU EL3 property is disabled before realization. |
| 565 | */ |
| 566 | if (object_property_find(cpuobj, "has_el3")) { |
| 567 | object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); |
| 568 | } |
| 569 | |
| 570 | s->cpu[n] = ARM_CPU(cpuobj); |
| 571 | object_property_set_int(cpuobj, "mp-affinity", |
| 572 | exynos4210_calc_affinity(n), &error_abort); |
| 573 | object_property_set_int(cpuobj, "reset-cbar", |
| 574 | EXYNOS4210_SMP_PRIVATE_BASE_ADDR, |
| 575 | &error_abort); |
| 576 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 577 | } |
| 578 | |
| 579 | /* IRQ Gate */ |
| 580 | for (i = 0; i < EXYNOS4210_NCPUS; i++) { |
| 581 | DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); |
| 582 | object_property_set_int(OBJECT(orgate), "num-lines", |
| 583 | EXYNOS4210_IRQ_GATE_NINPUTS, |
| 584 | &error_abort); |
| 585 | qdev_realize(orgate, NULL, &error_abort); |
| 586 | qdev_connect_gpio_out(orgate, 0, |
| 587 | qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); |
| 588 | } |
| 589 | |
| 590 | /* Private memory region and Internal GIC */ |
| 591 | qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS); |
| 592 | qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq", |
| 593 | GIC_EXT_IRQS + GIC_INTERNAL); |
| 594 | busdev = SYS_BUS_DEVICE(&s->a9mpcore); |
| 595 | sysbus_realize(busdev, &error_fatal); |
| 596 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); |
| 597 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
| 598 | sysbus_connect_irq(busdev, n, |
| 599 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); |
| 600 | } |
| 601 | |
| 602 | /* Cache controller */ |
| 603 | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); |
| 604 | |
| 605 | /* External GIC */ |
| 606 | qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); |
| 607 | busdev = SYS_BUS_DEVICE(&s->ext_gic); |
| 608 | sysbus_realize(busdev, &error_fatal); |
| 609 | /* Map CPU interface */ |
| 610 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); |
| 611 | /* Map Distributer interface */ |
| 612 | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); |
| 613 | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
| 614 | sysbus_connect_irq(busdev, n, |
| 615 | qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1)); |
| 616 | } |
| 617 | |
| 618 | /* Internal Interrupt Combiner */ |
| 619 | busdev = SYS_BUS_DEVICE(&s->int_combiner); |
| 620 | sysbus_realize(busdev, &error_fatal); |
| 621 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
| 622 | sysbus_connect_irq(busdev, n, |
| 623 | qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); |
| 624 | } |
| 625 | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); |
| 626 | |
| 627 | /* External Interrupt Combiner */ |
| 628 | qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); |
| 629 | busdev = SYS_BUS_DEVICE(&s->ext_combiner); |
| 630 | sysbus_realize(busdev, &error_fatal); |
| 631 | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
| 632 | sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n)); |
| 633 | } |
| 634 | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); |
| 635 | |
| 636 | /* Initialize board IRQs. */ |
| 637 | exynos4210_init_board_irqs(s); |
| 638 | |
| 639 | /*** Memory ***/ |
| 640 | |
| 641 | /* Chip-ID and OMR */ |
| 642 | memory_region_init_io(&s->chipid_mem, OBJECT(socdev), |
| 643 | &exynos4210_chipid_and_omr_ops, NULL, |
| 644 | "exynos4210.chipid", sizeof(chipid_and_omr)); |
| 645 | memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, |
| 646 | &s->chipid_mem); |
| 647 | |
| 648 | /* Internal ROM */ |
| 649 | memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom", |
| 650 | EXYNOS4210_IROM_SIZE, &error_fatal); |
| 651 | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, |
| 652 | &s->irom_mem); |
| 653 | /* mirror of iROM */ |
| 654 | memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev), |
| 655 | "exynos4210.irom_alias", &s->irom_mem, 0, |
| 656 | EXYNOS4210_IROM_SIZE); |
| 657 | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, |
| 658 | &s->irom_alias_mem); |
| 659 | |
| 660 | /* Internal RAM */ |
| 661 | memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", |
| 662 | EXYNOS4210_IRAM_SIZE, &error_fatal); |
| 663 | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, |
| 664 | &s->iram_mem); |
| 665 | |
| 666 | /* PMU. |
| 667 | * The only reason of existence at the moment is that secondary CPU boot |
| 668 | * loader uses PMU INFORM5 register as a holding pen. |
| 669 | */ |
| 670 | sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); |
| 671 | |
| 672 | sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL); |
| 673 | sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL); |
| 674 | |
| 675 | /* PWM */ |
| 676 | sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, |
| 677 | s->irq_table[exynos4210_get_irq(22, 0)], |
| 678 | s->irq_table[exynos4210_get_irq(22, 1)], |
| 679 | s->irq_table[exynos4210_get_irq(22, 2)], |
| 680 | s->irq_table[exynos4210_get_irq(22, 3)], |
| 681 | s->irq_table[exynos4210_get_irq(22, 4)], |
| 682 | NULL); |
| 683 | /* RTC */ |
| 684 | sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR, |
| 685 | s->irq_table[exynos4210_get_irq(23, 0)], |
| 686 | s->irq_table[exynos4210_get_irq(23, 1)], |
| 687 | NULL); |
| 688 | |
| 689 | /* Multi Core Timer */ |
| 690 | dev = qdev_new("exynos4210.mct"); |
| 691 | busdev = SYS_BUS_DEVICE(dev); |
| 692 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 693 | for (n = 0; n < 4; n++) { |
| 694 | /* Connect global timer interrupts to Combiner gpio_in */ |
| 695 | sysbus_connect_irq(busdev, n, |
| 696 | s->irq_table[exynos4210_get_irq(1, 4 + n)]); |
| 697 | } |
| 698 | /* Connect local timer interrupts to Combiner gpio_in */ |
| 699 | sysbus_connect_irq(busdev, 4, |
| 700 | s->irq_table[exynos4210_get_irq(51, 0)]); |
| 701 | sysbus_connect_irq(busdev, 5, |
| 702 | s->irq_table[exynos4210_get_irq(35, 3)]); |
| 703 | sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR); |
| 704 | |
| 705 | /*** I2C ***/ |
| 706 | for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { |
| 707 | uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; |
| 708 | qemu_irq i2c_irq; |
| 709 | |
| 710 | if (n < 8) { |
| 711 | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; |
| 712 | } else { |
| 713 | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; |
| 714 | } |
| 715 | |
| 716 | dev = qdev_new("exynos4210.i2c"); |
| 717 | busdev = SYS_BUS_DEVICE(dev); |
| 718 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 719 | sysbus_connect_irq(busdev, 0, i2c_irq); |
| 720 | sysbus_mmio_map(busdev, 0, addr); |
| 721 | s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
| 722 | } |
| 723 | |
| 724 | |
| 725 | /*** UARTs ***/ |
| 726 | uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, |
| 727 | EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0), |
| 728 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); |
| 729 | |
| 730 | uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, |
| 731 | EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1), |
| 732 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); |
| 733 | |
| 734 | uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, |
| 735 | EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2), |
| 736 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); |
| 737 | |
| 738 | uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, |
| 739 | EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3), |
| 740 | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); |
| 741 | |
| 742 | /*** SD/MMC host controllers ***/ |
| 743 | for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { |
| 744 | DeviceState *carddev; |
| 745 | BlockBackend *blk; |
| 746 | DriveInfo *di; |
| 747 | |
| 748 | /* Compatible with: |
| 749 | * - SD Host Controller Specification Version 2.0 |
| 750 | * - SDIO Specification Version 2.0 |
| 751 | * - MMC Specification Version 4.3 |
| 752 | * - SDMA |
| 753 | * - ADMA2 |
| 754 | * |
| 755 | * As this part of the Exynos4210 is not publicly available, |
| 756 | * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" |
| 757 | * public datasheet which is very similar (implementing |
| 758 | * MMC Specification Version 4.0 being the only difference noted) |
| 759 | */ |
| 760 | dev = qdev_new(TYPE_S3C_SDHCI); |
| 761 | qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); |
| 762 | |
| 763 | busdev = SYS_BUS_DEVICE(dev); |
| 764 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 765 | sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); |
| 766 | sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); |
| 767 | |
| 768 | di = drive_get(IF_SD, 0, n); |
| 769 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
| 770 | carddev = qdev_new(TYPE_SD_CARD); |
| 771 | qdev_prop_set_drive(carddev, "drive", blk); |
| 772 | qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), |
| 773 | &error_fatal); |
| 774 | } |
| 775 | |
| 776 | /*** Display controller (FIMD) ***/ |
| 777 | dev = qdev_new("exynos4210.fimd"); |
| 778 | object_property_set_link(OBJECT(dev), "framebuffer-memory", |
| 779 | OBJECT(system_mem), &error_fatal); |
| 780 | busdev = SYS_BUS_DEVICE(dev); |
| 781 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 782 | sysbus_mmio_map(busdev, 0, EXYNOS4210_FIMD0_BASE_ADDR); |
| 783 | for (n = 0; n < 3; n++) { |
| 784 | sysbus_connect_irq(busdev, n, s->irq_table[exynos4210_get_irq(11, n)]); |
| 785 | } |
| 786 | |
| 787 | sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, |
| 788 | s->irq_table[exynos4210_get_irq(28, 3)]); |
| 789 | |
| 790 | /*** DMA controllers ***/ |
| 791 | pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR, |
| 792 | &s->pl330_irq_orgate[0], |
| 793 | s->irq_table[exynos4210_get_irq(21, 0)], |
| 794 | 32, 32, 32); |
| 795 | pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR, |
| 796 | &s->pl330_irq_orgate[1], |
| 797 | s->irq_table[exynos4210_get_irq(21, 1)], |
| 798 | 32, 32, 32); |
| 799 | pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR, |
| 800 | &s->pl330_irq_orgate[2], |
| 801 | s->irq_table[exynos4210_get_irq(20, 1)], |
| 802 | 1, 31, 64); |
| 803 | |
| 804 | sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1, |
| 805 | qdev_get_gpio_in(pl330[0], 15)); |
| 806 | sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1, |
| 807 | qdev_get_gpio_in(pl330[1], 15)); |
| 808 | sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1, |
| 809 | qdev_get_gpio_in(pl330[0], 17)); |
| 810 | sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1, |
| 811 | qdev_get_gpio_in(pl330[1], 17)); |
| 812 | } |
| 813 | |
| 814 | static void exynos4210_init(Object *obj) |
| 815 | { |
| 816 | Exynos4210State *s = EXYNOS4210_SOC(obj); |
| 817 | int i; |
| 818 | |
| 819 | for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { |
| 820 | char *name = g_strdup_printf("pl330-irq-orgate%d", i); |
| 821 | OrIRQState *orgate = &s->pl330_irq_orgate[i]; |
| 822 | |
| 823 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); |
| 824 | g_free(name); |
| 825 | } |
| 826 | |
| 827 | for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { |
| 828 | g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); |
| 829 | object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); |
| 830 | } |
| 831 | |
| 832 | for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { |
| 833 | g_autofree char *name = g_strdup_printf("irq-splitter%d", i); |
| 834 | object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ); |
| 835 | } |
| 836 | |
| 837 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); |
| 838 | object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC); |
| 839 | object_initialize_child(obj, "int-combiner", &s->int_combiner, |
| 840 | TYPE_EXYNOS4210_COMBINER); |
| 841 | object_initialize_child(obj, "ext-combiner", &s->ext_combiner, |
| 842 | TYPE_EXYNOS4210_COMBINER); |
| 843 | } |
| 844 | |
| 845 | static void exynos4210_class_init(ObjectClass *klass, const void *data) |
| 846 | { |
| 847 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 848 | |
| 849 | dc->realize = exynos4210_realize; |
| 850 | } |
| 851 | |
| 852 | static const TypeInfo exynos4210_info = { |
| 853 | .name = TYPE_EXYNOS4210_SOC, |
| 854 | .parent = TYPE_SYS_BUS_DEVICE, |
| 855 | .instance_size = sizeof(Exynos4210State), |
| 856 | .instance_init = exynos4210_init, |
| 857 | .class_init = exynos4210_class_init, |
| 858 | }; |
| 859 | |
| 860 | static void exynos4210_register_types(void) |
| 861 | { |
| 862 | type_register_static(&exynos4210_info); |
| 863 | } |
| 864 | |
| 865 | type_init(exynos4210_register_types) |