| 1 | /* |
| 2 | * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> |
| 3 | * |
| 4 | * i.MX25 SOC emulation. |
| 5 | * |
| 6 | * Based on hw/arm/xlnx-zynqmp.c |
| 7 | * |
| 8 | * Copyright (C) 2015 Xilinx Inc |
| 9 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 19 | * for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License along |
| 22 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qapi/error.h" |
| 27 | #include "hw/arm/fsl-imx25.h" |
| 28 | #include "system/system.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "chardev/char.h" |
| 31 | #include "target/arm/cpu-qom.h" |
| 32 | |
| 33 | #define IMX25_ESDHC_CAPABILITIES 0x07e20000 |
| 34 | |
| 35 | static void fsl_imx25_init(Object *obj) |
| 36 | { |
| 37 | FslIMX25State *s = FSL_IMX25(obj); |
| 38 | int i; |
| 39 | |
| 40 | object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926")); |
| 41 | |
| 42 | object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC); |
| 43 | |
| 44 | object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM); |
| 45 | |
| 46 | for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { |
| 47 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL); |
| 48 | } |
| 49 | |
| 50 | for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { |
| 51 | object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT); |
| 52 | } |
| 53 | |
| 54 | for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { |
| 55 | object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT); |
| 56 | } |
| 57 | |
| 58 | object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC); |
| 59 | |
| 60 | object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC); |
| 61 | |
| 62 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { |
| 63 | object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C); |
| 64 | } |
| 65 | |
| 66 | for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { |
| 67 | object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO); |
| 68 | } |
| 69 | |
| 70 | for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { |
| 71 | object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], |
| 72 | TYPE_FSL_ESDHC_LE); |
| 73 | } |
| 74 | |
| 75 | for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { |
| 76 | object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA); |
| 77 | } |
| 78 | |
| 79 | object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT); |
| 80 | } |
| 81 | |
| 82 | static void fsl_imx25_realize(DeviceState *dev, Error **errp) |
| 83 | { |
| 84 | FslIMX25State *s = FSL_IMX25(dev); |
| 85 | uint8_t i; |
| 86 | |
| 87 | if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { |
| 88 | return; |
| 89 | } |
| 90 | |
| 91 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->avic), errp)) { |
| 92 | return; |
| 93 | } |
| 94 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); |
| 95 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, |
| 96 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); |
| 97 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, |
| 98 | qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); |
| 99 | |
| 100 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { |
| 101 | return; |
| 102 | } |
| 103 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); |
| 104 | |
| 105 | /* Initialize all UARTs */ |
| 106 | for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { |
| 107 | static const struct { |
| 108 | hwaddr addr; |
| 109 | unsigned int irq; |
| 110 | } serial_table[FSL_IMX25_NUM_UARTS] = { |
| 111 | { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, |
| 112 | { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, |
| 113 | { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, |
| 114 | { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, |
| 115 | { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } |
| 116 | }; |
| 117 | |
| 118 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
| 119 | |
| 120 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { |
| 121 | return; |
| 122 | } |
| 123 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); |
| 124 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 125 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 126 | serial_table[i].irq)); |
| 127 | } |
| 128 | |
| 129 | /* Initialize all GPT timers */ |
| 130 | for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { |
| 131 | static const struct { |
| 132 | hwaddr addr; |
| 133 | unsigned int irq; |
| 134 | } gpt_table[FSL_IMX25_NUM_GPTS] = { |
| 135 | { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, |
| 136 | { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, |
| 137 | { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, |
| 138 | { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } |
| 139 | }; |
| 140 | |
| 141 | s->gpt[i].ccm = IMX_CCM(&s->ccm); |
| 142 | |
| 143 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) { |
| 144 | return; |
| 145 | } |
| 146 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); |
| 147 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, |
| 148 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 149 | gpt_table[i].irq)); |
| 150 | } |
| 151 | |
| 152 | /* Initialize all EPIT timers */ |
| 153 | for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { |
| 154 | static const struct { |
| 155 | hwaddr addr; |
| 156 | unsigned int irq; |
| 157 | } epit_table[FSL_IMX25_NUM_EPITS] = { |
| 158 | { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, |
| 159 | { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } |
| 160 | }; |
| 161 | |
| 162 | s->epit[i].ccm = IMX_CCM(&s->ccm); |
| 163 | |
| 164 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { |
| 165 | return; |
| 166 | } |
| 167 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); |
| 168 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, |
| 169 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 170 | epit_table[i].irq)); |
| 171 | } |
| 172 | |
| 173 | object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, |
| 174 | &error_abort); |
| 175 | qemu_configure_nic_device(DEVICE(&s->fec), true, NULL); |
| 176 | |
| 177 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) { |
| 178 | return; |
| 179 | } |
| 180 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); |
| 181 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, |
| 182 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); |
| 183 | |
| 184 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rngc), errp)) { |
| 185 | return; |
| 186 | } |
| 187 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR); |
| 188 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0, |
| 189 | qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ)); |
| 190 | |
| 191 | /* Initialize all I2C */ |
| 192 | for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { |
| 193 | static const struct { |
| 194 | hwaddr addr; |
| 195 | unsigned int irq; |
| 196 | } i2c_table[FSL_IMX25_NUM_I2CS] = { |
| 197 | { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, |
| 198 | { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, |
| 199 | { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } |
| 200 | }; |
| 201 | |
| 202 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { |
| 203 | return; |
| 204 | } |
| 205 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); |
| 206 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, |
| 207 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 208 | i2c_table[i].irq)); |
| 209 | } |
| 210 | |
| 211 | /* Initialize all GPIOs */ |
| 212 | for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { |
| 213 | static const struct { |
| 214 | hwaddr addr; |
| 215 | unsigned int irq; |
| 216 | } gpio_table[FSL_IMX25_NUM_GPIOS] = { |
| 217 | { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, |
| 218 | { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, |
| 219 | { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, |
| 220 | { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } |
| 221 | }; |
| 222 | |
| 223 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { |
| 224 | return; |
| 225 | } |
| 226 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); |
| 227 | /* Connect GPIO IRQ to PIC */ |
| 228 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 229 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 230 | gpio_table[i].irq)); |
| 231 | } |
| 232 | |
| 233 | /* Initialize all SDHC */ |
| 234 | for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { |
| 235 | static const struct { |
| 236 | hwaddr addr; |
| 237 | unsigned int irq; |
| 238 | } esdhc_table[FSL_IMX25_NUM_ESDHCS] = { |
| 239 | { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ }, |
| 240 | { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, |
| 241 | }; |
| 242 | |
| 243 | object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", |
| 244 | IMX25_ESDHC_CAPABILITIES, &error_abort); |
| 245 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { |
| 246 | return; |
| 247 | } |
| 248 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); |
| 249 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, |
| 250 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 251 | esdhc_table[i].irq)); |
| 252 | } |
| 253 | |
| 254 | /* USB */ |
| 255 | for (i = 0; i < FSL_IMX25_NUM_USBS; i++) { |
| 256 | static const struct { |
| 257 | hwaddr addr; |
| 258 | unsigned int irq; |
| 259 | } usb_table[FSL_IMX25_NUM_USBS] = { |
| 260 | { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ }, |
| 261 | { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ }, |
| 262 | }; |
| 263 | |
| 264 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); |
| 265 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); |
| 266 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 267 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 268 | usb_table[i].irq)); |
| 269 | } |
| 270 | |
| 271 | /* Watchdog */ |
| 272 | object_property_set_bool(OBJECT(&s->wdt), "pretimeout-support", true, |
| 273 | &error_abort); |
| 274 | sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); |
| 275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); |
| 276 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, |
| 277 | qdev_get_gpio_in(DEVICE(&s->avic), |
| 278 | FSL_IMX25_WDT_IRQ)); |
| 279 | |
| 280 | /* initialize 2 x 16 KB ROM */ |
| 281 | if (!memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0", |
| 282 | FSL_IMX25_ROM0_SIZE, errp)) { |
| 283 | return; |
| 284 | } |
| 285 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, |
| 286 | &s->rom[0]); |
| 287 | if (!memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1", |
| 288 | FSL_IMX25_ROM1_SIZE, errp)) { |
| 289 | return; |
| 290 | } |
| 291 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, |
| 292 | &s->rom[1]); |
| 293 | |
| 294 | /* initialize internal RAM (128 KB) */ |
| 295 | if (!memory_region_init_ram(&s->iram, NULL, "imx25.iram", |
| 296 | FSL_IMX25_IRAM_SIZE, errp)) { |
| 297 | return; |
| 298 | } |
| 299 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, |
| 300 | &s->iram); |
| 301 | |
| 302 | /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ |
| 303 | memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias", |
| 304 | &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); |
| 305 | memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, |
| 306 | &s->iram_alias); |
| 307 | } |
| 308 | |
| 309 | static const Property fsl_imx25_properties[] = { |
| 310 | DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0), |
| 311 | }; |
| 312 | |
| 313 | static void fsl_imx25_class_init(ObjectClass *oc, const void *data) |
| 314 | { |
| 315 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 316 | |
| 317 | device_class_set_props(dc, fsl_imx25_properties); |
| 318 | dc->realize = fsl_imx25_realize; |
| 319 | dc->desc = "i.MX25 SOC"; |
| 320 | /* |
| 321 | * Reason: uses serial_hds in realize and the imx25 board does not |
| 322 | * support multiple CPUs |
| 323 | */ |
| 324 | dc->user_creatable = false; |
| 325 | } |
| 326 | |
| 327 | static const TypeInfo fsl_imx25_type_info = { |
| 328 | .name = TYPE_FSL_IMX25, |
| 329 | .parent = TYPE_DEVICE, |
| 330 | .instance_size = sizeof(FslIMX25State), |
| 331 | .instance_init = fsl_imx25_init, |
| 332 | .class_init = fsl_imx25_class_init, |
| 333 | }; |
| 334 | |
| 335 | static void fsl_imx25_register_types(void) |
| 336 | { |
| 337 | type_register_static(&fsl_imx25_type_info); |
| 338 | } |
| 339 | |
| 340 | type_init(fsl_imx25_register_types) |