| 1 | /* |
| 2 | * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> |
| 3 | * |
| 4 | * i.MX6 SOC emulation. |
| 5 | * |
| 6 | * Based on hw/arm/fsl-imx31.c |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along |
| 19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #include "qemu/osdep.h" |
| 23 | #include "qapi/error.h" |
| 24 | #include "hw/arm/fsl-imx6.h" |
| 25 | #include "hw/misc/unimp.h" |
| 26 | #include "hw/usb/imx-usb-phy.h" |
| 27 | #include "hw/core/boards.h" |
| 28 | #include "hw/core/qdev-properties.h" |
| 29 | #include "system/system.h" |
| 30 | #include "chardev/char.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "qemu/module.h" |
| 33 | #include "target/arm/cpu-qom.h" |
| 34 | |
| 35 | #define IMX6_ESDHC_CAPABILITIES 0x057834b4 |
| 36 | |
| 37 | #define NAME_SIZE 20 |
| 38 | |
| 39 | static void fsl_imx6_init(Object *obj) |
| 40 | { |
| 41 | FslIMX6State *s = FSL_IMX6(obj); |
| 42 | char name[NAME_SIZE]; |
| 43 | int i; |
| 44 | |
| 45 | object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); |
| 46 | |
| 47 | object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); |
| 48 | |
| 49 | object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); |
| 50 | |
| 51 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); |
| 52 | |
| 53 | for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { |
| 54 | snprintf(name, NAME_SIZE, "uart%d", i + 1); |
| 55 | object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); |
| 56 | } |
| 57 | |
| 58 | object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT); |
| 59 | |
| 60 | for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { |
| 61 | snprintf(name, NAME_SIZE, "epit%d", i + 1); |
| 62 | object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); |
| 63 | } |
| 64 | |
| 65 | for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { |
| 66 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
| 67 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); |
| 68 | } |
| 69 | |
| 70 | for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { |
| 71 | snprintf(name, NAME_SIZE, "gpio%d", i + 1); |
| 72 | object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); |
| 73 | } |
| 74 | |
| 75 | for (i = 0; i < FSL_IMX6_NUM_USDHCS; i++) { |
| 76 | snprintf(name, NAME_SIZE, "sdhc%d", i + 1); |
| 77 | object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); |
| 78 | } |
| 79 | |
| 80 | for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { |
| 81 | snprintf(name, NAME_SIZE, "usbphy%d", i); |
| 82 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); |
| 83 | } |
| 84 | for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { |
| 85 | snprintf(name, NAME_SIZE, "usb%d", i); |
| 86 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); |
| 87 | } |
| 88 | |
| 89 | for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { |
| 90 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
| 91 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); |
| 92 | } |
| 93 | for (i = 0; i < FSL_IMX6_NUM_CANS; i++) { |
| 94 | snprintf(name, NAME_SIZE, "flexcan%d", i + 1); |
| 95 | object_initialize_child(obj, name, &s->flexcan[i], TYPE_CAN_FLEXCAN2); |
| 96 | } |
| 97 | for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { |
| 98 | snprintf(name, NAME_SIZE, "wdt%d", i); |
| 99 | object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); |
| 100 | } |
| 101 | |
| 102 | |
| 103 | object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); |
| 104 | |
| 105 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); |
| 106 | object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq, |
| 107 | TYPE_OR_IRQ); |
| 108 | } |
| 109 | |
| 110 | static void fsl_imx6_realize(DeviceState *dev, Error **errp) |
| 111 | { |
| 112 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 113 | FslIMX6State *s = FSL_IMX6(dev); |
| 114 | uint16_t i; |
| 115 | qemu_irq irq; |
| 116 | unsigned int smp_cpus = ms->smp.cpus; |
| 117 | DeviceState *mpcore = DEVICE(&s->a9mpcore); |
| 118 | DeviceState *gic; |
| 119 | char name[NAME_SIZE]; |
| 120 | |
| 121 | if (smp_cpus > FSL_IMX6_NUM_CPUS) { |
| 122 | error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", |
| 123 | TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | for (i = 0; i < smp_cpus; i++) { |
| 128 | snprintf(name, NAME_SIZE, "cpu%d", i); |
| 129 | object_initialize_child(OBJECT(dev), name, &s->cpu[i], |
| 130 | ARM_CPU_TYPE_NAME("cortex-a9")); |
| 131 | } |
| 132 | |
| 133 | for (i = 0; i < smp_cpus; i++) { |
| 134 | |
| 135 | /* On uniprocessor, the CBAR is set to 0 */ |
| 136 | if (smp_cpus > 1) { |
| 137 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
| 138 | FSL_IMX6_A9MPCORE_ADDR, &error_abort); |
| 139 | } |
| 140 | |
| 141 | /* All CPU but CPU 0 start in power off mode */ |
| 142 | if (i) { |
| 143 | object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", |
| 144 | true, &error_abort); |
| 145 | } |
| 146 | |
| 147 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
| 148 | return; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); |
| 153 | |
| 154 | object_property_set_int(OBJECT(mpcore), "num-irq", |
| 155 | FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); |
| 156 | |
| 157 | if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) { |
| 158 | return; |
| 159 | } |
| 160 | sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); |
| 161 | |
| 162 | gic = mpcore; |
| 163 | for (i = 0; i < smp_cpus; i++) { |
| 164 | sysbus_connect_irq(SYS_BUS_DEVICE(gic), i, |
| 165 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); |
| 166 | sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus, |
| 167 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); |
| 168 | } |
| 169 | |
| 170 | /* L2 cache controller */ |
| 171 | sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL); |
| 172 | |
| 173 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { |
| 174 | return; |
| 175 | } |
| 176 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); |
| 177 | |
| 178 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), errp)) { |
| 179 | return; |
| 180 | } |
| 181 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); |
| 182 | |
| 183 | /* Initialize all UARTs */ |
| 184 | for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { |
| 185 | static const struct { |
| 186 | hwaddr addr; |
| 187 | unsigned int irq; |
| 188 | } serial_table[FSL_IMX6_NUM_UARTS] = { |
| 189 | { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, |
| 190 | { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, |
| 191 | { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, |
| 192 | { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, |
| 193 | { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, |
| 194 | }; |
| 195 | |
| 196 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
| 197 | |
| 198 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); |
| 203 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 204 | qdev_get_gpio_in(gic, serial_table[i].irq)); |
| 205 | } |
| 206 | |
| 207 | s->gpt.ccm = IMX_CCM(&s->ccm); |
| 208 | |
| 209 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { |
| 210 | return; |
| 211 | } |
| 212 | |
| 213 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); |
| 214 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, |
| 215 | qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ)); |
| 216 | |
| 217 | /* Initialize all EPIT timers */ |
| 218 | for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { |
| 219 | static const struct { |
| 220 | hwaddr addr; |
| 221 | unsigned int irq; |
| 222 | } epit_table[FSL_IMX6_NUM_EPITS] = { |
| 223 | { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, |
| 224 | { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, |
| 225 | }; |
| 226 | |
| 227 | s->epit[i].ccm = IMX_CCM(&s->ccm); |
| 228 | |
| 229 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), errp)) { |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); |
| 234 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, |
| 235 | qdev_get_gpio_in(gic, epit_table[i].irq)); |
| 236 | } |
| 237 | |
| 238 | /* Initialize all I2C */ |
| 239 | for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { |
| 240 | static const struct { |
| 241 | hwaddr addr; |
| 242 | unsigned int irq; |
| 243 | } i2c_table[FSL_IMX6_NUM_I2CS] = { |
| 244 | { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, |
| 245 | { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, |
| 246 | { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } |
| 247 | }; |
| 248 | |
| 249 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); |
| 254 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, |
| 255 | qdev_get_gpio_in(gic, i2c_table[i].irq)); |
| 256 | } |
| 257 | |
| 258 | /* Initialize all GPIOs */ |
| 259 | for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { |
| 260 | static const struct { |
| 261 | hwaddr addr; |
| 262 | unsigned int irq_low; |
| 263 | unsigned int irq_high; |
| 264 | } gpio_table[FSL_IMX6_NUM_GPIOS] = { |
| 265 | { |
| 266 | FSL_IMX6_GPIO1_ADDR, |
| 267 | FSL_IMX6_GPIO1_LOW_IRQ, |
| 268 | FSL_IMX6_GPIO1_HIGH_IRQ |
| 269 | }, |
| 270 | { |
| 271 | FSL_IMX6_GPIO2_ADDR, |
| 272 | FSL_IMX6_GPIO2_LOW_IRQ, |
| 273 | FSL_IMX6_GPIO2_HIGH_IRQ |
| 274 | }, |
| 275 | { |
| 276 | FSL_IMX6_GPIO3_ADDR, |
| 277 | FSL_IMX6_GPIO3_LOW_IRQ, |
| 278 | FSL_IMX6_GPIO3_HIGH_IRQ |
| 279 | }, |
| 280 | { |
| 281 | FSL_IMX6_GPIO4_ADDR, |
| 282 | FSL_IMX6_GPIO4_LOW_IRQ, |
| 283 | FSL_IMX6_GPIO4_HIGH_IRQ |
| 284 | }, |
| 285 | { |
| 286 | FSL_IMX6_GPIO5_ADDR, |
| 287 | FSL_IMX6_GPIO5_LOW_IRQ, |
| 288 | FSL_IMX6_GPIO5_HIGH_IRQ |
| 289 | }, |
| 290 | { |
| 291 | FSL_IMX6_GPIO6_ADDR, |
| 292 | FSL_IMX6_GPIO6_LOW_IRQ, |
| 293 | FSL_IMX6_GPIO6_HIGH_IRQ |
| 294 | }, |
| 295 | { |
| 296 | FSL_IMX6_GPIO7_ADDR, |
| 297 | FSL_IMX6_GPIO7_LOW_IRQ, |
| 298 | FSL_IMX6_GPIO7_HIGH_IRQ |
| 299 | }, |
| 300 | }; |
| 301 | |
| 302 | object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, |
| 303 | &error_abort); |
| 304 | object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", |
| 305 | true, &error_abort); |
| 306 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { |
| 307 | return; |
| 308 | } |
| 309 | |
| 310 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); |
| 311 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 312 | qdev_get_gpio_in(gic, gpio_table[i].irq_low)); |
| 313 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, |
| 314 | qdev_get_gpio_in(gic, gpio_table[i].irq_high)); |
| 315 | } |
| 316 | |
| 317 | /* Initialize all SDHC */ |
| 318 | for (i = 0; i < FSL_IMX6_NUM_USDHCS; i++) { |
| 319 | static const struct { |
| 320 | hwaddr addr; |
| 321 | unsigned int irq; |
| 322 | } esdhc_table[FSL_IMX6_NUM_USDHCS] = { |
| 323 | { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, |
| 324 | { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, |
| 325 | { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, |
| 326 | { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, |
| 327 | }; |
| 328 | |
| 329 | /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ |
| 330 | object_property_set_uint(OBJECT(&s->usdhc[i]), "capareg", |
| 331 | IMX6_ESDHC_CAPABILITIES, &error_abort); |
| 332 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { |
| 333 | return; |
| 334 | } |
| 335 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, esdhc_table[i].addr); |
| 336 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, |
| 337 | qdev_get_gpio_in(gic, esdhc_table[i].irq)); |
| 338 | } |
| 339 | |
| 340 | /* USB */ |
| 341 | for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { |
| 342 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); |
| 343 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, |
| 344 | FSL_IMX6_USBPHY1_ADDR + i * 0x1000); |
| 345 | } |
| 346 | for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { |
| 347 | static const int FSL_IMX6_USBn_IRQ[] = { |
| 348 | FSL_IMX6_USB_OTG_IRQ, |
| 349 | FSL_IMX6_USB_HOST1_IRQ, |
| 350 | FSL_IMX6_USB_HOST2_IRQ, |
| 351 | FSL_IMX6_USB_HOST3_IRQ, |
| 352 | }; |
| 353 | |
| 354 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); |
| 355 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 356 | FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); |
| 357 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 358 | qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i])); |
| 359 | } |
| 360 | |
| 361 | /* Initialize all ECSPI */ |
| 362 | for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { |
| 363 | static const struct { |
| 364 | hwaddr addr; |
| 365 | unsigned int irq; |
| 366 | } spi_table[FSL_IMX6_NUM_ECSPIS] = { |
| 367 | { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, |
| 368 | { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, |
| 369 | { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, |
| 370 | { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, |
| 371 | { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, |
| 372 | }; |
| 373 | |
| 374 | /* Initialize the SPI */ |
| 375 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
| 376 | return; |
| 377 | } |
| 378 | |
| 379 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); |
| 380 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 381 | qdev_get_gpio_in(gic, spi_table[i].irq)); |
| 382 | } |
| 383 | |
| 384 | /* Initialize all FLEXCANs */ |
| 385 | for (i = 0; i < FSL_IMX6_NUM_CANS; i++) { |
| 386 | static const struct { |
| 387 | hwaddr addr; |
| 388 | unsigned int irq; |
| 389 | } flexcan_table[FSL_IMX6_NUM_CANS] = { |
| 390 | { FSL_IMX6_CAN1_ADDR, FSL_IMX6_FLEXCAN1_IRQ }, |
| 391 | { FSL_IMX6_CAN2_ADDR, FSL_IMX6_FLEXCAN2_IRQ }, |
| 392 | }; |
| 393 | |
| 394 | object_property_set_link(OBJECT(&s->flexcan[i]), "clock-control-module", |
| 395 | OBJECT(&s->ccm), &error_abort); |
| 396 | object_property_set_link(OBJECT(&s->flexcan[i]), "canbus", |
| 397 | OBJECT(s->canbus[i]), &error_abort); |
| 398 | |
| 399 | sysbus_realize(SYS_BUS_DEVICE(&s->flexcan[i]), &error_abort); |
| 400 | |
| 401 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->flexcan[i]), 0, flexcan_table[i].addr); |
| 402 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->flexcan[i]), 0, |
| 403 | qdev_get_gpio_in(gic, flexcan_table[i].irq)); |
| 404 | } |
| 405 | |
| 406 | object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, |
| 407 | &error_abort); |
| 408 | qemu_configure_nic_device(DEVICE(&s->eth), true, NULL); |
| 409 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { |
| 410 | return; |
| 411 | } |
| 412 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); |
| 413 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, |
| 414 | qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ)); |
| 415 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, |
| 416 | qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ)); |
| 417 | |
| 418 | /* |
| 419 | * SNVS |
| 420 | */ |
| 421 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); |
| 422 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); |
| 423 | |
| 424 | /* |
| 425 | * Watchdog |
| 426 | */ |
| 427 | for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { |
| 428 | static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { |
| 429 | FSL_IMX6_WDOG1_ADDR, |
| 430 | FSL_IMX6_WDOG2_ADDR, |
| 431 | }; |
| 432 | static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { |
| 433 | FSL_IMX6_WDOG1_IRQ, |
| 434 | FSL_IMX6_WDOG2_IRQ, |
| 435 | }; |
| 436 | |
| 437 | object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", |
| 438 | true, &error_abort); |
| 439 | sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); |
| 440 | |
| 441 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); |
| 442 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, |
| 443 | qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i])); |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * PCIe |
| 448 | */ |
| 449 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); |
| 450 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); |
| 451 | |
| 452 | object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2, |
| 453 | &error_abort); |
| 454 | qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort); |
| 455 | |
| 456 | irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_MSI_IRQ); |
| 457 | qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); |
| 458 | |
| 459 | irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ); |
| 460 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); |
| 461 | irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ); |
| 462 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); |
| 463 | irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ); |
| 464 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); |
| 465 | irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); |
| 466 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); |
| 467 | irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1); |
| 468 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); |
| 469 | |
| 470 | /* |
| 471 | * PCIe PHY |
| 472 | */ |
| 473 | create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR, |
| 474 | FSL_IMX6_PCIe_SIZE); |
| 475 | |
| 476 | /* ROM memory */ |
| 477 | if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", |
| 478 | FSL_IMX6_ROM_SIZE, errp)) { |
| 479 | return; |
| 480 | } |
| 481 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, |
| 482 | &s->rom); |
| 483 | |
| 484 | /* CAAM memory */ |
| 485 | if (!memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", |
| 486 | FSL_IMX6_CAAM_MEM_SIZE, errp)) { |
| 487 | return; |
| 488 | } |
| 489 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, |
| 490 | &s->caam); |
| 491 | |
| 492 | /* OCRAM memory */ |
| 493 | if (!memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", |
| 494 | FSL_IMX6_OCRAM_SIZE, errp)) { |
| 495 | return; |
| 496 | } |
| 497 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, |
| 498 | &s->ocram); |
| 499 | |
| 500 | /* internal OCRAM (256 KB) is aliased over 1 MB */ |
| 501 | memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", |
| 502 | &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); |
| 503 | memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, |
| 504 | &s->ocram_alias); |
| 505 | } |
| 506 | |
| 507 | static const Property fsl_imx6_properties[] = { |
| 508 | DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), |
| 509 | DEFINE_PROP_LINK("canbus0", FslIMX6State, canbus[0], TYPE_CAN_BUS, |
| 510 | CanBusState *), |
| 511 | DEFINE_PROP_LINK("canbus1", FslIMX6State, canbus[1], TYPE_CAN_BUS, |
| 512 | CanBusState *), |
| 513 | }; |
| 514 | |
| 515 | static void fsl_imx6_class_init(ObjectClass *oc, const void *data) |
| 516 | { |
| 517 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 518 | |
| 519 | device_class_set_props(dc, fsl_imx6_properties); |
| 520 | dc->realize = fsl_imx6_realize; |
| 521 | dc->desc = "i.MX6 SOC"; |
| 522 | /* Reason: Uses serial_hd() in the realize() function */ |
| 523 | dc->user_creatable = false; |
| 524 | } |
| 525 | |
| 526 | static const TypeInfo fsl_imx6_type_info = { |
| 527 | .name = TYPE_FSL_IMX6, |
| 528 | .parent = TYPE_DEVICE, |
| 529 | .instance_size = sizeof(FslIMX6State), |
| 530 | .instance_init = fsl_imx6_init, |
| 531 | .class_init = fsl_imx6_class_init, |
| 532 | }; |
| 533 | |
| 534 | static void fsl_imx6_register_types(void) |
| 535 | { |
| 536 | type_register_static(&fsl_imx6_type_info); |
| 537 | } |
| 538 | |
| 539 | type_init(fsl_imx6_register_types) |