| 1 | /* |
| 2 | * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> |
| 3 | * |
| 4 | * i.MX6UL SOC emulation. |
| 5 | * |
| 6 | * Based on hw/arm/fsl-imx7.c |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qapi/error.h" |
| 21 | #include "hw/arm/fsl-imx6ul.h" |
| 22 | #include "hw/display/imx6ul_lcdif.h" |
| 23 | #include "hw/misc/unimp.h" |
| 24 | #include "hw/usb/imx-usb-phy.h" |
| 25 | #include "hw/core/boards.h" |
| 26 | #include "system/system.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "target/arm/cpu-qom.h" |
| 30 | |
| 31 | #define NAME_SIZE 20 |
| 32 | |
| 33 | static void fsl_imx6ul_init(Object *obj) |
| 34 | { |
| 35 | FslIMX6ULState *s = FSL_IMX6UL(obj); |
| 36 | char name[NAME_SIZE]; |
| 37 | int i; |
| 38 | |
| 39 | object_initialize_child(obj, "cpu0", &s->cpu, |
| 40 | ARM_CPU_TYPE_NAME("cortex-a7")); |
| 41 | |
| 42 | /* |
| 43 | * A7MPCORE |
| 44 | */ |
| 45 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
| 46 | TYPE_A15MPCORE_PRIV); |
| 47 | |
| 48 | /* |
| 49 | * CCM |
| 50 | */ |
| 51 | object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); |
| 52 | |
| 53 | /* |
| 54 | * SRC |
| 55 | */ |
| 56 | object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); |
| 57 | |
| 58 | /* |
| 59 | * GPCv2 |
| 60 | */ |
| 61 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); |
| 62 | |
| 63 | /* |
| 64 | * SNVS |
| 65 | */ |
| 66 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); |
| 67 | |
| 68 | /* |
| 69 | * GPIOs |
| 70 | */ |
| 71 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { |
| 72 | snprintf(name, NAME_SIZE, "gpio%d", i); |
| 73 | object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); |
| 74 | } |
| 75 | |
| 76 | /* |
| 77 | * GPTs |
| 78 | */ |
| 79 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { |
| 80 | snprintf(name, NAME_SIZE, "gpt%d", i); |
| 81 | object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT); |
| 82 | } |
| 83 | |
| 84 | /* |
| 85 | * EPITs |
| 86 | */ |
| 87 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { |
| 88 | snprintf(name, NAME_SIZE, "epit%d", i + 1); |
| 89 | object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * eCSPIs |
| 94 | */ |
| 95 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { |
| 96 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
| 97 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * I2Cs |
| 102 | */ |
| 103 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { |
| 104 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
| 105 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * UARTs |
| 110 | */ |
| 111 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { |
| 112 | snprintf(name, NAME_SIZE, "uart%d", i); |
| 113 | object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Ethernets |
| 118 | */ |
| 119 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { |
| 120 | snprintf(name, NAME_SIZE, "eth%d", i); |
| 121 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * USB PHYs |
| 126 | */ |
| 127 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { |
| 128 | snprintf(name, NAME_SIZE, "usbphy%d", i); |
| 129 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); |
| 130 | } |
| 131 | |
| 132 | /* |
| 133 | * USBs |
| 134 | */ |
| 135 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { |
| 136 | snprintf(name, NAME_SIZE, "usb%d", i); |
| 137 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); |
| 138 | } |
| 139 | |
| 140 | /* |
| 141 | * LCDIF |
| 142 | */ |
| 143 | object_initialize_child(obj, "lcdif", &s->lcdif, TYPE_IMX6UL_LCDIF); |
| 144 | |
| 145 | /* |
| 146 | * SDHCIs |
| 147 | */ |
| 148 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { |
| 149 | snprintf(name, NAME_SIZE, "usdhc%d", i); |
| 150 | object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * Watchdogs |
| 155 | */ |
| 156 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { |
| 157 | snprintf(name, NAME_SIZE, "wdt%d", i); |
| 158 | object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
| 163 | { |
| 164 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 165 | FslIMX6ULState *s = FSL_IMX6UL(dev); |
| 166 | DeviceState *mpcore = DEVICE(&s->a7mpcore); |
| 167 | int i; |
| 168 | char name[NAME_SIZE]; |
| 169 | DeviceState *gic; |
| 170 | SysBusDevice *gicsbd; |
| 171 | DeviceState *cpu; |
| 172 | |
| 173 | if (ms->smp.cpus > 1) { |
| 174 | error_setg(errp, "%s: Only a single CPU is supported (%d requested)", |
| 175 | TYPE_FSL_IMX6UL, ms->smp.cpus); |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); |
| 180 | |
| 181 | /* |
| 182 | * A7MPCORE |
| 183 | */ |
| 184 | object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort); |
| 185 | object_property_set_int(OBJECT(mpcore), "num-irq", |
| 186 | FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); |
| 187 | sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); |
| 188 | sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); |
| 189 | |
| 190 | gic = mpcore; |
| 191 | gicsbd = SYS_BUS_DEVICE(gic); |
| 192 | cpu = DEVICE(&s->cpu); |
| 193 | sysbus_connect_irq(gicsbd, 0, qdev_get_gpio_in(cpu, ARM_CPU_IRQ)); |
| 194 | sysbus_connect_irq(gicsbd, 1, qdev_get_gpio_in(cpu, ARM_CPU_FIQ)); |
| 195 | sysbus_connect_irq(gicsbd, 2, qdev_get_gpio_in(cpu, ARM_CPU_VIRQ)); |
| 196 | sysbus_connect_irq(gicsbd, 3, qdev_get_gpio_in(cpu, ARM_CPU_VFIQ)); |
| 197 | |
| 198 | /* |
| 199 | * A7MPCORE DAP |
| 200 | */ |
| 201 | create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, |
| 202 | FSL_IMX6UL_A7MPCORE_DAP_SIZE); |
| 203 | |
| 204 | /* |
| 205 | * MMDC |
| 206 | */ |
| 207 | create_unimplemented_device("a7mpcore-mmdc", FSL_IMX6UL_MMDC_CFG_ADDR, |
| 208 | FSL_IMX6UL_MMDC_CFG_SIZE); |
| 209 | |
| 210 | /* |
| 211 | * OCOTP |
| 212 | */ |
| 213 | create_unimplemented_device("a7mpcore-ocotp", FSL_IMX6UL_OCOTP_CTRL_ADDR, |
| 214 | FSL_IMX6UL_OCOTP_CTRL_SIZE); |
| 215 | |
| 216 | /* |
| 217 | * QSPI |
| 218 | */ |
| 219 | create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_QSPI_ADDR, |
| 220 | FSL_IMX6UL_QSPI_SIZE); |
| 221 | |
| 222 | /* |
| 223 | * CAAM |
| 224 | */ |
| 225 | create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_CAAM_ADDR, |
| 226 | FSL_IMX6UL_CAAM_SIZE); |
| 227 | |
| 228 | /* |
| 229 | * USBMISC |
| 230 | */ |
| 231 | create_unimplemented_device("a7mpcore-usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR, |
| 232 | FSL_IMX6UL_USBO2_USBMISC_SIZE); |
| 233 | |
| 234 | /* |
| 235 | * GPTs |
| 236 | */ |
| 237 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { |
| 238 | static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { |
| 239 | FSL_IMX6UL_GPT1_ADDR, |
| 240 | FSL_IMX6UL_GPT2_ADDR, |
| 241 | }; |
| 242 | |
| 243 | static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { |
| 244 | FSL_IMX6UL_GPT1_IRQ, |
| 245 | FSL_IMX6UL_GPT2_IRQ, |
| 246 | }; |
| 247 | |
| 248 | s->gpt[i].ccm = IMX_CCM(&s->ccm); |
| 249 | sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); |
| 250 | |
| 251 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, |
| 252 | FSL_IMX6UL_GPTn_ADDR[i]); |
| 253 | |
| 254 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, |
| 255 | qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i])); |
| 256 | } |
| 257 | |
| 258 | /* |
| 259 | * EPITs |
| 260 | */ |
| 261 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { |
| 262 | static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { |
| 263 | FSL_IMX6UL_EPIT1_ADDR, |
| 264 | FSL_IMX6UL_EPIT2_ADDR, |
| 265 | }; |
| 266 | |
| 267 | static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { |
| 268 | FSL_IMX6UL_EPIT1_IRQ, |
| 269 | FSL_IMX6UL_EPIT2_IRQ, |
| 270 | }; |
| 271 | |
| 272 | s->epit[i].ccm = IMX_CCM(&s->ccm); |
| 273 | sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort); |
| 274 | |
| 275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, |
| 276 | FSL_IMX6UL_EPITn_ADDR[i]); |
| 277 | |
| 278 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, |
| 279 | qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i])); |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * GPIOs |
| 284 | */ |
| 285 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { |
| 286 | static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { |
| 287 | FSL_IMX6UL_GPIO1_ADDR, |
| 288 | FSL_IMX6UL_GPIO2_ADDR, |
| 289 | FSL_IMX6UL_GPIO3_ADDR, |
| 290 | FSL_IMX6UL_GPIO4_ADDR, |
| 291 | FSL_IMX6UL_GPIO5_ADDR, |
| 292 | }; |
| 293 | |
| 294 | static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { |
| 295 | FSL_IMX6UL_GPIO1_LOW_IRQ, |
| 296 | FSL_IMX6UL_GPIO2_LOW_IRQ, |
| 297 | FSL_IMX6UL_GPIO3_LOW_IRQ, |
| 298 | FSL_IMX6UL_GPIO4_LOW_IRQ, |
| 299 | FSL_IMX6UL_GPIO5_LOW_IRQ, |
| 300 | }; |
| 301 | |
| 302 | static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { |
| 303 | FSL_IMX6UL_GPIO1_HIGH_IRQ, |
| 304 | FSL_IMX6UL_GPIO2_HIGH_IRQ, |
| 305 | FSL_IMX6UL_GPIO3_HIGH_IRQ, |
| 306 | FSL_IMX6UL_GPIO4_HIGH_IRQ, |
| 307 | FSL_IMX6UL_GPIO5_HIGH_IRQ, |
| 308 | }; |
| 309 | |
| 310 | sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); |
| 311 | |
| 312 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 313 | FSL_IMX6UL_GPIOn_ADDR[i]); |
| 314 | |
| 315 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 316 | qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i])); |
| 317 | |
| 318 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, |
| 319 | qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * IOMUXC |
| 324 | */ |
| 325 | create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, |
| 326 | FSL_IMX6UL_IOMUXC_SIZE); |
| 327 | create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, |
| 328 | FSL_IMX6UL_IOMUXC_GPR_SIZE); |
| 329 | |
| 330 | /* |
| 331 | * CCM |
| 332 | */ |
| 333 | sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); |
| 334 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); |
| 335 | |
| 336 | /* |
| 337 | * SRC |
| 338 | */ |
| 339 | sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); |
| 340 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); |
| 341 | |
| 342 | /* |
| 343 | * GPCv2 |
| 344 | */ |
| 345 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); |
| 346 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); |
| 347 | |
| 348 | /* |
| 349 | * ECSPIs |
| 350 | */ |
| 351 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { |
| 352 | static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { |
| 353 | FSL_IMX6UL_ECSPI1_ADDR, |
| 354 | FSL_IMX6UL_ECSPI2_ADDR, |
| 355 | FSL_IMX6UL_ECSPI3_ADDR, |
| 356 | FSL_IMX6UL_ECSPI4_ADDR, |
| 357 | }; |
| 358 | |
| 359 | static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { |
| 360 | FSL_IMX6UL_ECSPI1_IRQ, |
| 361 | FSL_IMX6UL_ECSPI2_IRQ, |
| 362 | FSL_IMX6UL_ECSPI3_IRQ, |
| 363 | FSL_IMX6UL_ECSPI4_IRQ, |
| 364 | }; |
| 365 | |
| 366 | /* Initialize the SPI */ |
| 367 | sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); |
| 368 | |
| 369 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 370 | FSL_IMX6UL_SPIn_ADDR[i]); |
| 371 | |
| 372 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 373 | qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i])); |
| 374 | } |
| 375 | |
| 376 | /* |
| 377 | * I2Cs |
| 378 | */ |
| 379 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { |
| 380 | static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { |
| 381 | FSL_IMX6UL_I2C1_ADDR, |
| 382 | FSL_IMX6UL_I2C2_ADDR, |
| 383 | FSL_IMX6UL_I2C3_ADDR, |
| 384 | FSL_IMX6UL_I2C4_ADDR, |
| 385 | }; |
| 386 | |
| 387 | static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { |
| 388 | FSL_IMX6UL_I2C1_IRQ, |
| 389 | FSL_IMX6UL_I2C2_IRQ, |
| 390 | FSL_IMX6UL_I2C3_IRQ, |
| 391 | FSL_IMX6UL_I2C4_IRQ, |
| 392 | }; |
| 393 | |
| 394 | sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); |
| 395 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); |
| 396 | |
| 397 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, |
| 398 | qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i])); |
| 399 | } |
| 400 | |
| 401 | /* |
| 402 | * UARTs |
| 403 | */ |
| 404 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { |
| 405 | static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { |
| 406 | FSL_IMX6UL_UART1_ADDR, |
| 407 | FSL_IMX6UL_UART2_ADDR, |
| 408 | FSL_IMX6UL_UART3_ADDR, |
| 409 | FSL_IMX6UL_UART4_ADDR, |
| 410 | FSL_IMX6UL_UART5_ADDR, |
| 411 | FSL_IMX6UL_UART6_ADDR, |
| 412 | FSL_IMX6UL_UART7_ADDR, |
| 413 | FSL_IMX6UL_UART8_ADDR, |
| 414 | }; |
| 415 | |
| 416 | static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { |
| 417 | FSL_IMX6UL_UART1_IRQ, |
| 418 | FSL_IMX6UL_UART2_IRQ, |
| 419 | FSL_IMX6UL_UART3_IRQ, |
| 420 | FSL_IMX6UL_UART4_IRQ, |
| 421 | FSL_IMX6UL_UART5_IRQ, |
| 422 | FSL_IMX6UL_UART6_IRQ, |
| 423 | FSL_IMX6UL_UART7_IRQ, |
| 424 | FSL_IMX6UL_UART8_IRQ, |
| 425 | }; |
| 426 | |
| 427 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
| 428 | |
| 429 | sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); |
| 430 | |
| 431 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 432 | FSL_IMX6UL_UARTn_ADDR[i]); |
| 433 | |
| 434 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, |
| 435 | qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i])); |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * Ethernets |
| 440 | * |
| 441 | * We must use two loops since phy_connected affects the other interface |
| 442 | * and we have to set all properties before calling sysbus_realize(). |
| 443 | */ |
| 444 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { |
| 445 | object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", |
| 446 | s->phy_connected[i], &error_abort); |
| 447 | /* |
| 448 | * If the MDIO bus on this controller is not connected, assume the |
| 449 | * other controller provides support for it. |
| 450 | */ |
| 451 | if (!s->phy_connected[i]) { |
| 452 | object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", |
| 453 | OBJECT(&s->eth[i]), &error_abort); |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { |
| 458 | static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { |
| 459 | FSL_IMX6UL_ENET1_ADDR, |
| 460 | FSL_IMX6UL_ENET2_ADDR, |
| 461 | }; |
| 462 | |
| 463 | static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { |
| 464 | FSL_IMX6UL_ENET1_IRQ, |
| 465 | FSL_IMX6UL_ENET2_IRQ, |
| 466 | }; |
| 467 | |
| 468 | static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { |
| 469 | FSL_IMX6UL_ENET1_TIMER_IRQ, |
| 470 | FSL_IMX6UL_ENET2_TIMER_IRQ, |
| 471 | }; |
| 472 | |
| 473 | object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", |
| 474 | s->phy_num[i], &error_abort); |
| 475 | object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", |
| 476 | FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort); |
| 477 | qemu_configure_nic_device(DEVICE(&s->eth[i]), true, NULL); |
| 478 | sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); |
| 479 | |
| 480 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, |
| 481 | FSL_IMX6UL_ENETn_ADDR[i]); |
| 482 | |
| 483 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, |
| 484 | qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_IRQ[i])); |
| 485 | |
| 486 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, |
| 487 | qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_TIMER_IRQ[i])); |
| 488 | } |
| 489 | |
| 490 | /* |
| 491 | * USB PHYs |
| 492 | */ |
| 493 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { |
| 494 | static const hwaddr |
| 495 | FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { |
| 496 | FSL_IMX6UL_USBPHY1_ADDR, |
| 497 | FSL_IMX6UL_USBPHY2_ADDR, |
| 498 | }; |
| 499 | |
| 500 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); |
| 501 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, |
| 502 | FSL_IMX6UL_USB_PHYn_ADDR[i]); |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * USBs |
| 507 | */ |
| 508 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { |
| 509 | static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { |
| 510 | FSL_IMX6UL_USBO2_USB1_ADDR, |
| 511 | FSL_IMX6UL_USBO2_USB2_ADDR, |
| 512 | }; |
| 513 | |
| 514 | static const int FSL_IMX6UL_USBn_IRQ[] = { |
| 515 | FSL_IMX6UL_USB1_IRQ, |
| 516 | FSL_IMX6UL_USB2_IRQ, |
| 517 | }; |
| 518 | |
| 519 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); |
| 520 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 521 | FSL_IMX6UL_USB02_USBn_ADDR[i]); |
| 522 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 523 | qdev_get_gpio_in(gic, FSL_IMX6UL_USBn_IRQ[i])); |
| 524 | } |
| 525 | |
| 526 | /* |
| 527 | * USDHCs |
| 528 | */ |
| 529 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { |
| 530 | static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { |
| 531 | FSL_IMX6UL_USDHC1_ADDR, |
| 532 | FSL_IMX6UL_USDHC2_ADDR, |
| 533 | }; |
| 534 | |
| 535 | static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { |
| 536 | FSL_IMX6UL_USDHC1_IRQ, |
| 537 | FSL_IMX6UL_USDHC2_IRQ, |
| 538 | }; |
| 539 | |
| 540 | sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); |
| 541 | |
| 542 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, |
| 543 | FSL_IMX6UL_USDHCn_ADDR[i]); |
| 544 | |
| 545 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, |
| 546 | qdev_get_gpio_in(gic, FSL_IMX6UL_USDHCn_IRQ[i])); |
| 547 | } |
| 548 | |
| 549 | /* |
| 550 | * SNVS |
| 551 | */ |
| 552 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); |
| 553 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); |
| 554 | |
| 555 | /* |
| 556 | * Watchdogs |
| 557 | */ |
| 558 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { |
| 559 | static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { |
| 560 | FSL_IMX6UL_WDOG1_ADDR, |
| 561 | FSL_IMX6UL_WDOG2_ADDR, |
| 562 | FSL_IMX6UL_WDOG3_ADDR, |
| 563 | }; |
| 564 | |
| 565 | static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { |
| 566 | FSL_IMX6UL_WDOG1_IRQ, |
| 567 | FSL_IMX6UL_WDOG2_IRQ, |
| 568 | FSL_IMX6UL_WDOG3_IRQ, |
| 569 | }; |
| 570 | |
| 571 | object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", |
| 572 | true, &error_abort); |
| 573 | sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); |
| 574 | |
| 575 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, |
| 576 | FSL_IMX6UL_WDOGn_ADDR[i]); |
| 577 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, |
| 578 | qdev_get_gpio_in(gic, FSL_IMX6UL_WDOGn_IRQ[i])); |
| 579 | } |
| 580 | |
| 581 | /* |
| 582 | * SDMA |
| 583 | */ |
| 584 | create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, |
| 585 | FSL_IMX6UL_SDMA_SIZE); |
| 586 | |
| 587 | /* |
| 588 | * SAIs (Audio SSI (Synchronous Serial Interface)) |
| 589 | */ |
| 590 | for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { |
| 591 | static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { |
| 592 | FSL_IMX6UL_SAI1_ADDR, |
| 593 | FSL_IMX6UL_SAI2_ADDR, |
| 594 | FSL_IMX6UL_SAI3_ADDR, |
| 595 | }; |
| 596 | |
| 597 | snprintf(name, NAME_SIZE, "sai%d", i); |
| 598 | create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], |
| 599 | FSL_IMX6UL_SAIn_SIZE); |
| 600 | } |
| 601 | |
| 602 | /* |
| 603 | * PWMs |
| 604 | */ |
| 605 | for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { |
| 606 | static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { |
| 607 | FSL_IMX6UL_PWM1_ADDR, |
| 608 | FSL_IMX6UL_PWM2_ADDR, |
| 609 | FSL_IMX6UL_PWM3_ADDR, |
| 610 | FSL_IMX6UL_PWM4_ADDR, |
| 611 | FSL_IMX6UL_PWM5_ADDR, |
| 612 | FSL_IMX6UL_PWM6_ADDR, |
| 613 | FSL_IMX6UL_PWM7_ADDR, |
| 614 | FSL_IMX6UL_PWM8_ADDR, |
| 615 | }; |
| 616 | |
| 617 | snprintf(name, NAME_SIZE, "pwm%d", i); |
| 618 | create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], |
| 619 | FSL_IMX6UL_PWMn_SIZE); |
| 620 | } |
| 621 | |
| 622 | /* |
| 623 | * Audio ASRC (asynchronous sample rate converter) |
| 624 | */ |
| 625 | create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, |
| 626 | FSL_IMX6UL_ASRC_SIZE); |
| 627 | |
| 628 | /* |
| 629 | * CANs |
| 630 | */ |
| 631 | for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { |
| 632 | static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { |
| 633 | FSL_IMX6UL_CAN1_ADDR, |
| 634 | FSL_IMX6UL_CAN2_ADDR, |
| 635 | }; |
| 636 | |
| 637 | snprintf(name, NAME_SIZE, "can%d", i); |
| 638 | create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], |
| 639 | FSL_IMX6UL_CANn_SIZE); |
| 640 | } |
| 641 | |
| 642 | /* |
| 643 | * APHB_DMA |
| 644 | */ |
| 645 | create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, |
| 646 | FSL_IMX6UL_APBH_DMA_SIZE); |
| 647 | |
| 648 | /* |
| 649 | * ADCs |
| 650 | */ |
| 651 | for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { |
| 652 | static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { |
| 653 | FSL_IMX6UL_ADC1_ADDR, |
| 654 | FSL_IMX6UL_ADC2_ADDR, |
| 655 | }; |
| 656 | |
| 657 | snprintf(name, NAME_SIZE, "adc%d", i); |
| 658 | create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], |
| 659 | FSL_IMX6UL_ADCn_SIZE); |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * LCD |
| 664 | */ |
| 665 | sysbus_realize(SYS_BUS_DEVICE(&s->lcdif), &error_abort); |
| 666 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lcdif), 0, FSL_IMX6UL_LCDIF_ADDR); |
| 667 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lcdif), 0, |
| 668 | qdev_get_gpio_in(gic, FSL_IMX6UL_LCDIF_IRQ)); |
| 669 | |
| 670 | /* |
| 671 | * CSU |
| 672 | */ |
| 673 | create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, |
| 674 | FSL_IMX6UL_CSU_SIZE); |
| 675 | |
| 676 | /* |
| 677 | * TZASC |
| 678 | */ |
| 679 | create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, |
| 680 | FSL_IMX6UL_TZASC_SIZE); |
| 681 | |
| 682 | /* |
| 683 | * ROM memory |
| 684 | */ |
| 685 | memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom", |
| 686 | FSL_IMX6UL_ROM_SIZE, &error_abort); |
| 687 | memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, |
| 688 | &s->rom); |
| 689 | |
| 690 | /* |
| 691 | * CAAM memory |
| 692 | */ |
| 693 | memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam", |
| 694 | FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); |
| 695 | memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, |
| 696 | &s->caam); |
| 697 | |
| 698 | /* |
| 699 | * OCRAM memory |
| 700 | */ |
| 701 | memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", |
| 702 | FSL_IMX6UL_OCRAM_MEM_SIZE, |
| 703 | &error_abort); |
| 704 | memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, |
| 705 | &s->ocram); |
| 706 | |
| 707 | /* |
| 708 | * internal OCRAM (128 KB) is aliased over 512 KB |
| 709 | */ |
| 710 | memory_region_init_alias(&s->ocram_alias, OBJECT(dev), |
| 711 | "imx6ul.ocram_alias", &s->ocram, 0, |
| 712 | FSL_IMX6UL_OCRAM_ALIAS_SIZE); |
| 713 | memory_region_add_subregion(get_system_memory(), |
| 714 | FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); |
| 715 | } |
| 716 | |
| 717 | static const Property fsl_imx6ul_properties[] = { |
| 718 | DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), |
| 719 | DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), |
| 720 | DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0], |
| 721 | true), |
| 722 | DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1], |
| 723 | true), |
| 724 | }; |
| 725 | |
| 726 | static void fsl_imx6ul_class_init(ObjectClass *oc, const void *data) |
| 727 | { |
| 728 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 729 | |
| 730 | device_class_set_props(dc, fsl_imx6ul_properties); |
| 731 | dc->realize = fsl_imx6ul_realize; |
| 732 | dc->desc = "i.MX6UL SOC"; |
| 733 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
| 734 | dc->user_creatable = false; |
| 735 | } |
| 736 | |
| 737 | static const TypeInfo fsl_imx6ul_type_info = { |
| 738 | .name = TYPE_FSL_IMX6UL, |
| 739 | .parent = TYPE_DEVICE, |
| 740 | .instance_size = sizeof(FslIMX6ULState), |
| 741 | .instance_init = fsl_imx6ul_init, |
| 742 | .class_init = fsl_imx6ul_class_init, |
| 743 | }; |
| 744 | |
| 745 | static void fsl_imx6ul_register_types(void) |
| 746 | { |
| 747 | type_register_static(&fsl_imx6ul_type_info); |
| 748 | } |
| 749 | type_init(fsl_imx6ul_register_types) |