| 1 | /* |
| 2 | * Copyright (c) 2018, Impinj, Inc. |
| 3 | * |
| 4 | * i.MX7 SoC definitions |
| 5 | * |
| 6 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> |
| 7 | * |
| 8 | * Based on hw/arm/fsl-imx6.c |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "hw/arm/fsl-imx7.h" |
| 24 | #include "hw/misc/unimp.h" |
| 25 | #include "hw/core/boards.h" |
| 26 | #include "system/system.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "target/arm/cpu-qom.h" |
| 30 | |
| 31 | #define NAME_SIZE 20 |
| 32 | |
| 33 | static void fsl_imx7_init(Object *obj) |
| 34 | { |
| 35 | FslIMX7State *s = FSL_IMX7(obj); |
| 36 | char name[NAME_SIZE]; |
| 37 | int i; |
| 38 | |
| 39 | /* |
| 40 | * A7MPCORE |
| 41 | */ |
| 42 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
| 43 | TYPE_A15MPCORE_PRIV); |
| 44 | |
| 45 | /* |
| 46 | * GPIOs |
| 47 | */ |
| 48 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { |
| 49 | snprintf(name, NAME_SIZE, "gpio%d", i); |
| 50 | object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); |
| 51 | } |
| 52 | |
| 53 | /* |
| 54 | * GPTs |
| 55 | */ |
| 56 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { |
| 57 | snprintf(name, NAME_SIZE, "gpt%d", i); |
| 58 | object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); |
| 59 | } |
| 60 | |
| 61 | /* |
| 62 | * CCM |
| 63 | */ |
| 64 | object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM); |
| 65 | |
| 66 | /* |
| 67 | * Analog |
| 68 | */ |
| 69 | object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG); |
| 70 | |
| 71 | /* |
| 72 | * GPCv2 |
| 73 | */ |
| 74 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); |
| 75 | |
| 76 | /* |
| 77 | * SRC |
| 78 | */ |
| 79 | object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); |
| 80 | |
| 81 | /* |
| 82 | * ECSPIs |
| 83 | */ |
| 84 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { |
| 85 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
| 86 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); |
| 87 | } |
| 88 | |
| 89 | /* |
| 90 | * I2Cs |
| 91 | */ |
| 92 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { |
| 93 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
| 94 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); |
| 95 | } |
| 96 | |
| 97 | /* |
| 98 | * UARTs |
| 99 | */ |
| 100 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { |
| 101 | snprintf(name, NAME_SIZE, "uart%d", i); |
| 102 | object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); |
| 103 | } |
| 104 | |
| 105 | /* |
| 106 | * Ethernets |
| 107 | */ |
| 108 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { |
| 109 | snprintf(name, NAME_SIZE, "eth%d", i); |
| 110 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); |
| 111 | } |
| 112 | |
| 113 | /* |
| 114 | * SDHCIs |
| 115 | */ |
| 116 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { |
| 117 | snprintf(name, NAME_SIZE, "usdhc%d", i); |
| 118 | object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | * SNVS |
| 123 | */ |
| 124 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); |
| 125 | |
| 126 | /* |
| 127 | * Watchdogs |
| 128 | */ |
| 129 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { |
| 130 | snprintf(name, NAME_SIZE, "wdt%d", i); |
| 131 | object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); |
| 132 | } |
| 133 | |
| 134 | /* |
| 135 | * GPR |
| 136 | */ |
| 137 | object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); |
| 138 | |
| 139 | /* |
| 140 | * PCIE |
| 141 | */ |
| 142 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); |
| 143 | object_initialize_child(obj, "pcie4-msi-irq", &s->pcie4_msi_irq, |
| 144 | TYPE_OR_IRQ); |
| 145 | |
| 146 | /* |
| 147 | * USBs |
| 148 | */ |
| 149 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { |
| 150 | snprintf(name, NAME_SIZE, "usb%d", i); |
| 151 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
| 156 | { |
| 157 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 158 | FslIMX7State *s = FSL_IMX7(dev); |
| 159 | DeviceState *mpcore = DEVICE(&s->a7mpcore); |
| 160 | DeviceState *gic; |
| 161 | int i; |
| 162 | qemu_irq irq; |
| 163 | char name[NAME_SIZE]; |
| 164 | unsigned int smp_cpus = ms->smp.cpus; |
| 165 | |
| 166 | if (smp_cpus > FSL_IMX7_NUM_CPUS) { |
| 167 | error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", |
| 168 | TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); |
| 169 | return; |
| 170 | } |
| 171 | |
| 172 | /* |
| 173 | * CPUs |
| 174 | */ |
| 175 | for (i = 0; i < smp_cpus; i++) { |
| 176 | snprintf(name, NAME_SIZE, "cpu%d", i); |
| 177 | object_initialize_child(OBJECT(dev), name, &s->cpu[i], |
| 178 | ARM_CPU_TYPE_NAME("cortex-a7")); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * CPUs |
| 183 | */ |
| 184 | for (i = 0; i < smp_cpus; i++) { |
| 185 | Object *o = OBJECT(&s->cpu[i]); |
| 186 | |
| 187 | /* On uniprocessor, the CBAR is set to 0 */ |
| 188 | if (smp_cpus > 1) { |
| 189 | object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR, |
| 190 | &error_abort); |
| 191 | } |
| 192 | |
| 193 | if (i) { |
| 194 | /* |
| 195 | * Secondary CPUs start in powered-down state (and can be |
| 196 | * powered up via the SRC system reset controller) |
| 197 | */ |
| 198 | object_property_set_bool(o, "start-powered-off", true, |
| 199 | &error_abort); |
| 200 | } |
| 201 | |
| 202 | qdev_realize(DEVICE(o), NULL, &error_abort); |
| 203 | } |
| 204 | |
| 205 | /* |
| 206 | * A7MPCORE |
| 207 | */ |
| 208 | object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort); |
| 209 | object_property_set_int(OBJECT(mpcore), "num-irq", |
| 210 | FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); |
| 211 | sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort); |
| 212 | sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); |
| 213 | |
| 214 | gic = mpcore; |
| 215 | for (i = 0; i < smp_cpus; i++) { |
| 216 | SysBusDevice *sbd = SYS_BUS_DEVICE(gic); |
| 217 | DeviceState *d = DEVICE(qemu_get_cpu(i)); |
| 218 | |
| 219 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); |
| 220 | sysbus_connect_irq(sbd, i, irq); |
| 221 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); |
| 222 | sysbus_connect_irq(sbd, i + smp_cpus, irq); |
| 223 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
| 224 | sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq); |
| 225 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
| 226 | sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq); |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * A7MPCORE DAP |
| 231 | */ |
| 232 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, |
| 233 | FSL_IMX7_A7MPCORE_DAP_SIZE); |
| 234 | |
| 235 | /* |
| 236 | * GPTs |
| 237 | */ |
| 238 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { |
| 239 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { |
| 240 | FSL_IMX7_GPT1_ADDR, |
| 241 | FSL_IMX7_GPT2_ADDR, |
| 242 | FSL_IMX7_GPT3_ADDR, |
| 243 | FSL_IMX7_GPT4_ADDR, |
| 244 | }; |
| 245 | |
| 246 | static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = { |
| 247 | FSL_IMX7_GPT1_IRQ, |
| 248 | FSL_IMX7_GPT2_IRQ, |
| 249 | FSL_IMX7_GPT3_IRQ, |
| 250 | FSL_IMX7_GPT4_IRQ, |
| 251 | }; |
| 252 | |
| 253 | s->gpt[i].ccm = IMX_CCM(&s->ccm); |
| 254 | sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); |
| 255 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); |
| 256 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, |
| 257 | qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i])); |
| 258 | } |
| 259 | |
| 260 | /* |
| 261 | * GPIOs |
| 262 | */ |
| 263 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { |
| 264 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { |
| 265 | FSL_IMX7_GPIO1_ADDR, |
| 266 | FSL_IMX7_GPIO2_ADDR, |
| 267 | FSL_IMX7_GPIO3_ADDR, |
| 268 | FSL_IMX7_GPIO4_ADDR, |
| 269 | FSL_IMX7_GPIO5_ADDR, |
| 270 | FSL_IMX7_GPIO6_ADDR, |
| 271 | FSL_IMX7_GPIO7_ADDR, |
| 272 | }; |
| 273 | |
| 274 | static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = { |
| 275 | FSL_IMX7_GPIO1_LOW_IRQ, |
| 276 | FSL_IMX7_GPIO2_LOW_IRQ, |
| 277 | FSL_IMX7_GPIO3_LOW_IRQ, |
| 278 | FSL_IMX7_GPIO4_LOW_IRQ, |
| 279 | FSL_IMX7_GPIO5_LOW_IRQ, |
| 280 | FSL_IMX7_GPIO6_LOW_IRQ, |
| 281 | FSL_IMX7_GPIO7_LOW_IRQ, |
| 282 | }; |
| 283 | |
| 284 | static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = { |
| 285 | FSL_IMX7_GPIO1_HIGH_IRQ, |
| 286 | FSL_IMX7_GPIO2_HIGH_IRQ, |
| 287 | FSL_IMX7_GPIO3_HIGH_IRQ, |
| 288 | FSL_IMX7_GPIO4_HIGH_IRQ, |
| 289 | FSL_IMX7_GPIO5_HIGH_IRQ, |
| 290 | FSL_IMX7_GPIO6_HIGH_IRQ, |
| 291 | FSL_IMX7_GPIO7_HIGH_IRQ, |
| 292 | }; |
| 293 | |
| 294 | sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); |
| 295 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 296 | FSL_IMX7_GPIOn_ADDR[i]); |
| 297 | |
| 298 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, |
| 299 | qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i])); |
| 300 | |
| 301 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, |
| 302 | qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i])); |
| 303 | } |
| 304 | |
| 305 | /* |
| 306 | * IOMUXC and IOMUXC_LPSR |
| 307 | */ |
| 308 | create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, |
| 309 | FSL_IMX7_IOMUXC_SIZE); |
| 310 | create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, |
| 311 | FSL_IMX7_IOMUXC_LPSR_SIZE); |
| 312 | |
| 313 | /* |
| 314 | * CCM |
| 315 | */ |
| 316 | sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); |
| 317 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); |
| 318 | |
| 319 | /* |
| 320 | * Analog |
| 321 | */ |
| 322 | sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort); |
| 323 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR); |
| 324 | |
| 325 | /* |
| 326 | * GPCv2 |
| 327 | */ |
| 328 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); |
| 329 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); |
| 330 | |
| 331 | /* |
| 332 | * ECSPIs |
| 333 | */ |
| 334 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { |
| 335 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { |
| 336 | FSL_IMX7_ECSPI1_ADDR, |
| 337 | FSL_IMX7_ECSPI2_ADDR, |
| 338 | FSL_IMX7_ECSPI3_ADDR, |
| 339 | FSL_IMX7_ECSPI4_ADDR, |
| 340 | }; |
| 341 | |
| 342 | static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = { |
| 343 | FSL_IMX7_ECSPI1_IRQ, |
| 344 | FSL_IMX7_ECSPI2_IRQ, |
| 345 | FSL_IMX7_ECSPI3_IRQ, |
| 346 | FSL_IMX7_ECSPI4_IRQ, |
| 347 | }; |
| 348 | |
| 349 | /* Initialize the SPI */ |
| 350 | sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); |
| 351 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 352 | FSL_IMX7_SPIn_ADDR[i]); |
| 353 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, |
| 354 | qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i])); |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * I2Cs |
| 359 | */ |
| 360 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { |
| 361 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { |
| 362 | FSL_IMX7_I2C1_ADDR, |
| 363 | FSL_IMX7_I2C2_ADDR, |
| 364 | FSL_IMX7_I2C3_ADDR, |
| 365 | FSL_IMX7_I2C4_ADDR, |
| 366 | }; |
| 367 | |
| 368 | static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = { |
| 369 | FSL_IMX7_I2C1_IRQ, |
| 370 | FSL_IMX7_I2C2_IRQ, |
| 371 | FSL_IMX7_I2C3_IRQ, |
| 372 | FSL_IMX7_I2C4_IRQ, |
| 373 | }; |
| 374 | |
| 375 | sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); |
| 376 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); |
| 377 | |
| 378 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, |
| 379 | qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i])); |
| 380 | } |
| 381 | |
| 382 | /* |
| 383 | * UARTs |
| 384 | */ |
| 385 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { |
| 386 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { |
| 387 | FSL_IMX7_UART1_ADDR, |
| 388 | FSL_IMX7_UART2_ADDR, |
| 389 | FSL_IMX7_UART3_ADDR, |
| 390 | FSL_IMX7_UART4_ADDR, |
| 391 | FSL_IMX7_UART5_ADDR, |
| 392 | FSL_IMX7_UART6_ADDR, |
| 393 | FSL_IMX7_UART7_ADDR, |
| 394 | }; |
| 395 | |
| 396 | static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = { |
| 397 | FSL_IMX7_UART1_IRQ, |
| 398 | FSL_IMX7_UART2_IRQ, |
| 399 | FSL_IMX7_UART3_IRQ, |
| 400 | FSL_IMX7_UART4_IRQ, |
| 401 | FSL_IMX7_UART5_IRQ, |
| 402 | FSL_IMX7_UART6_IRQ, |
| 403 | FSL_IMX7_UART7_IRQ, |
| 404 | }; |
| 405 | |
| 406 | |
| 407 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
| 408 | |
| 409 | sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); |
| 410 | |
| 411 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); |
| 412 | |
| 413 | irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]); |
| 414 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); |
| 415 | } |
| 416 | |
| 417 | /* |
| 418 | * Ethernets |
| 419 | * |
| 420 | * We must use two loops since phy_connected affects the other interface |
| 421 | * and we have to set all properties before calling sysbus_realize(). |
| 422 | */ |
| 423 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { |
| 424 | object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", |
| 425 | s->phy_connected[i], &error_abort); |
| 426 | /* |
| 427 | * If the MDIO bus on this controller is not connected, assume the |
| 428 | * other controller provides support for it. |
| 429 | */ |
| 430 | if (!s->phy_connected[i]) { |
| 431 | object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", |
| 432 | OBJECT(&s->eth[i]), &error_abort); |
| 433 | } |
| 434 | } |
| 435 | |
| 436 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { |
| 437 | static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = { |
| 438 | FSL_IMX7_ENET1_ADDR, |
| 439 | FSL_IMX7_ENET2_ADDR, |
| 440 | }; |
| 441 | |
| 442 | object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", |
| 443 | s->phy_num[i], &error_abort); |
| 444 | object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", |
| 445 | FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); |
| 446 | qemu_configure_nic_device(DEVICE(&s->eth[i]), true, NULL); |
| 447 | sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); |
| 448 | |
| 449 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); |
| 450 | |
| 451 | irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0)); |
| 452 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); |
| 453 | irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3)); |
| 454 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); |
| 455 | } |
| 456 | |
| 457 | /* |
| 458 | * USDHCs |
| 459 | */ |
| 460 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { |
| 461 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { |
| 462 | FSL_IMX7_USDHC1_ADDR, |
| 463 | FSL_IMX7_USDHC2_ADDR, |
| 464 | FSL_IMX7_USDHC3_ADDR, |
| 465 | }; |
| 466 | |
| 467 | static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = { |
| 468 | FSL_IMX7_USDHC1_IRQ, |
| 469 | FSL_IMX7_USDHC2_IRQ, |
| 470 | FSL_IMX7_USDHC3_IRQ, |
| 471 | }; |
| 472 | |
| 473 | sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); |
| 474 | |
| 475 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, |
| 476 | FSL_IMX7_USDHCn_ADDR[i]); |
| 477 | |
| 478 | irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]); |
| 479 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); |
| 480 | } |
| 481 | |
| 482 | /* |
| 483 | * SNVS |
| 484 | */ |
| 485 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); |
| 486 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); |
| 487 | |
| 488 | /* |
| 489 | * SRC |
| 490 | */ |
| 491 | sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); |
| 492 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); |
| 493 | |
| 494 | /* |
| 495 | * Watchdogs |
| 496 | */ |
| 497 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { |
| 498 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { |
| 499 | FSL_IMX7_WDOG1_ADDR, |
| 500 | FSL_IMX7_WDOG2_ADDR, |
| 501 | FSL_IMX7_WDOG3_ADDR, |
| 502 | FSL_IMX7_WDOG4_ADDR, |
| 503 | }; |
| 504 | static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = { |
| 505 | FSL_IMX7_WDOG1_IRQ, |
| 506 | FSL_IMX7_WDOG2_IRQ, |
| 507 | FSL_IMX7_WDOG3_IRQ, |
| 508 | FSL_IMX7_WDOG4_IRQ, |
| 509 | }; |
| 510 | |
| 511 | object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", |
| 512 | true, &error_abort); |
| 513 | sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); |
| 514 | |
| 515 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); |
| 516 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, |
| 517 | qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i])); |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * SDMA |
| 522 | */ |
| 523 | create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); |
| 524 | |
| 525 | /* |
| 526 | * CAAM |
| 527 | */ |
| 528 | create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); |
| 529 | |
| 530 | /* |
| 531 | * PWMs |
| 532 | */ |
| 533 | for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { |
| 534 | static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { |
| 535 | FSL_IMX7_PWM1_ADDR, |
| 536 | FSL_IMX7_PWM2_ADDR, |
| 537 | FSL_IMX7_PWM3_ADDR, |
| 538 | FSL_IMX7_PWM4_ADDR, |
| 539 | }; |
| 540 | |
| 541 | snprintf(name, NAME_SIZE, "pwm%d", i); |
| 542 | create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], |
| 543 | FSL_IMX7_PWMn_SIZE); |
| 544 | } |
| 545 | |
| 546 | /* |
| 547 | * CANs |
| 548 | */ |
| 549 | for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { |
| 550 | static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { |
| 551 | FSL_IMX7_CAN1_ADDR, |
| 552 | FSL_IMX7_CAN2_ADDR, |
| 553 | }; |
| 554 | |
| 555 | snprintf(name, NAME_SIZE, "can%d", i); |
| 556 | create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], |
| 557 | FSL_IMX7_CANn_SIZE); |
| 558 | } |
| 559 | |
| 560 | /* |
| 561 | * SAIs (Audio SSI (Synchronous Serial Interface)) |
| 562 | */ |
| 563 | for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { |
| 564 | static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { |
| 565 | FSL_IMX7_SAI1_ADDR, |
| 566 | FSL_IMX7_SAI2_ADDR, |
| 567 | FSL_IMX7_SAI3_ADDR, |
| 568 | }; |
| 569 | |
| 570 | snprintf(name, NAME_SIZE, "sai%d", i); |
| 571 | create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], |
| 572 | FSL_IMX7_SAIn_SIZE); |
| 573 | } |
| 574 | |
| 575 | /* |
| 576 | * OCOTP |
| 577 | */ |
| 578 | create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, |
| 579 | FSL_IMX7_OCOTP_SIZE); |
| 580 | |
| 581 | /* |
| 582 | * GPR |
| 583 | */ |
| 584 | sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); |
| 585 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); |
| 586 | |
| 587 | /* |
| 588 | * PCIE |
| 589 | */ |
| 590 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); |
| 591 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); |
| 592 | |
| 593 | object_property_set_int(OBJECT(&s->pcie4_msi_irq), "num-lines", 2, |
| 594 | &error_abort); |
| 595 | qdev_realize(DEVICE(&s->pcie4_msi_irq), NULL, &error_abort); |
| 596 | |
| 597 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ); |
| 598 | qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); |
| 599 | |
| 600 | irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ); |
| 601 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); |
| 602 | irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ); |
| 603 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); |
| 604 | irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ); |
| 605 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); |
| 606 | irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); |
| 607 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); |
| 608 | irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 1); |
| 609 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, irq); |
| 610 | |
| 611 | /* |
| 612 | * USBs |
| 613 | */ |
| 614 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { |
| 615 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { |
| 616 | FSL_IMX7_USBMISC1_ADDR, |
| 617 | FSL_IMX7_USBMISC2_ADDR, |
| 618 | FSL_IMX7_USBMISC3_ADDR, |
| 619 | }; |
| 620 | |
| 621 | static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = { |
| 622 | FSL_IMX7_USB1_ADDR, |
| 623 | FSL_IMX7_USB2_ADDR, |
| 624 | FSL_IMX7_USB3_ADDR, |
| 625 | }; |
| 626 | |
| 627 | static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = { |
| 628 | FSL_IMX7_USB1_IRQ, |
| 629 | FSL_IMX7_USB2_IRQ, |
| 630 | FSL_IMX7_USB3_IRQ, |
| 631 | }; |
| 632 | |
| 633 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); |
| 634 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, |
| 635 | FSL_IMX7_USBn_ADDR[i]); |
| 636 | |
| 637 | irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]); |
| 638 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); |
| 639 | |
| 640 | snprintf(name, NAME_SIZE, "usbmisc%d", i); |
| 641 | create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i], |
| 642 | FSL_IMX7_USBMISCn_SIZE); |
| 643 | } |
| 644 | |
| 645 | /* |
| 646 | * ADCs |
| 647 | */ |
| 648 | for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) { |
| 649 | static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = { |
| 650 | FSL_IMX7_ADC1_ADDR, |
| 651 | FSL_IMX7_ADC2_ADDR, |
| 652 | }; |
| 653 | |
| 654 | snprintf(name, NAME_SIZE, "adc%d", i); |
| 655 | create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i], |
| 656 | FSL_IMX7_ADCn_SIZE); |
| 657 | } |
| 658 | |
| 659 | /* |
| 660 | * LCD |
| 661 | */ |
| 662 | create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR, |
| 663 | FSL_IMX7_LCDIF_SIZE); |
| 664 | |
| 665 | /* |
| 666 | * DMA APBH |
| 667 | */ |
| 668 | create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR, |
| 669 | FSL_IMX7_DMA_APBH_SIZE); |
| 670 | /* |
| 671 | * PCIe PHY |
| 672 | */ |
| 673 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, |
| 674 | FSL_IMX7_PCIE_PHY_SIZE); |
| 675 | |
| 676 | /* |
| 677 | * CSU |
| 678 | */ |
| 679 | create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, |
| 680 | FSL_IMX7_CSU_SIZE); |
| 681 | |
| 682 | /* |
| 683 | * TZASC |
| 684 | */ |
| 685 | create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, |
| 686 | FSL_IMX7_TZASC_SIZE); |
| 687 | |
| 688 | /* |
| 689 | * OCRAM memory |
| 690 | */ |
| 691 | memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", |
| 692 | FSL_IMX7_OCRAM_MEM_SIZE, |
| 693 | &error_abort); |
| 694 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, |
| 695 | &s->ocram); |
| 696 | |
| 697 | /* |
| 698 | * OCRAM EPDC memory |
| 699 | */ |
| 700 | memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", |
| 701 | FSL_IMX7_OCRAM_EPDC_SIZE, |
| 702 | &error_abort); |
| 703 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, |
| 704 | &s->ocram_epdc); |
| 705 | |
| 706 | /* |
| 707 | * OCRAM PXP memory |
| 708 | */ |
| 709 | memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", |
| 710 | FSL_IMX7_OCRAM_PXP_SIZE, |
| 711 | &error_abort); |
| 712 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, |
| 713 | &s->ocram_pxp); |
| 714 | |
| 715 | /* |
| 716 | * OCRAM_S memory |
| 717 | */ |
| 718 | memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", |
| 719 | FSL_IMX7_OCRAM_S_SIZE, |
| 720 | &error_abort); |
| 721 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, |
| 722 | &s->ocram_s); |
| 723 | |
| 724 | /* |
| 725 | * ROM memory |
| 726 | */ |
| 727 | memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", |
| 728 | FSL_IMX7_ROM_SIZE, &error_abort); |
| 729 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, |
| 730 | &s->rom); |
| 731 | |
| 732 | /* |
| 733 | * CAAM memory |
| 734 | */ |
| 735 | memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", |
| 736 | FSL_IMX7_CAAM_MEM_SIZE, &error_abort); |
| 737 | memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, |
| 738 | &s->caam); |
| 739 | } |
| 740 | |
| 741 | static const Property fsl_imx7_properties[] = { |
| 742 | DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0), |
| 743 | DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1), |
| 744 | DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX7State, phy_connected[0], |
| 745 | true), |
| 746 | DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1], |
| 747 | true), |
| 748 | }; |
| 749 | |
| 750 | static void fsl_imx7_class_init(ObjectClass *oc, const void *data) |
| 751 | { |
| 752 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 753 | |
| 754 | device_class_set_props(dc, fsl_imx7_properties); |
| 755 | dc->realize = fsl_imx7_realize; |
| 756 | |
| 757 | /* Reason: Uses serial_hds and nd_table in realize() directly */ |
| 758 | dc->user_creatable = false; |
| 759 | dc->desc = "i.MX7 SOC"; |
| 760 | } |
| 761 | |
| 762 | static const TypeInfo fsl_imx7_type_info = { |
| 763 | .name = TYPE_FSL_IMX7, |
| 764 | .parent = TYPE_DEVICE, |
| 765 | .instance_size = sizeof(FslIMX7State), |
| 766 | .instance_init = fsl_imx7_init, |
| 767 | .class_init = fsl_imx7_class_init, |
| 768 | }; |
| 769 | |
| 770 | static void fsl_imx7_register_types(void) |
| 771 | { |
| 772 | type_register_static(&fsl_imx7_type_info); |
| 773 | } |
| 774 | type_init(fsl_imx7_register_types) |