@samitouri / QOSamiQemu
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1 /*
2 * i.MX 8M Plus SoC Implementation
3 *
4 * Based on hw/arm/fsl-imx6.c
5 *
6 * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "system/address-spaces.h"
13 #include "hw/arm/bsa.h"
14 #include "hw/arm/fsl-imx8mp.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/core/boards.h"
17 #include "system/kvm.h"
18 #include "system/system.h"
19 #include "target/arm/cpu.h"
20 #include "target/arm/cpu-qom.h"
21 #include "target/arm/kvm_arm.h"
22 #include "qapi/error.h"
23 #include "qobject/qlist.h"
24
25 static const struct {
26 hwaddr addr;
27 size_t size;
28 const char *name;
29 } fsl_imx8mp_memmap[] = {
30 [FSL_IMX8MP_RAM] = { FSL_IMX8MP_RAM_START, FSL_IMX8MP_RAM_SIZE_MAX, "ram" },
31 [FSL_IMX8MP_DDR_PHY_BROADCAST] = { 0x3dc00000, 4 * MiB, "ddr_phy_broadcast" },
32 [FSL_IMX8MP_DDR_PERF_MON] = { 0x3d800000, 4 * MiB, "ddr_perf_mon" },
33 [FSL_IMX8MP_DDR_CTL] = { 0x3d400000, 4 * MiB, "ddr_ctl" },
34 [FSL_IMX8MP_DDR_BLK_CTRL] = { 0x3d000000, 1 * MiB, "ddr_blk_ctrl" },
35 [FSL_IMX8MP_DDR_PHY] = { 0x3c000000, 16 * MiB, "ddr_phy" },
36 [FSL_IMX8MP_AUDIO_DSP] = { 0x3b000000, 16 * MiB, "audio_dsp" },
37 [FSL_IMX8MP_GIC_DIST] = { 0x38800000, 512 * KiB, "gic_dist" },
38 [FSL_IMX8MP_GIC_REDIST] = { 0x38880000, 512 * KiB, "gic_redist" },
39 [FSL_IMX8MP_NPU] = { 0x38500000, 2 * MiB, "npu" },
40 [FSL_IMX8MP_VPU] = { 0x38340000, 2 * MiB, "vpu" },
41 [FSL_IMX8MP_VPU_BLK_CTRL] = { 0x38330000, 2 * MiB, "vpu_blk_ctrl" },
42 [FSL_IMX8MP_VPU_VC8000E_ENCODER] = { 0x38320000, 2 * MiB, "vpu_vc8000e_encoder" },
43 [FSL_IMX8MP_VPU_G2_DECODER] = { 0x38310000, 2 * MiB, "vpu_g2_decoder" },
44 [FSL_IMX8MP_VPU_G1_DECODER] = { 0x38300000, 2 * MiB, "vpu_g1_decoder" },
45 [FSL_IMX8MP_USB2_GLUE] = { 0x382f0000, 0x100, "usb2_glue" },
46 [FSL_IMX8MP_USB2_OTG] = { 0x3820cc00, 0x100, "usb2_otg" },
47 [FSL_IMX8MP_USB2_DEV] = { 0x3820c700, 0x500, "usb2_dev" },
48 [FSL_IMX8MP_USB2] = { 0x38200000, 0xc700, "usb2" },
49 [FSL_IMX8MP_USB1_GLUE] = { 0x381f0000, 0x100, "usb1_glue" },
50 [FSL_IMX8MP_USB1_OTG] = { 0x3810cc00, 0x100, "usb1_otg" },
51 [FSL_IMX8MP_USB1_DEV] = { 0x3810c700, 0x500, "usb1_dev" },
52 [FSL_IMX8MP_USB1] = { 0x38100000, 0xc700, "usb1" },
53 [FSL_IMX8MP_GPU2D] = { 0x38008000, 32 * KiB, "gpu2d" },
54 [FSL_IMX8MP_GPU3D] = { 0x38000000, 32 * KiB, "gpu3d" },
55 [FSL_IMX8MP_QSPI1_RX_BUFFER] = { 0x34000000, 32 * MiB, "qspi1_rx_buffer" },
56 [FSL_IMX8MP_PCIE1] = { 0x33800000, 4 * MiB, "pcie1" },
57 [FSL_IMX8MP_QSPI1_TX_BUFFER] = { 0x33008000, 32 * KiB, "qspi1_tx_buffer" },
58 [FSL_IMX8MP_APBH_DMA] = { 0x33000000, 32 * KiB, "apbh_dma" },
59
60 /* AIPS-5 Begin */
61 [FSL_IMX8MP_MU_3_B] = { 0x30e90000, 64 * KiB, "mu_3_b" },
62 [FSL_IMX8MP_MU_3_A] = { 0x30e80000, 64 * KiB, "mu_3_a" },
63 [FSL_IMX8MP_MU_2_B] = { 0x30e70000, 64 * KiB, "mu_2_b" },
64 [FSL_IMX8MP_MU_2_A] = { 0x30e60000, 64 * KiB, "mu_2_a" },
65 [FSL_IMX8MP_EDMA_CHANNELS] = { 0x30e40000, 128 * KiB, "edma_channels" },
66 [FSL_IMX8MP_EDMA_MANAGEMENT_PAGE] = { 0x30e30000, 64 * KiB, "edma_management_page" },
67 [FSL_IMX8MP_AUDIO_BLK_CTRL] = { 0x30e20000, 64 * KiB, "audio_blk_ctrl" },
68 [FSL_IMX8MP_SDMA2] = { 0x30e10000, 64 * KiB, "sdma2" },
69 [FSL_IMX8MP_SDMA3] = { 0x30e00000, 64 * KiB, "sdma3" },
70 [FSL_IMX8MP_AIPS5_CONFIGURATION] = { 0x30df0000, 64 * KiB, "aips5_configuration" },
71 [FSL_IMX8MP_SPBA2] = { 0x30cf0000, 64 * KiB, "spba2" },
72 [FSL_IMX8MP_AUDIO_XCVR_RX] = { 0x30cc0000, 64 * KiB, "audio_xcvr_rx" },
73 [FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR] = { 0x30cb0000, 64 * KiB, "hdmi_tx_audlnk_mstr" },
74 [FSL_IMX8MP_PDM] = { 0x30ca0000, 64 * KiB, "pdm" },
75 [FSL_IMX8MP_ASRC] = { 0x30c90000, 64 * KiB, "asrc" },
76 [FSL_IMX8MP_SAI7] = { 0x30c80000, 64 * KiB, "sai7" },
77 [FSL_IMX8MP_SAI6] = { 0x30c60000, 64 * KiB, "sai6" },
78 [FSL_IMX8MP_SAI5] = { 0x30c50000, 64 * KiB, "sai5" },
79 [FSL_IMX8MP_SAI3] = { 0x30c30000, 64 * KiB, "sai3" },
80 [FSL_IMX8MP_SAI2] = { 0x30c20000, 64 * KiB, "sai2" },
81 [FSL_IMX8MP_SAI1] = { 0x30c10000, 64 * KiB, "sai1" },
82 /* AIPS-5 End */
83
84 /* AIPS-4 Begin */
85 [FSL_IMX8MP_HDMI_TX] = { 0x32fc0000, 128 * KiB, "hdmi_tx" },
86 [FSL_IMX8MP_TZASC] = { 0x32f80000, 64 * KiB, "tzasc" },
87 [FSL_IMX8MP_HSIO_BLK_CTL] = { 0x32f10000, 64 * KiB, "hsio_blk_ctl" },
88 [FSL_IMX8MP_PCIE_PHY1] = { 0x32f00000, 64 * KiB, "pcie_phy1" },
89 [FSL_IMX8MP_MEDIA_BLK_CTL] = { 0x32ec0000, 64 * KiB, "media_blk_ctl" },
90 [FSL_IMX8MP_LCDIF2] = { 0x32e90000, 64 * KiB, "lcdif2" },
91 [FSL_IMX8MP_LCDIF1] = { 0x32e80000, 64 * KiB, "lcdif1" },
92 [FSL_IMX8MP_MIPI_DSI1] = { 0x32e60000, 64 * KiB, "mipi_dsi1" },
93 [FSL_IMX8MP_MIPI_CSI2] = { 0x32e50000, 64 * KiB, "mipi_csi2" },
94 [FSL_IMX8MP_MIPI_CSI1] = { 0x32e40000, 64 * KiB, "mipi_csi1" },
95 [FSL_IMX8MP_IPS_DEWARP] = { 0x32e30000, 64 * KiB, "ips_dewarp" },
96 [FSL_IMX8MP_ISP2] = { 0x32e20000, 64 * KiB, "isp2" },
97 [FSL_IMX8MP_ISP1] = { 0x32e10000, 64 * KiB, "isp1" },
98 [FSL_IMX8MP_ISI] = { 0x32e00000, 64 * KiB, "isi" },
99 [FSL_IMX8MP_AIPS4_CONFIGURATION] = { 0x32df0000, 64 * KiB, "aips4_configuration" },
100 /* AIPS-4 End */
101
102 [FSL_IMX8MP_INTERCONNECT] = { 0x32700000, 1 * MiB, "interconnect" },
103
104 /* AIPS-3 Begin */
105 [FSL_IMX8MP_ENET2_TSN] = { 0x30bf0000, 64 * KiB, "enet2_tsn" },
106 [FSL_IMX8MP_ENET1] = { 0x30be0000, 64 * KiB, "enet1" },
107 [FSL_IMX8MP_SDMA1] = { 0x30bd0000, 64 * KiB, "sdma1" },
108 [FSL_IMX8MP_QSPI] = { 0x30bb0000, 64 * KiB, "qspi" },
109 [FSL_IMX8MP_USDHC3] = { 0x30b60000, 64 * KiB, "usdhc3" },
110 [FSL_IMX8MP_USDHC2] = { 0x30b50000, 64 * KiB, "usdhc2" },
111 [FSL_IMX8MP_USDHC1] = { 0x30b40000, 64 * KiB, "usdhc1" },
112 [FSL_IMX8MP_I2C6] = { 0x30ae0000, 64 * KiB, "i2c6" },
113 [FSL_IMX8MP_I2C5] = { 0x30ad0000, 64 * KiB, "i2c5" },
114 [FSL_IMX8MP_SEMAPHORE_HS] = { 0x30ac0000, 64 * KiB, "semaphore_hs" },
115 [FSL_IMX8MP_MU_1_B] = { 0x30ab0000, 64 * KiB, "mu_1_b" },
116 [FSL_IMX8MP_MU_1_A] = { 0x30aa0000, 64 * KiB, "mu_1_a" },
117 [FSL_IMX8MP_AUD_IRQ_STEER] = { 0x30a80000, 64 * KiB, "aud_irq_steer" },
118 [FSL_IMX8MP_UART4] = { 0x30a60000, 64 * KiB, "uart4" },
119 [FSL_IMX8MP_I2C4] = { 0x30a50000, 64 * KiB, "i2c4" },
120 [FSL_IMX8MP_I2C3] = { 0x30a40000, 64 * KiB, "i2c3" },
121 [FSL_IMX8MP_I2C2] = { 0x30a30000, 64 * KiB, "i2c2" },
122 [FSL_IMX8MP_I2C1] = { 0x30a20000, 64 * KiB, "i2c1" },
123 [FSL_IMX8MP_AIPS3_CONFIGURATION] = { 0x309f0000, 64 * KiB, "aips3_configuration" },
124 [FSL_IMX8MP_CAAM] = { 0x30900000, 256 * KiB, "caam" },
125 [FSL_IMX8MP_SPBA1] = { 0x308f0000, 64 * KiB, "spba1" },
126 [FSL_IMX8MP_FLEXCAN2] = { 0x308d0000, 64 * KiB, "flexcan2" },
127 [FSL_IMX8MP_FLEXCAN1] = { 0x308c0000, 64 * KiB, "flexcan1" },
128 [FSL_IMX8MP_UART2] = { 0x30890000, 64 * KiB, "uart2" },
129 [FSL_IMX8MP_UART3] = { 0x30880000, 64 * KiB, "uart3" },
130 [FSL_IMX8MP_UART1] = { 0x30860000, 64 * KiB, "uart1" },
131 [FSL_IMX8MP_ECSPI3] = { 0x30840000, 64 * KiB, "ecspi3" },
132 [FSL_IMX8MP_ECSPI2] = { 0x30830000, 64 * KiB, "ecspi2" },
133 [FSL_IMX8MP_ECSPI1] = { 0x30820000, 64 * KiB, "ecspi1" },
134 /* AIPS-3 End */
135
136 /* AIPS-2 Begin */
137 [FSL_IMX8MP_QOSC] = { 0x307f0000, 64 * KiB, "qosc" },
138 [FSL_IMX8MP_PERFMON2] = { 0x307d0000, 64 * KiB, "perfmon2" },
139 [FSL_IMX8MP_PERFMON1] = { 0x307c0000, 64 * KiB, "perfmon1" },
140 [FSL_IMX8MP_GPT4] = { 0x30700000, 64 * KiB, "gpt4" },
141 [FSL_IMX8MP_GPT5] = { 0x306f0000, 64 * KiB, "gpt5" },
142 [FSL_IMX8MP_GPT6] = { 0x306e0000, 64 * KiB, "gpt6" },
143 [FSL_IMX8MP_SYSCNT_CTRL] = { 0x306c0000, 64 * KiB, "syscnt_ctrl" },
144 [FSL_IMX8MP_SYSCNT_CMP] = { 0x306b0000, 64 * KiB, "syscnt_cmp" },
145 [FSL_IMX8MP_SYSCNT_RD] = { 0x306a0000, 64 * KiB, "syscnt_rd" },
146 [FSL_IMX8MP_PWM4] = { 0x30690000, 64 * KiB, "pwm4" },
147 [FSL_IMX8MP_PWM3] = { 0x30680000, 64 * KiB, "pwm3" },
148 [FSL_IMX8MP_PWM2] = { 0x30670000, 64 * KiB, "pwm2" },
149 [FSL_IMX8MP_PWM1] = { 0x30660000, 64 * KiB, "pwm1" },
150 [FSL_IMX8MP_AIPS2_CONFIGURATION] = { 0x305f0000, 64 * KiB, "aips2_configuration" },
151 /* AIPS-2 End */
152
153 /* AIPS-1 Begin */
154 [FSL_IMX8MP_CSU] = { 0x303e0000, 64 * KiB, "csu" },
155 [FSL_IMX8MP_RDC] = { 0x303d0000, 64 * KiB, "rdc" },
156 [FSL_IMX8MP_SEMAPHORE2] = { 0x303c0000, 64 * KiB, "semaphore2" },
157 [FSL_IMX8MP_SEMAPHORE1] = { 0x303b0000, 64 * KiB, "semaphore1" },
158 [FSL_IMX8MP_GPC] = { 0x303a0000, 64 * KiB, "gpc" },
159 [FSL_IMX8MP_SRC] = { 0x30390000, 64 * KiB, "src" },
160 [FSL_IMX8MP_CCM] = { 0x30380000, 64 * KiB, "ccm" },
161 [FSL_IMX8MP_SNVS_HP] = { 0x30370000, 64 * KiB, "snvs_hp" },
162 [FSL_IMX8MP_ANA_PLL] = { 0x30360000, 64 * KiB, "ana_pll" },
163 [FSL_IMX8MP_OCOTP_CTRL] = { 0x30350000, 64 * KiB, "ocotp_ctrl" },
164 [FSL_IMX8MP_IOMUXC_GPR] = { 0x30340000, 64 * KiB, "iomuxc_gpr" },
165 [FSL_IMX8MP_IOMUXC] = { 0x30330000, 64 * KiB, "iomuxc" },
166 [FSL_IMX8MP_GPT3] = { 0x302f0000, 64 * KiB, "gpt3" },
167 [FSL_IMX8MP_GPT2] = { 0x302e0000, 64 * KiB, "gpt2" },
168 [FSL_IMX8MP_GPT1] = { 0x302d0000, 64 * KiB, "gpt1" },
169 [FSL_IMX8MP_WDOG3] = { 0x302a0000, 64 * KiB, "wdog3" },
170 [FSL_IMX8MP_WDOG2] = { 0x30290000, 64 * KiB, "wdog2" },
171 [FSL_IMX8MP_WDOG1] = { 0x30280000, 64 * KiB, "wdog1" },
172 [FSL_IMX8MP_ANA_OSC] = { 0x30270000, 64 * KiB, "ana_osc" },
173 [FSL_IMX8MP_ANA_TSENSOR] = { 0x30260000, 64 * KiB, "ana_tsensor" },
174 [FSL_IMX8MP_GPIO5] = { 0x30240000, 64 * KiB, "gpio5" },
175 [FSL_IMX8MP_GPIO4] = { 0x30230000, 64 * KiB, "gpio4" },
176 [FSL_IMX8MP_GPIO3] = { 0x30220000, 64 * KiB, "gpio3" },
177 [FSL_IMX8MP_GPIO2] = { 0x30210000, 64 * KiB, "gpio2" },
178 [FSL_IMX8MP_GPIO1] = { 0x30200000, 64 * KiB, "gpio1" },
179 [FSL_IMX8MP_AIPS1_CONFIGURATION] = { 0x301f0000, 64 * KiB, "aips1_configuration" },
180 /* AIPS-1 End */
181
182 [FSL_IMX8MP_A53_DAP] = { 0x28000000, 16 * MiB, "a53_dap" },
183 [FSL_IMX8MP_PCIE1_MEM] = { 0x18000000, 128 * MiB, "pcie1_mem" },
184 [FSL_IMX8MP_QSPI_MEM] = { 0x08000000, 256 * MiB, "qspi_mem" },
185 [FSL_IMX8MP_OCRAM] = { 0x00900000, 576 * KiB, "ocram" },
186 [FSL_IMX8MP_TCM_DTCM] = { 0x00800000, 128 * KiB, "tcm_dtcm" },
187 [FSL_IMX8MP_TCM_ITCM] = { 0x007e0000, 128 * KiB, "tcm_itcm" },
188 [FSL_IMX8MP_OCRAM_S] = { 0x00180000, 36 * KiB, "ocram_s" },
189 [FSL_IMX8MP_CAAM_MEM] = { 0x00100000, 32 * KiB, "caam_mem" },
190 [FSL_IMX8MP_BOOT_ROM_PROTECTED] = { 0x0003f000, 4 * KiB, "boot_rom_protected" },
191 [FSL_IMX8MP_BOOT_ROM] = { 0x00000000, 252 * KiB, "boot_rom" },
192 };
193
194 static void fsl_imx8mp_init(Object *obj)
195 {
196 FslImx8mpState *s = FSL_IMX8MP(obj);
197 int i;
198
199 object_initialize_child(obj, "gic", &s->gic, gicv3_class_name());
200
201 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM);
202
203 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG);
204
205 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
206
207 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
208 g_autofree char *name = g_strdup_printf("uart%d", i + 1);
209 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
210 }
211
212 for (i = 0; i < FSL_IMX8MP_NUM_GPTS; i++) {
213 g_autofree char *name = g_strdup_printf("gpt%d", i + 1);
214 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MP_GPT);
215 }
216 object_initialize_child(obj, "gpt5-gpt6-irq", &s->gpt5_gpt6_irq,
217 TYPE_OR_IRQ);
218
219 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
220 g_autofree char *name = g_strdup_printf("i2c%d", i + 1);
221 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
222 }
223
224 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
225 g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
226 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
227 }
228
229 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
230 g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
231 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
232 }
233
234 for (i = 0; i < FSL_IMX8MP_NUM_USBS; i++) {
235 g_autofree char *name = g_strdup_printf("usb%d", i);
236 object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3);
237 }
238
239 for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
240 g_autofree char *name = g_strdup_printf("spi%d", i + 1);
241 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
242 }
243
244 for (i = 0; i < FSL_IMX8MP_NUM_WDTS; i++) {
245 g_autofree char *name = g_strdup_printf("wdt%d", i);
246 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
247 }
248
249 for (i = 0; i < FSL_IMX8MP_NUM_CANS; i++) {
250 g_autofree char *name = g_strdup_printf("flexcan%d", i);
251 object_initialize_child(obj, name, &s->flexcan[i], TYPE_CAN_FLEXCAN3);
252 }
253
254 object_initialize_child(obj, "eth0", &s->enet, TYPE_IMX_ENET);
255
256 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
257 object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
258 TYPE_FSL_IMX8M_PCIE_PHY);
259 }
260
261 static void fsl_imx8mp_realize(DeviceState *dev, Error **errp)
262 {
263 MachineState *ms = MACHINE(qdev_get_machine());
264 FslImx8mpState *s = FSL_IMX8MP(dev);
265 DeviceState *gicdev = DEVICE(&s->gic);
266 const char *cpu_type = ms->cpu_type ?: ARM_CPU_TYPE_NAME("cortex-a53");
267 int i;
268
269 if (ms->smp.cpus > FSL_IMX8MP_NUM_CPUS) {
270 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
271 TYPE_FSL_IMX8MP, FSL_IMX8MP_NUM_CPUS, ms->smp.cpus);
272 return;
273 }
274
275 for (i = 0; i < ms->smp.cpus; i++) {
276 g_autofree char *name = g_strdup_printf("cpu%d", i);
277 object_initialize_child(OBJECT(dev), name, &s->cpu[i], cpu_type);
278 }
279
280 /* CPUs */
281 for (i = 0; i < ms->smp.cpus; i++) {
282 /* On uniprocessor, the CBAR is set to 0 */
283 if (ms->smp.cpus > 1 &&
284 object_property_find(OBJECT(&s->cpu[i]), "reset-cbar")) {
285 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
286 fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr,
287 &error_abort);
288 }
289
290 /*
291 * CNTFID0 base frequency in Hz of system counter
292 */
293 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000,
294 &error_abort);
295
296 if (object_property_find(OBJECT(&s->cpu[i]), "has_el2")) {
297 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el2",
298 !kvm_enabled(), &error_abort);
299 }
300
301 if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) {
302 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3",
303 !kvm_enabled(), &error_abort);
304 }
305
306 if (i) {
307 /*
308 * Secondary CPUs start in powered-down state (and can be
309 * powered up via the SRC system reset controller)
310 */
311 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
312 true, &error_abort);
313 }
314
315 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
316 return;
317 }
318 }
319
320 /* GIC */
321 {
322 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&s->gic);
323 QList *redist_region_count;
324 bool pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
325
326 qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus);
327 qdev_prop_set_uint32(gicdev, "num-irq",
328 FSL_IMX8MP_NUM_IRQS + GIC_INTERNAL);
329 redist_region_count = qlist_new();
330 qlist_append_int(redist_region_count, ms->smp.cpus);
331 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
332 object_property_set_link(OBJECT(&s->gic), "sysmem",
333 OBJECT(get_system_memory()), &error_fatal);
334 if (!sysbus_realize(gicsbd, errp)) {
335 return;
336 }
337 sysbus_mmio_map(gicsbd, 0, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_DIST].addr);
338 sysbus_mmio_map(gicsbd, 1, fsl_imx8mp_memmap[FSL_IMX8MP_GIC_REDIST].addr);
339
340 /*
341 * Wire the outputs from each CPU's generic timer and the GICv3
342 * maintenance interrupt signal to the appropriate GIC PPI inputs, and
343 * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.
344 */
345 for (i = 0; i < ms->smp.cpus; i++) {
346 DeviceState *cpudev = DEVICE(&s->cpu[i]);
347 int intidbase = FSL_IMX8MP_NUM_IRQS + i * GIC_INTERNAL;
348 qemu_irq irq;
349
350 /*
351 * Mapping from the output timer irq lines from the CPU to the
352 * GIC PPI inputs.
353 */
354 static const int timer_irqs[] = {
355 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
356 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
357 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
358 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
359 };
360
361 for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {
362 irq = qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]);
363 qdev_connect_gpio_out(cpudev, j, irq);
364 }
365
366 irq = qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IRQ);
367 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
368 0, irq);
369
370 irq = qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ);
371 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq);
372
373 sysbus_connect_irq(gicsbd, i,
374 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
375 sysbus_connect_irq(gicsbd, i + ms->smp.cpus,
376 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
377 sysbus_connect_irq(gicsbd, i + 2 * ms->smp.cpus,
378 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
379 sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus,
380 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
381
382 if (kvm_enabled()) {
383 if (pmu) {
384 assert(arm_feature(&s->cpu[i].env, ARM_FEATURE_PMU));
385 if (kvm_irqchip_in_kernel()) {
386 kvm_arm_pmu_set_irq(&s->cpu[i], VIRTUAL_PMU_IRQ);
387 }
388 kvm_arm_pmu_init(&s->cpu[i]);
389 }
390 }
391 }
392 }
393
394 /* CCM */
395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
396 return;
397 }
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0,
399 fsl_imx8mp_memmap[FSL_IMX8MP_CCM].addr);
400
401 /* Analog */
402 if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) {
403 return;
404 }
405 sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0,
406 fsl_imx8mp_memmap[FSL_IMX8MP_ANA_PLL].addr);
407
408 /* UARTs */
409 for (i = 0; i < FSL_IMX8MP_NUM_UARTS; i++) {
410 struct {
411 hwaddr addr;
412 unsigned int irq;
413 } serial_table[FSL_IMX8MP_NUM_UARTS] = {
414 { fsl_imx8mp_memmap[FSL_IMX8MP_UART1].addr, FSL_IMX8MP_UART1_IRQ },
415 { fsl_imx8mp_memmap[FSL_IMX8MP_UART2].addr, FSL_IMX8MP_UART2_IRQ },
416 { fsl_imx8mp_memmap[FSL_IMX8MP_UART3].addr, FSL_IMX8MP_UART3_IRQ },
417 { fsl_imx8mp_memmap[FSL_IMX8MP_UART4].addr, FSL_IMX8MP_UART4_IRQ },
418 };
419
420 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
421 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
422 return;
423 }
424
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
427 qdev_get_gpio_in(gicdev, serial_table[i].irq));
428 }
429
430 /* GPTs */
431 object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), "num-lines", 2,
432 &error_abort);
433 if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) {
434 return;
435 }
436
437 qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0,
438 qdev_get_gpio_in(gicdev, FSL_IMX8MP_GPT5_GPT6_IRQ));
439
440 for (i = 0; i < FSL_IMX8MP_NUM_GPTS; i++) {
441 hwaddr gpt_addrs[FSL_IMX8MP_NUM_GPTS] = {
442 fsl_imx8mp_memmap[FSL_IMX8MP_GPT1].addr,
443 fsl_imx8mp_memmap[FSL_IMX8MP_GPT2].addr,
444 fsl_imx8mp_memmap[FSL_IMX8MP_GPT3].addr,
445 fsl_imx8mp_memmap[FSL_IMX8MP_GPT4].addr,
446 fsl_imx8mp_memmap[FSL_IMX8MP_GPT5].addr,
447 fsl_imx8mp_memmap[FSL_IMX8MP_GPT6].addr,
448 };
449
450 s->gpt[i].ccm = IMX_CCM(&s->ccm);
451
452 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) {
453 return;
454 }
455
456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]);
457
458 if (i < FSL_IMX8MP_NUM_GPTS - 2) {
459 static const unsigned int gpt_irqs[FSL_IMX8MP_NUM_GPTS - 2] = {
460 FSL_IMX8MP_GPT1_IRQ,
461 FSL_IMX8MP_GPT2_IRQ,
462 FSL_IMX8MP_GPT3_IRQ,
463 FSL_IMX8MP_GPT4_IRQ,
464 };
465
466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
467 qdev_get_gpio_in(gicdev, gpt_irqs[i]));
468 } else {
469 int irq = i - FSL_IMX8MP_NUM_GPTS + 2;
470
471 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
472 qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq), irq));
473 }
474 }
475
476 /* I2Cs */
477 for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) {
478 struct {
479 hwaddr addr;
480 unsigned int irq;
481 } i2c_table[FSL_IMX8MP_NUM_I2CS] = {
482 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ },
483 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ },
484 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ },
485 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ },
486 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ },
487 { fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ },
488 };
489
490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) {
491 return;
492 }
493
494 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
495 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
496 qdev_get_gpio_in(gicdev, i2c_table[i].irq));
497 }
498
499 /* GPIOs */
500 for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) {
501 struct {
502 hwaddr addr;
503 unsigned int irq_low;
504 unsigned int irq_high;
505 } gpio_table[FSL_IMX8MP_NUM_GPIOS] = {
506 {
507 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO1].addr,
508 FSL_IMX8MP_GPIO1_LOW_IRQ,
509 FSL_IMX8MP_GPIO1_HIGH_IRQ
510 },
511 {
512 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO2].addr,
513 FSL_IMX8MP_GPIO2_LOW_IRQ,
514 FSL_IMX8MP_GPIO2_HIGH_IRQ
515 },
516 {
517 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO3].addr,
518 FSL_IMX8MP_GPIO3_LOW_IRQ,
519 FSL_IMX8MP_GPIO3_HIGH_IRQ
520 },
521 {
522 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO4].addr,
523 FSL_IMX8MP_GPIO4_LOW_IRQ,
524 FSL_IMX8MP_GPIO4_HIGH_IRQ
525 },
526 {
527 fsl_imx8mp_memmap[FSL_IMX8MP_GPIO5].addr,
528 FSL_IMX8MP_GPIO5_LOW_IRQ,
529 FSL_IMX8MP_GPIO5_HIGH_IRQ
530 },
531 };
532
533 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
534 &error_abort);
535 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
536 true, &error_abort);
537 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
538 return;
539 }
540
541 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
542 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
543 qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
544 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
545 qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
546 }
547
548 /* USDHCs */
549 for (i = 0; i < FSL_IMX8MP_NUM_USDHCS; i++) {
550 struct {
551 hwaddr addr;
552 unsigned int irq;
553 } usdhc_table[FSL_IMX8MP_NUM_USDHCS] = {
554 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC1].addr, FSL_IMX8MP_USDHC1_IRQ },
555 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC2].addr, FSL_IMX8MP_USDHC2_IRQ },
556 { fsl_imx8mp_memmap[FSL_IMX8MP_USDHC3].addr, FSL_IMX8MP_USDHC3_IRQ },
557 };
558
559 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) {
560 return;
561 }
562
563 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].addr);
564 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
565 qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
566 }
567
568 /* USBs */
569 for (i = 0; i < FSL_IMX8MP_NUM_USBS; i++) {
570 struct {
571 hwaddr addr;
572 unsigned int irq;
573 } usb_table[FSL_IMX8MP_NUM_USBS] = {
574 { fsl_imx8mp_memmap[FSL_IMX8MP_USB1].addr, FSL_IMX8MP_USB1_IRQ },
575 { fsl_imx8mp_memmap[FSL_IMX8MP_USB2].addr, FSL_IMX8MP_USB2_IRQ },
576 };
577
578 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p2", 1);
579 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p3", 1);
580 qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
581 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
582 return;
583 }
584 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
585 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
586 qdev_get_gpio_in(gicdev, usb_table[i].irq));
587 }
588
589 /* ECSPIs */
590 for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
591 struct {
592 hwaddr addr;
593 unsigned int irq;
594 } spi_table[FSL_IMX8MP_NUM_ECSPIS] = {
595 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI1].addr, FSL_IMX8MP_ECSPI1_IRQ },
596 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI2].addr, FSL_IMX8MP_ECSPI2_IRQ },
597 { fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI3].addr, FSL_IMX8MP_ECSPI3_IRQ },
598 };
599
600 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
601 return;
602 }
603
604 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
606 qdev_get_gpio_in(gicdev, spi_table[i].irq));
607 }
608
609 /* ENET1 */
610 object_property_set_uint(OBJECT(&s->enet), "phy-num", s->phy_num,
611 &error_abort);
612 object_property_set_uint(OBJECT(&s->enet), "tx-ring-num", 3, &error_abort);
613 qemu_configure_nic_device(DEVICE(&s->enet), true, NULL);
614 if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) {
615 return;
616 }
617 sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0,
618 fsl_imx8mp_memmap[FSL_IMX8MP_ENET1].addr);
619 sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0,
620 qdev_get_gpio_in(gicdev, FSL_IMX8MP_ENET1_MAC_IRQ));
621 sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1,
622 qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IRQ));
623
624 /* SNVS */
625 if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
626 return;
627 }
628 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
629 fsl_imx8mp_memmap[FSL_IMX8MP_SNVS_HP].addr);
630
631 /* Watchdogs */
632 for (i = 0; i < FSL_IMX8MP_NUM_WDTS; i++) {
633 struct {
634 hwaddr addr;
635 unsigned int irq;
636 } wdog_table[FSL_IMX8MP_NUM_WDTS] = {
637 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG1].addr, FSL_IMX8MP_WDOG1_IRQ },
638 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG2].addr, FSL_IMX8MP_WDOG2_IRQ },
639 { fsl_imx8mp_memmap[FSL_IMX8MP_WDOG3].addr, FSL_IMX8MP_WDOG3_IRQ },
640 };
641
642 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
643 true, &error_abort);
644 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
645 return;
646 }
647
648 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr);
649 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
650 qdev_get_gpio_in(gicdev, wdog_table[i].irq));
651 }
652
653 /* PCIe */
654 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
655 return;
656 }
657 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
658 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE1].addr);
659
660 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
661 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTA_IRQ));
662 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
663 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTB_IRQ));
664 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
665 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTC_IRQ));
666 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
667 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_INTD_IRQ));
668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
669 qdev_get_gpio_in(gicdev, FSL_IMX8MP_PCI_MSI_IRQ));
670
671 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
672 return;
673 }
674 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
675 fsl_imx8mp_memmap[FSL_IMX8MP_PCIE_PHY1].addr);
676
677 /* FlexCANs */
678 for (i = 0; i < FSL_IMX8MP_NUM_CANS; i++) {
679 static const struct {
680 hwaddr addr;
681 unsigned int irq;
682 } flexcan_table[FSL_IMX8MP_NUM_CANS] = {
683 {
684 fsl_imx8mp_memmap[FSL_IMX8MP_FLEXCAN1].addr,
685 FSL_IMX8MP_FLEXCAN1_IRQ
686 }, {
687 fsl_imx8mp_memmap[FSL_IMX8MP_FLEXCAN2].addr,
688 FSL_IMX8MP_FLEXCAN2_IRQ
689 },
690 };
691
692 object_property_set_link(OBJECT(&s->flexcan[i]), "clock-control-module",
693 OBJECT(&s->ccm), &error_abort);
694 object_property_set_link(OBJECT(&s->flexcan[i]), "canbus",
695 OBJECT(s->canbus[i]), &error_abort);
696
697 sysbus_realize(SYS_BUS_DEVICE(&s->flexcan[i]), &error_abort);
698
699 sysbus_mmio_map(SYS_BUS_DEVICE(&s->flexcan[i]), 0,
700 flexcan_table[i].addr);
701 sysbus_connect_irq(SYS_BUS_DEVICE(&s->flexcan[i]), 0,
702 qdev_get_gpio_in(gicdev, flexcan_table[i].irq));
703 }
704
705 /* On-Chip RAM */
706 if (!memory_region_init_ram(&s->ocram, OBJECT(dev), "imx8mp.ocram",
707 fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].size,
708 errp)) {
709 return;
710 }
711 memory_region_add_subregion(get_system_memory(),
712 fsl_imx8mp_memmap[FSL_IMX8MP_OCRAM].addr,
713 &s->ocram);
714
715 /* Unimplemented devices */
716 for (i = 0; i < ARRAY_SIZE(fsl_imx8mp_memmap); i++) {
717 switch (i) {
718 case FSL_IMX8MP_ANA_PLL:
719 case FSL_IMX8MP_CCM:
720 case FSL_IMX8MP_FLEXCAN1 ... FSL_IMX8MP_FLEXCAN2:
721 case FSL_IMX8MP_GIC_DIST:
722 case FSL_IMX8MP_GIC_REDIST:
723 case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
724 case FSL_IMX8MP_GPT1 ... FSL_IMX8MP_GPT6:
725 case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3:
726 case FSL_IMX8MP_ENET1:
727 case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6:
728 case FSL_IMX8MP_OCRAM:
729 case FSL_IMX8MP_PCIE1:
730 case FSL_IMX8MP_PCIE_PHY1:
731 case FSL_IMX8MP_RAM:
732 case FSL_IMX8MP_SNVS_HP:
733 case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4:
734 case FSL_IMX8MP_USB1 ... FSL_IMX8MP_USB2:
735 case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3:
736 case FSL_IMX8MP_WDOG1 ... FSL_IMX8MP_WDOG3:
737 /* device implemented and treated above */
738 break;
739
740 default:
741 create_unimplemented_device(fsl_imx8mp_memmap[i].name,
742 fsl_imx8mp_memmap[i].addr,
743 fsl_imx8mp_memmap[i].size);
744 break;
745 }
746 }
747 }
748
749 static const Property fsl_imx8mp_properties[] = {
750 DEFINE_PROP_UINT32("fec1-phy-num", FslImx8mpState, phy_num, 0),
751 DEFINE_PROP_BOOL("fec1-phy-connected", FslImx8mpState, phy_connected, true),
752 DEFINE_PROP_LINK("canbus0", FslImx8mpState, canbus[0], TYPE_CAN_BUS,
753 CanBusState *),
754 DEFINE_PROP_LINK("canbus1", FslImx8mpState, canbus[1], TYPE_CAN_BUS,
755 CanBusState *),
756 };
757
758 static void fsl_imx8mp_class_init(ObjectClass *oc, const void *data)
759 {
760 DeviceClass *dc = DEVICE_CLASS(oc);
761
762 device_class_set_props(dc, fsl_imx8mp_properties);
763 dc->realize = fsl_imx8mp_realize;
764
765 dc->desc = "i.MX 8M Plus SoC";
766 }
767
768 static const TypeInfo fsl_imx8mp_types[] = {
769 {
770 .name = TYPE_FSL_IMX8MP,
771 .parent = TYPE_SYS_BUS_DEVICE,
772 .instance_size = sizeof(FslImx8mpState),
773 .instance_init = fsl_imx8mp_init,
774 .class_init = fsl_imx8mp_class_init,
775 },
776 };
777
778 DEFINE_TYPES(fsl_imx8mp_types)