| 1 | /* |
| 2 | * ARM Integrator CP System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2005-2007 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This code is licensed under the GPL |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qapi/error.h" |
| 12 | #include "hw/core/sysbus.h" |
| 13 | #include "migration/vmstate.h" |
| 14 | #include "hw/core/boards.h" |
| 15 | #include "hw/arm/boot.h" |
| 16 | #include "hw/arm/machines-qom.h" |
| 17 | #include "hw/misc/arm_integrator_debug.h" |
| 18 | #include "hw/net/smc91c111.h" |
| 19 | #include "net/net.h" |
| 20 | #include "system/address-spaces.h" |
| 21 | #include "system/runstate.h" |
| 22 | #include "system/system.h" |
| 23 | #include "qemu/log.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "hw/char/pl011.h" |
| 26 | #include "hw/core/irq.h" |
| 27 | #include "hw/sd/sd.h" |
| 28 | #include "qom/object.h" |
| 29 | #include "target/arm/cpu-qom.h" |
| 30 | |
| 31 | #define TYPE_INTEGRATOR_CM "integrator_core" |
| 32 | OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM) |
| 33 | |
| 34 | struct IntegratorCMState { |
| 35 | /*< private >*/ |
| 36 | SysBusDevice parent_obj; |
| 37 | /*< public >*/ |
| 38 | |
| 39 | MemoryRegion iomem; |
| 40 | uint32_t memsz; |
| 41 | MemoryRegion flash; |
| 42 | uint32_t cm_osc; |
| 43 | uint32_t cm_ctrl; |
| 44 | uint32_t cm_lock; |
| 45 | uint32_t cm_auxosc; |
| 46 | uint32_t cm_sdram; |
| 47 | uint32_t cm_init; |
| 48 | uint32_t cm_flags; |
| 49 | uint32_t cm_nvflags; |
| 50 | uint32_t cm_refcnt_offset; |
| 51 | uint32_t int_level; |
| 52 | uint32_t irq_enabled; |
| 53 | uint32_t fiq_enabled; |
| 54 | }; |
| 55 | |
| 56 | static uint8_t integrator_spd[128] = { |
| 57 | 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, |
| 58 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
| 59 | }; |
| 60 | |
| 61 | static const VMStateDescription vmstate_integratorcm = { |
| 62 | .name = "integratorcm", |
| 63 | .version_id = 1, |
| 64 | .minimum_version_id = 1, |
| 65 | .fields = (const VMStateField[]) { |
| 66 | VMSTATE_UINT32(cm_osc, IntegratorCMState), |
| 67 | VMSTATE_UINT32(cm_ctrl, IntegratorCMState), |
| 68 | VMSTATE_UINT32(cm_lock, IntegratorCMState), |
| 69 | VMSTATE_UINT32(cm_auxosc, IntegratorCMState), |
| 70 | VMSTATE_UINT32(cm_sdram, IntegratorCMState), |
| 71 | VMSTATE_UINT32(cm_init, IntegratorCMState), |
| 72 | VMSTATE_UINT32(cm_flags, IntegratorCMState), |
| 73 | VMSTATE_UINT32(cm_nvflags, IntegratorCMState), |
| 74 | VMSTATE_UINT32(int_level, IntegratorCMState), |
| 75 | VMSTATE_UINT32(irq_enabled, IntegratorCMState), |
| 76 | VMSTATE_UINT32(fiq_enabled, IntegratorCMState), |
| 77 | VMSTATE_END_OF_LIST() |
| 78 | } |
| 79 | }; |
| 80 | |
| 81 | static uint64_t integratorcm_read(void *opaque, hwaddr offset, |
| 82 | unsigned size) |
| 83 | { |
| 84 | IntegratorCMState *s = opaque; |
| 85 | if (offset >= 0x100 && offset < 0x200) { |
| 86 | /* CM_SPD */ |
| 87 | if (offset >= 0x180) |
| 88 | return 0; |
| 89 | return integrator_spd[offset >> 2]; |
| 90 | } |
| 91 | switch (offset >> 2) { |
| 92 | case 0: /* CM_ID */ |
| 93 | return 0x411a3001; |
| 94 | case 1: /* CM_PROC */ |
| 95 | return 0; |
| 96 | case 2: /* CM_OSC */ |
| 97 | return s->cm_osc; |
| 98 | case 3: /* CM_CTRL */ |
| 99 | return s->cm_ctrl; |
| 100 | case 4: /* CM_STAT */ |
| 101 | return 0x00100000; |
| 102 | case 5: /* CM_LOCK */ |
| 103 | if (s->cm_lock == 0xa05f) { |
| 104 | return 0x1a05f; |
| 105 | } else { |
| 106 | return s->cm_lock; |
| 107 | } |
| 108 | case 7: /* CM_AUXOSC */ |
| 109 | return s->cm_auxosc; |
| 110 | case 8: /* CM_SDRAM */ |
| 111 | return s->cm_sdram; |
| 112 | case 9: /* CM_INIT */ |
| 113 | return s->cm_init; |
| 114 | case 10: /* CM_REFCNT */ |
| 115 | /* This register, CM_REFCNT, provides a 32-bit count value. |
| 116 | * The count increments at the fixed reference clock frequency of 24MHz |
| 117 | * and can be used as a real-time counter. |
| 118 | */ |
| 119 | return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, |
| 120 | 1000) - s->cm_refcnt_offset; |
| 121 | case 12: /* CM_FLAGS */ |
| 122 | return s->cm_flags; |
| 123 | case 14: /* CM_NVFLAGS */ |
| 124 | return s->cm_nvflags; |
| 125 | case 16: /* CM_IRQ_STAT */ |
| 126 | return s->int_level & s->irq_enabled; |
| 127 | case 17: /* CM_IRQ_RSTAT */ |
| 128 | return s->int_level; |
| 129 | case 18: /* CM_IRQ_ENSET */ |
| 130 | return s->irq_enabled; |
| 131 | case 20: /* CM_SOFT_INTSET */ |
| 132 | return s->int_level & 1; |
| 133 | case 24: /* CM_FIQ_STAT */ |
| 134 | return s->int_level & s->fiq_enabled; |
| 135 | case 25: /* CM_FIQ_RSTAT */ |
| 136 | return s->int_level; |
| 137 | case 26: /* CM_FIQ_ENSET */ |
| 138 | return s->fiq_enabled; |
| 139 | case 32: /* CM_VOLTAGE_CTL0 */ |
| 140 | case 33: /* CM_VOLTAGE_CTL1 */ |
| 141 | case 34: /* CM_VOLTAGE_CTL2 */ |
| 142 | case 35: /* CM_VOLTAGE_CTL3 */ |
| 143 | /* ??? Voltage control unimplemented. */ |
| 144 | return 0; |
| 145 | default: |
| 146 | qemu_log_mask(LOG_UNIMP, |
| 147 | "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", |
| 148 | __func__, offset); |
| 149 | return 0; |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | static void integratorcm_do_remap(IntegratorCMState *s) |
| 154 | { |
| 155 | /* Sync memory region state with CM_CTRL REMAP bit: |
| 156 | * bit 0 => flash at address 0; bit 1 => RAM |
| 157 | */ |
| 158 | memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); |
| 159 | } |
| 160 | |
| 161 | static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) |
| 162 | { |
| 163 | if (value & 8) { |
| 164 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 165 | } |
| 166 | if ((s->cm_ctrl ^ value) & 1) { |
| 167 | /* (value & 1) != 0 means the green "MISC LED" is lit. |
| 168 | * We don't have any nice place to display LEDs. printf is a bad |
| 169 | * idea because Linux uses the LED as a heartbeat and the output |
| 170 | * will swamp anything else on the terminal. |
| 171 | */ |
| 172 | } |
| 173 | /* Note that the RESET bit [3] always reads as zero */ |
| 174 | s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); |
| 175 | integratorcm_do_remap(s); |
| 176 | } |
| 177 | |
| 178 | static void integratorcm_update(IntegratorCMState *s) |
| 179 | { |
| 180 | /* |
| 181 | * ??? The CPU irq/fiq is raised when either the core module or base PIC |
| 182 | * are active. To implement this we would need to run these signals |
| 183 | * through an OR gate with the PIC outputs. In practice guests don't |
| 184 | * use this, which is intended for an external debugger. |
| 185 | */ |
| 186 | if (s->int_level & (s->irq_enabled | s->fiq_enabled)) { |
| 187 | qemu_log_mask(LOG_UNIMP, |
| 188 | "%s: raising IRQ/FIQ via core module registers is not implemented\n", |
| 189 | __func__); |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | static void integratorcm_write(void *opaque, hwaddr offset, |
| 194 | uint64_t value, unsigned size) |
| 195 | { |
| 196 | IntegratorCMState *s = opaque; |
| 197 | switch (offset >> 2) { |
| 198 | case 2: /* CM_OSC */ |
| 199 | if (s->cm_lock == 0xa05f) |
| 200 | s->cm_osc = value; |
| 201 | break; |
| 202 | case 3: /* CM_CTRL */ |
| 203 | integratorcm_set_ctrl(s, value); |
| 204 | break; |
| 205 | case 5: /* CM_LOCK */ |
| 206 | s->cm_lock = value & 0xffff; |
| 207 | break; |
| 208 | case 7: /* CM_AUXOSC */ |
| 209 | if (s->cm_lock == 0xa05f) |
| 210 | s->cm_auxosc = value; |
| 211 | break; |
| 212 | case 8: /* CM_SDRAM */ |
| 213 | s->cm_sdram = value; |
| 214 | break; |
| 215 | case 9: /* CM_INIT */ |
| 216 | /* ??? This can change the memory bus frequency. */ |
| 217 | s->cm_init = value; |
| 218 | break; |
| 219 | case 12: /* CM_FLAGSS */ |
| 220 | s->cm_flags |= value; |
| 221 | break; |
| 222 | case 13: /* CM_FLAGSC */ |
| 223 | s->cm_flags &= ~value; |
| 224 | break; |
| 225 | case 14: /* CM_NVFLAGSS */ |
| 226 | s->cm_nvflags |= value; |
| 227 | break; |
| 228 | case 15: /* CM_NVFLAGSS */ |
| 229 | s->cm_nvflags &= ~value; |
| 230 | break; |
| 231 | case 18: /* CM_IRQ_ENSET */ |
| 232 | s->irq_enabled |= value; |
| 233 | integratorcm_update(s); |
| 234 | break; |
| 235 | case 19: /* CM_IRQ_ENCLR */ |
| 236 | s->irq_enabled &= ~value; |
| 237 | integratorcm_update(s); |
| 238 | break; |
| 239 | case 20: /* CM_SOFT_INTSET */ |
| 240 | s->int_level |= (value & 1); |
| 241 | integratorcm_update(s); |
| 242 | break; |
| 243 | case 21: /* CM_SOFT_INTCLR */ |
| 244 | s->int_level &= ~(value & 1); |
| 245 | integratorcm_update(s); |
| 246 | break; |
| 247 | case 26: /* CM_FIQ_ENSET */ |
| 248 | s->fiq_enabled |= value; |
| 249 | integratorcm_update(s); |
| 250 | break; |
| 251 | case 27: /* CM_FIQ_ENCLR */ |
| 252 | s->fiq_enabled &= ~value; |
| 253 | integratorcm_update(s); |
| 254 | break; |
| 255 | case 32: /* CM_VOLTAGE_CTL0 */ |
| 256 | case 33: /* CM_VOLTAGE_CTL1 */ |
| 257 | case 34: /* CM_VOLTAGE_CTL2 */ |
| 258 | case 35: /* CM_VOLTAGE_CTL3 */ |
| 259 | /* ??? Voltage control unimplemented. */ |
| 260 | break; |
| 261 | default: |
| 262 | qemu_log_mask(LOG_UNIMP, |
| 263 | "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n", |
| 264 | __func__, offset); |
| 265 | break; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | /* Integrator/CM control registers. */ |
| 270 | |
| 271 | static const MemoryRegionOps integratorcm_ops = { |
| 272 | .read = integratorcm_read, |
| 273 | .write = integratorcm_write, |
| 274 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 275 | }; |
| 276 | |
| 277 | static void integratorcm_init(Object *obj) |
| 278 | { |
| 279 | IntegratorCMState *s = INTEGRATOR_CM(obj); |
| 280 | |
| 281 | s->cm_osc = 0x01000048; |
| 282 | /* ??? What should the high bits of this value be? */ |
| 283 | s->cm_auxosc = 0x0007feff; |
| 284 | s->cm_sdram = 0x00011122; |
| 285 | memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); |
| 286 | s->cm_init = 0x00000112; |
| 287 | s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, |
| 288 | 1000); |
| 289 | |
| 290 | /* ??? Save/restore. */ |
| 291 | } |
| 292 | |
| 293 | static void integratorcm_realize(DeviceState *d, Error **errp) |
| 294 | { |
| 295 | IntegratorCMState *s = INTEGRATOR_CM(d); |
| 296 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
| 297 | |
| 298 | if (!memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", |
| 299 | 0x100000, errp)) { |
| 300 | return; |
| 301 | } |
| 302 | |
| 303 | memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, |
| 304 | "integratorcm", 0x00800000); |
| 305 | sysbus_init_mmio(dev, &s->iomem); |
| 306 | |
| 307 | integratorcm_do_remap(s); |
| 308 | |
| 309 | if (s->memsz >= 256) { |
| 310 | integrator_spd[31] = 64; |
| 311 | s->cm_sdram |= 0x10; |
| 312 | } else if (s->memsz >= 128) { |
| 313 | integrator_spd[31] = 32; |
| 314 | s->cm_sdram |= 0x0c; |
| 315 | } else if (s->memsz >= 64) { |
| 316 | integrator_spd[31] = 16; |
| 317 | s->cm_sdram |= 0x08; |
| 318 | } else if (s->memsz >= 32) { |
| 319 | integrator_spd[31] = 4; |
| 320 | s->cm_sdram |= 0x04; |
| 321 | } else { |
| 322 | integrator_spd[31] = 2; |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | /* Integrator/CP hardware emulation. */ |
| 327 | /* Primary interrupt controller. */ |
| 328 | |
| 329 | #define TYPE_INTEGRATOR_PIC "integrator_pic" |
| 330 | OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state, INTEGRATOR_PIC) |
| 331 | |
| 332 | struct icp_pic_state { |
| 333 | /*< private >*/ |
| 334 | SysBusDevice parent_obj; |
| 335 | /*< public >*/ |
| 336 | |
| 337 | MemoryRegion iomem; |
| 338 | uint32_t level; |
| 339 | uint32_t irq_enabled; |
| 340 | uint32_t fiq_enabled; |
| 341 | qemu_irq parent_irq; |
| 342 | qemu_irq parent_fiq; |
| 343 | }; |
| 344 | |
| 345 | static const VMStateDescription vmstate_icp_pic = { |
| 346 | .name = "icp_pic", |
| 347 | .version_id = 1, |
| 348 | .minimum_version_id = 1, |
| 349 | .fields = (const VMStateField[]) { |
| 350 | VMSTATE_UINT32(level, icp_pic_state), |
| 351 | VMSTATE_UINT32(irq_enabled, icp_pic_state), |
| 352 | VMSTATE_UINT32(fiq_enabled, icp_pic_state), |
| 353 | VMSTATE_END_OF_LIST() |
| 354 | } |
| 355 | }; |
| 356 | |
| 357 | static void icp_pic_update(icp_pic_state *s) |
| 358 | { |
| 359 | uint32_t flags; |
| 360 | |
| 361 | flags = (s->level & s->irq_enabled); |
| 362 | qemu_set_irq(s->parent_irq, flags != 0); |
| 363 | flags = (s->level & s->fiq_enabled); |
| 364 | qemu_set_irq(s->parent_fiq, flags != 0); |
| 365 | } |
| 366 | |
| 367 | static void icp_pic_set_irq(void *opaque, int irq, int level) |
| 368 | { |
| 369 | icp_pic_state *s = (icp_pic_state *)opaque; |
| 370 | if (level) |
| 371 | s->level |= 1 << irq; |
| 372 | else |
| 373 | s->level &= ~(1 << irq); |
| 374 | icp_pic_update(s); |
| 375 | } |
| 376 | |
| 377 | static uint64_t icp_pic_read(void *opaque, hwaddr offset, |
| 378 | unsigned size) |
| 379 | { |
| 380 | icp_pic_state *s = (icp_pic_state *)opaque; |
| 381 | |
| 382 | switch (offset >> 2) { |
| 383 | case 0: /* IRQ_STATUS */ |
| 384 | return s->level & s->irq_enabled; |
| 385 | case 1: /* IRQ_RAWSTAT */ |
| 386 | return s->level; |
| 387 | case 2: /* IRQ_ENABLESET */ |
| 388 | return s->irq_enabled; |
| 389 | case 4: /* INT_SOFTSET */ |
| 390 | return s->level & 1; |
| 391 | case 8: /* FRQ_STATUS */ |
| 392 | return s->level & s->fiq_enabled; |
| 393 | case 9: /* FRQ_RAWSTAT */ |
| 394 | return s->level; |
| 395 | case 10: /* FRQ_ENABLESET */ |
| 396 | return s->fiq_enabled; |
| 397 | case 3: /* IRQ_ENABLECLR */ |
| 398 | case 5: /* INT_SOFTCLR */ |
| 399 | case 11: /* FRQ_ENABLECLR */ |
| 400 | default: |
| 401 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 402 | __func__, offset); |
| 403 | return 0; |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | static void icp_pic_write(void *opaque, hwaddr offset, |
| 408 | uint64_t value, unsigned size) |
| 409 | { |
| 410 | icp_pic_state *s = (icp_pic_state *)opaque; |
| 411 | |
| 412 | switch (offset >> 2) { |
| 413 | case 2: /* IRQ_ENABLESET */ |
| 414 | s->irq_enabled |= value; |
| 415 | break; |
| 416 | case 3: /* IRQ_ENABLECLR */ |
| 417 | s->irq_enabled &= ~value; |
| 418 | break; |
| 419 | case 4: /* INT_SOFTSET */ |
| 420 | if (value & 1) |
| 421 | icp_pic_set_irq(s, 0, 1); |
| 422 | break; |
| 423 | case 5: /* INT_SOFTCLR */ |
| 424 | if (value & 1) |
| 425 | icp_pic_set_irq(s, 0, 0); |
| 426 | break; |
| 427 | case 10: /* FRQ_ENABLESET */ |
| 428 | s->fiq_enabled |= value; |
| 429 | break; |
| 430 | case 11: /* FRQ_ENABLECLR */ |
| 431 | s->fiq_enabled &= ~value; |
| 432 | break; |
| 433 | case 0: /* IRQ_STATUS */ |
| 434 | case 1: /* IRQ_RAWSTAT */ |
| 435 | case 8: /* FRQ_STATUS */ |
| 436 | case 9: /* FRQ_RAWSTAT */ |
| 437 | default: |
| 438 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 439 | __func__, offset); |
| 440 | return; |
| 441 | } |
| 442 | icp_pic_update(s); |
| 443 | } |
| 444 | |
| 445 | static const MemoryRegionOps icp_pic_ops = { |
| 446 | .read = icp_pic_read, |
| 447 | .write = icp_pic_write, |
| 448 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 449 | }; |
| 450 | |
| 451 | static void icp_pic_init(Object *obj) |
| 452 | { |
| 453 | DeviceState *dev = DEVICE(obj); |
| 454 | icp_pic_state *s = INTEGRATOR_PIC(obj); |
| 455 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 456 | |
| 457 | qdev_init_gpio_in(dev, icp_pic_set_irq, 32); |
| 458 | sysbus_init_irq(sbd, &s->parent_irq); |
| 459 | sysbus_init_irq(sbd, &s->parent_fiq); |
| 460 | memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, |
| 461 | "icp-pic", 0x00800000); |
| 462 | sysbus_init_mmio(sbd, &s->iomem); |
| 463 | } |
| 464 | |
| 465 | /* CP control registers. */ |
| 466 | |
| 467 | #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" |
| 468 | OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState, ICP_CONTROL_REGS) |
| 469 | |
| 470 | struct ICPCtrlRegsState { |
| 471 | /*< private >*/ |
| 472 | SysBusDevice parent_obj; |
| 473 | /*< public >*/ |
| 474 | |
| 475 | MemoryRegion iomem; |
| 476 | |
| 477 | qemu_irq mmc_irq; |
| 478 | uint32_t intreg_state; |
| 479 | }; |
| 480 | |
| 481 | #define ICP_GPIO_MMC_WPROT "mmc-wprot" |
| 482 | #define ICP_GPIO_MMC_CARDIN "mmc-cardin" |
| 483 | |
| 484 | #define ICP_INTREG_WPROT (1 << 0) |
| 485 | #define ICP_INTREG_CARDIN (1 << 3) |
| 486 | |
| 487 | static const VMStateDescription vmstate_icp_control = { |
| 488 | .name = "icp_control", |
| 489 | .version_id = 1, |
| 490 | .minimum_version_id = 1, |
| 491 | .fields = (const VMStateField[]) { |
| 492 | VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), |
| 493 | VMSTATE_END_OF_LIST() |
| 494 | } |
| 495 | }; |
| 496 | |
| 497 | static uint64_t icp_control_read(void *opaque, hwaddr offset, |
| 498 | unsigned size) |
| 499 | { |
| 500 | ICPCtrlRegsState *s = opaque; |
| 501 | |
| 502 | switch (offset >> 2) { |
| 503 | case 0: /* CP_IDFIELD */ |
| 504 | return 0x41034003; |
| 505 | case 1: /* CP_FLASHPROG */ |
| 506 | return 0; |
| 507 | case 2: /* CP_INTREG */ |
| 508 | return s->intreg_state; |
| 509 | case 3: /* CP_DECODE */ |
| 510 | return 0x11; |
| 511 | default: |
| 512 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 513 | __func__, offset); |
| 514 | return 0; |
| 515 | } |
| 516 | } |
| 517 | |
| 518 | static void icp_control_write(void *opaque, hwaddr offset, |
| 519 | uint64_t value, unsigned size) |
| 520 | { |
| 521 | ICPCtrlRegsState *s = opaque; |
| 522 | |
| 523 | switch (offset >> 2) { |
| 524 | case 2: /* CP_INTREG */ |
| 525 | s->intreg_state &= ~(value & ICP_INTREG_CARDIN); |
| 526 | qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); |
| 527 | break; |
| 528 | case 1: /* CP_FLASHPROG */ |
| 529 | case 3: /* CP_DECODE */ |
| 530 | /* Nothing interesting implemented yet. */ |
| 531 | break; |
| 532 | default: |
| 533 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 534 | __func__, offset); |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | static const MemoryRegionOps icp_control_ops = { |
| 539 | .read = icp_control_read, |
| 540 | .write = icp_control_write, |
| 541 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 542 | }; |
| 543 | |
| 544 | static void icp_control_mmc_wprot(void *opaque, int line, int level) |
| 545 | { |
| 546 | ICPCtrlRegsState *s = opaque; |
| 547 | |
| 548 | s->intreg_state &= ~ICP_INTREG_WPROT; |
| 549 | if (level) { |
| 550 | s->intreg_state |= ICP_INTREG_WPROT; |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | static void icp_control_mmc_cardin(void *opaque, int line, int level) |
| 555 | { |
| 556 | ICPCtrlRegsState *s = opaque; |
| 557 | |
| 558 | /* line is released by writing to CP_INTREG */ |
| 559 | if (level) { |
| 560 | s->intreg_state |= ICP_INTREG_CARDIN; |
| 561 | qemu_set_irq(s->mmc_irq, 1); |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | static void icp_control_init(Object *obj) |
| 566 | { |
| 567 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 568 | ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); |
| 569 | DeviceState *dev = DEVICE(obj); |
| 570 | |
| 571 | memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, |
| 572 | "icp_ctrl_regs", 0x00800000); |
| 573 | sysbus_init_mmio(sbd, &s->iomem); |
| 574 | |
| 575 | qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); |
| 576 | qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, |
| 577 | ICP_GPIO_MMC_CARDIN, 1); |
| 578 | sysbus_init_irq(sbd, &s->mmc_irq); |
| 579 | } |
| 580 | |
| 581 | |
| 582 | /* Board init. */ |
| 583 | |
| 584 | #define TYPE_INTEGRATORCP_MACHINE MACHINE_TYPE_NAME("integratorcp") |
| 585 | OBJECT_DECLARE_SIMPLE_TYPE(IntegratorcpMachineState, |
| 586 | INTEGRATORCP_MACHINE) |
| 587 | |
| 588 | struct IntegratorcpMachineState { |
| 589 | MachineState parent; |
| 590 | |
| 591 | struct arm_boot_info bootinfo; |
| 592 | }; |
| 593 | |
| 594 | static void integratorcp_init(MachineState *machine) |
| 595 | { |
| 596 | IntegratorcpMachineState *icms = INTEGRATORCP_MACHINE(machine); |
| 597 | ram_addr_t ram_size = machine->ram_size; |
| 598 | Object *cpuobj; |
| 599 | ARMCPU *cpu; |
| 600 | MemoryRegion *address_space_mem = get_system_memory(); |
| 601 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); |
| 602 | qemu_irq pic[32]; |
| 603 | DeviceState *dev, *sic, *icp; |
| 604 | DriveInfo *dinfo; |
| 605 | int i; |
| 606 | |
| 607 | cpuobj = object_new(machine->cpu_type); |
| 608 | |
| 609 | /* By default ARM1176 CPUs have EL3 enabled. This board does not |
| 610 | * currently support EL3 so the CPU EL3 property is disabled before |
| 611 | * realization. |
| 612 | */ |
| 613 | if (object_property_find(cpuobj, "has_el3")) { |
| 614 | object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); |
| 615 | } |
| 616 | |
| 617 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 618 | |
| 619 | cpu = ARM_CPU(cpuobj); |
| 620 | |
| 621 | /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ |
| 622 | /* ??? RAM should repeat to fill physical memory space. */ |
| 623 | /* SDRAM at address zero*/ |
| 624 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
| 625 | /* And again at address 0x80000000 */ |
| 626 | memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, |
| 627 | 0, ram_size); |
| 628 | memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); |
| 629 | |
| 630 | dev = qdev_new(TYPE_INTEGRATOR_CM); |
| 631 | qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); |
| 632 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 633 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
| 634 | |
| 635 | dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, |
| 636 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), |
| 637 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), |
| 638 | NULL); |
| 639 | for (i = 0; i < 32; i++) { |
| 640 | pic[i] = qdev_get_gpio_in(dev, i); |
| 641 | } |
| 642 | sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); |
| 643 | sysbus_create_varargs("integrator_pit", 0x13000000, |
| 644 | pic[5], pic[6], pic[7], NULL); |
| 645 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
| 646 | pl011_create(0x16000000, pic[1], serial_hd(0)); |
| 647 | pl011_create(0x17000000, pic[2], serial_hd(1)); |
| 648 | icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, |
| 649 | qdev_get_gpio_in(sic, 3)); |
| 650 | sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); |
| 651 | sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); |
| 652 | sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); |
| 653 | |
| 654 | dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); |
| 655 | qdev_connect_gpio_out_named(dev, "card-read-only", 0, |
| 656 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); |
| 657 | qdev_connect_gpio_out_named(dev, "card-inserted", 0, |
| 658 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); |
| 659 | dinfo = drive_get(IF_SD, 0, 0); |
| 660 | if (dinfo) { |
| 661 | DeviceState *card; |
| 662 | |
| 663 | card = qdev_new(TYPE_SD_CARD); |
| 664 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), |
| 665 | &error_fatal); |
| 666 | qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), |
| 667 | &error_fatal); |
| 668 | } |
| 669 | |
| 670 | dev = qdev_new("pl041"); |
| 671 | if (machine->audiodev) { |
| 672 | qdev_prop_set_string(dev, "audiodev", machine->audiodev); |
| 673 | } |
| 674 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 675 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x1d000000); |
| 676 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[25]); |
| 677 | |
| 678 | if (qemu_find_nic_info("smc91c111", true, NULL)) { |
| 679 | smc91c111_init(0xc8000000, pic[27]); |
| 680 | } |
| 681 | |
| 682 | dev = qdev_new("pl110"); |
| 683 | object_property_set_link(OBJECT(dev), "framebuffer-memory", |
| 684 | OBJECT(address_space_mem), &error_fatal); |
| 685 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 686 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000); |
| 687 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]); |
| 688 | |
| 689 | icms->bootinfo.loader_start = 0x0; |
| 690 | icms->bootinfo.board_id = 0x113; |
| 691 | icms->bootinfo.ram_size = ram_size; |
| 692 | arm_load_kernel(cpu, machine, &icms->bootinfo); |
| 693 | } |
| 694 | |
| 695 | static void integratorcp_machine_init(MachineClass *mc) |
| 696 | { |
| 697 | mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; |
| 698 | mc->init = integratorcp_init; |
| 699 | mc->ignore_memory_transaction_failures = true; |
| 700 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
| 701 | mc->default_ram_id = "integrator.ram"; |
| 702 | mc->auto_create_sdcard = true; |
| 703 | |
| 704 | machine_add_audiodev_property(mc); |
| 705 | } |
| 706 | |
| 707 | DEFINE_MACHINE_EXTENDED("integratorcp", MACHINE, IntegratorcpMachineState, |
| 708 | integratorcp_machine_init, false, |
| 709 | arm_machine_interfaces) |
| 710 | |
| 711 | static const Property core_properties[] = { |
| 712 | DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), |
| 713 | }; |
| 714 | |
| 715 | static void core_class_init(ObjectClass *klass, const void *data) |
| 716 | { |
| 717 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 718 | |
| 719 | device_class_set_props(dc, core_properties); |
| 720 | dc->realize = integratorcm_realize; |
| 721 | dc->vmsd = &vmstate_integratorcm; |
| 722 | } |
| 723 | |
| 724 | static void icp_pic_class_init(ObjectClass *klass, const void *data) |
| 725 | { |
| 726 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 727 | |
| 728 | dc->vmsd = &vmstate_icp_pic; |
| 729 | } |
| 730 | |
| 731 | static void icp_control_class_init(ObjectClass *klass, const void *data) |
| 732 | { |
| 733 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 734 | |
| 735 | dc->vmsd = &vmstate_icp_control; |
| 736 | } |
| 737 | |
| 738 | static const TypeInfo core_info = { |
| 739 | .name = TYPE_INTEGRATOR_CM, |
| 740 | .parent = TYPE_SYS_BUS_DEVICE, |
| 741 | .instance_size = sizeof(IntegratorCMState), |
| 742 | .instance_init = integratorcm_init, |
| 743 | .class_init = core_class_init, |
| 744 | }; |
| 745 | |
| 746 | static const TypeInfo icp_pic_info = { |
| 747 | .name = TYPE_INTEGRATOR_PIC, |
| 748 | .parent = TYPE_SYS_BUS_DEVICE, |
| 749 | .instance_size = sizeof(icp_pic_state), |
| 750 | .instance_init = icp_pic_init, |
| 751 | .class_init = icp_pic_class_init, |
| 752 | }; |
| 753 | |
| 754 | static const TypeInfo icp_ctrl_regs_info = { |
| 755 | .name = TYPE_ICP_CONTROL_REGS, |
| 756 | .parent = TYPE_SYS_BUS_DEVICE, |
| 757 | .instance_size = sizeof(ICPCtrlRegsState), |
| 758 | .instance_init = icp_control_init, |
| 759 | .class_init = icp_control_class_init, |
| 760 | }; |
| 761 | |
| 762 | static void integratorcp_register_types(void) |
| 763 | { |
| 764 | type_register_static(&icp_pic_info); |
| 765 | type_register_static(&core_info); |
| 766 | type_register_static(&icp_ctrl_regs_info); |
| 767 | } |
| 768 | |
| 769 | type_init(integratorcp_register_types) |