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1 /*
2 * MAX78000 SOC
3 *
4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 * Implementation based on stm32f205 and Max78000 user guide at
9 * https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "system/address-spaces.h"
15 #include "system/system.h"
16 #include "hw/arm/max78000_soc.h"
17 #include "hw/core/qdev-clock.h"
18 #include "hw/misc/unimp.h"
19
20 static const uint32_t max78000_icc_addr[] = {0x4002a000, 0x4002a800};
21 static const uint32_t max78000_uart_addr[] = {0x40042000, 0x40043000,
22 0x40044000};
23
24 static const int max78000_uart_irq[] = {14, 15, 34};
25
26 static void max78000_soc_initfn(Object *obj)
27 {
28 MAX78000State *s = MAX78000_SOC(obj);
29 int i;
30
31 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
32
33 object_initialize_child(obj, "gcr", &s->gcr, TYPE_MAX78000_GCR);
34
35 for (i = 0; i < MAX78000_NUM_ICC; i++) {
36 g_autofree char *name = g_strdup_printf("icc%d", i);
37 object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC);
38 }
39
40 for (i = 0; i < MAX78000_NUM_UART; i++) {
41 g_autofree char *name = g_strdup_printf("uart%d", i);
42 object_initialize_child(obj, name, &s->uart[i],
43 TYPE_MAX78000_UART);
44 }
45
46 object_initialize_child(obj, "trng", &s->trng, TYPE_MAX78000_TRNG);
47
48 object_initialize_child(obj, "aes", &s->aes, TYPE_MAX78000_AES);
49
50 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
51 }
52
53 static void max78000_soc_realize(DeviceState *dev_soc, Error **errp)
54 {
55 MAX78000State *s = MAX78000_SOC(dev_soc);
56 MemoryRegion *system_memory = get_system_memory();
57 DeviceState *dev, *gcrdev, *armv7m;
58 SysBusDevice *busdev;
59 Error *err = NULL;
60 int i;
61
62 if (!clock_has_source(s->sysclk)) {
63 error_setg(errp, "sysclk clock must be wired up by the board code");
64 return;
65 }
66
67 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash",
68 FLASH_SIZE, &err);
69 if (err != NULL) {
70 error_propagate(errp, err);
71 return;
72 }
73
74 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
75
76 memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE,
77 &err);
78
79 gcrdev = DEVICE(&s->gcr);
80 object_property_set_link(OBJECT(gcrdev), "sram", OBJECT(&s->sram),
81 &err);
82
83 if (err != NULL) {
84 error_propagate(errp, err);
85 return;
86 }
87 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
88
89 armv7m = DEVICE(&s->armv7m);
90
91 /*
92 * The MAX78000 user guide's Interrupt Vector Table section
93 * suggests that there are 120 IRQs in the text, while only listing
94 * 104 in table 5-1. Implement the more generous of the two.
95 * This has not been tested in hardware.
96 */
97 qdev_prop_set_uint32(armv7m, "num-irq", 120);
98 qdev_prop_set_uint8(armv7m, "num-prio-bits", 3);
99 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
100 qdev_prop_set_bit(armv7m, "enable-bitband", true);
101 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
102 object_property_set_link(OBJECT(&s->armv7m), "memory",
103 OBJECT(system_memory), &error_abort);
104 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
105 return;
106 }
107
108 for (i = 0; i < MAX78000_NUM_ICC; i++) {
109 dev = DEVICE(&(s->icc[i]));
110 sysbus_realize(SYS_BUS_DEVICE(dev), errp);
111 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]);
112 }
113
114 for (i = 0; i < MAX78000_NUM_UART; i++) {
115 g_autofree char *link = g_strdup_printf("uart%d", i);
116 dev = DEVICE(&(s->uart[i]));
117 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
118 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
119 return;
120 }
121
122 object_property_set_link(OBJECT(gcrdev), link, OBJECT(dev),
123 &err);
124
125 busdev = SYS_BUS_DEVICE(dev);
126 sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]);
127 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,
128 max78000_uart_irq[i]));
129 }
130
131 dev = DEVICE(&s->trng);
132 sysbus_realize(SYS_BUS_DEVICE(dev), errp);
133 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x4004d000);
134 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 4));
135
136 object_property_set_link(OBJECT(gcrdev), "trng", OBJECT(dev), &err);
137
138 dev = DEVICE(&s->aes);
139 sysbus_realize(SYS_BUS_DEVICE(dev), errp);
140 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40007400);
141 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 5));
142
143 object_property_set_link(OBJECT(gcrdev), "aes", OBJECT(dev), &err);
144
145 dev = DEVICE(&s->gcr);
146 sysbus_realize(SYS_BUS_DEVICE(dev), errp);
147 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000);
148
149 create_unimplemented_device("systemInterface", 0x40000400, 0x400);
150 create_unimplemented_device("functionControl", 0x40000800, 0x400);
151 create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400);
152 create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40);
153 create_unimplemented_device("SIMO", 0x40004400, 0x400);
154 create_unimplemented_device("trimSystemInit", 0x40005400, 0x400);
155 create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400);
156 create_unimplemented_device("wakeupTimer", 0x40006400, 0x400);
157 create_unimplemented_device("powerSequencer", 0x40006800, 0x400);
158 create_unimplemented_device("miscControl", 0x40006c00, 0x400);
159
160 create_unimplemented_device("gpio0", 0x40008000, 0x1000);
161 create_unimplemented_device("gpio1", 0x40009000, 0x1000);
162
163 create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000);
164 create_unimplemented_device("CRC", 0x4000f000, 0x1000);
165
166 create_unimplemented_device("timer0", 0x40010000, 0x1000);
167 create_unimplemented_device("timer1", 0x40011000, 0x1000);
168 create_unimplemented_device("timer2", 0x40012000, 0x1000);
169 create_unimplemented_device("timer3", 0x40013000, 0x1000);
170
171 create_unimplemented_device("i2c0", 0x4001d000, 0x1000);
172 create_unimplemented_device("i2c1", 0x4001e000, 0x1000);
173 create_unimplemented_device("i2c2", 0x4001f000, 0x1000);
174
175 create_unimplemented_device("standardDMA", 0x40028000, 0x1000);
176 create_unimplemented_device("flashController0", 0x40029000, 0x400);
177
178 create_unimplemented_device("adc", 0x40034000, 0x1000);
179 create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0);
180 create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000);
181 create_unimplemented_device("semaphore", 0x4003e000, 0x1000);
182
183 create_unimplemented_device("spi1", 0x40046000, 0x2000);
184 create_unimplemented_device("i2s", 0x40060000, 0x1000);
185 create_unimplemented_device("lowPowerControl", 0x40080000, 0x400);
186 create_unimplemented_device("gpio2", 0x40080400, 0x200);
187 create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x400);
188 create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400);
189
190 create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400);
191 create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400);
192 create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400);
193
194 create_unimplemented_device("spi0", 0x400be000, 0x400);
195
196 /*
197 * The MAX78000 user guide's base address map lists the CNN TX FIFO as
198 * beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FIFO
199 * is listed as having data accessible up to offset 0x1000, the user
200 * guide is likely incorrect.
201 */
202 create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000);
203
204 create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x10000);
205 create_unimplemented_device("cnnx16quad0", 0x50100000, 0x40000);
206 create_unimplemented_device("cnnx16quad1", 0x50500000, 0x40000);
207 create_unimplemented_device("cnnx16quad2", 0x50900000, 0x40000);
208 create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x40000);
209
210 }
211
212 static void max78000_soc_class_init(ObjectClass *klass, const void *data)
213 {
214 DeviceClass *dc = DEVICE_CLASS(klass);
215
216 dc->realize = max78000_soc_realize;
217 }
218
219 static const TypeInfo max78000_soc_info = {
220 .name = TYPE_MAX78000_SOC,
221 .parent = TYPE_SYS_BUS_DEVICE,
222 .instance_size = sizeof(MAX78000State),
223 .instance_init = max78000_soc_initfn,
224 .class_init = max78000_soc_class_init,
225 };
226
227 static void max78000_soc_types(void)
228 {
229 type_register_static(&max78000_soc_info);
230 }
231
232 type_init(max78000_soc_types)