| 1 | /* |
| 2 | * Arm V2M MPS2 and MPS3 board emulation, trustzone aware FPGA images |
| 3 | * |
| 4 | * Copyright (c) 2017 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger |
| 13 | * FPGA but is otherwise the same as the 2). Since the CPU itself |
| 14 | * and most of the devices are in the FPGA, the details of the board |
| 15 | * as seen by the guest depend significantly on the FPGA image. |
| 16 | * This source file covers the following FPGA images, for TrustZone cores: |
| 17 | * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 |
| 18 | * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 |
| 19 | * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 |
| 20 | * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547 |
| 21 | * "mps3-an555" -- Single Cortex-M85 as documented in Application Note AN555 |
| 22 | * |
| 23 | * Links to the TRM for the board itself and to the various Application |
| 24 | * Notes which document the FPGA images can be found here: |
| 25 | * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 |
| 26 | * |
| 27 | * MPS2 and MPS2+ Board TRM: |
| 28 | * https://developer.arm.com/documentation/100112/latest/ |
| 29 | * MPS3 Board TRM: |
| 30 | * https://developer.arm.com/documentation/100765/latest/ |
| 31 | * |
| 32 | * Application Note AN505: |
| 33 | * https://developer.arm.com/documentation/dai0505/latest/ |
| 34 | * Application Note AN521: |
| 35 | * https://developer.arm.com/documentation/dai0521/latest/ |
| 36 | * Application Note AN524: |
| 37 | * https://developer.arm.com/documentation/dai0524/latest/ |
| 38 | * Application Note AN547: |
| 39 | * https://developer.arm.com/documentation/dai0547/latest/ |
| 40 | * Application Note AN555: |
| 41 | * https://developer.arm.com/documentation/107642/latest/ |
| 42 | * |
| 43 | * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide |
| 44 | * (ARM ECM0601256) for the details of some of the device layout: |
| 45 | * https://developer.arm.com/documentation/ecm0601256/latest |
| 46 | * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines |
| 47 | * most of the device layout: |
| 48 | * https://developer.arm.com/documentation/101104/latest/ |
| 49 | * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: |
| 50 | * https://developer.arm.com/documentation/101773/latest/ |
| 51 | * and the AN555 uses the SSE-310, whose layout is in the SSE-310 TRM: |
| 52 | * https://developer.arm.com/documentation/102778/latest/ |
| 53 | */ |
| 54 | |
| 55 | #include "qemu/osdep.h" |
| 56 | #include "qemu/units.h" |
| 57 | #include "qemu/cutils.h" |
| 58 | #include "qapi/error.h" |
| 59 | #include "qobject/qlist.h" |
| 60 | #include "qemu/error-report.h" |
| 61 | #include "hw/arm/boot.h" |
| 62 | #include "hw/arm/armv7m.h" |
| 63 | #include "hw/arm/machines-qom.h" |
| 64 | #include "hw/core/or-irq.h" |
| 65 | #include "hw/core/boards.h" |
| 66 | #include "system/address-spaces.h" |
| 67 | #include "system/system.h" |
| 68 | #include "system/reset.h" |
| 69 | #include "hw/misc/unimp.h" |
| 70 | #include "hw/char/cmsdk-apb-uart.h" |
| 71 | #include "hw/timer/cmsdk-apb-timer.h" |
| 72 | #include "hw/misc/mps2-scc.h" |
| 73 | #include "hw/misc/mps2-fpgaio.h" |
| 74 | #include "hw/misc/tz-mpc.h" |
| 75 | #include "hw/misc/tz-msc.h" |
| 76 | #include "hw/arm/armsse.h" |
| 77 | #include "hw/dma/pl080.h" |
| 78 | #include "hw/rtc/pl031.h" |
| 79 | #include "hw/ssi/pl022.h" |
| 80 | #include "hw/i2c/arm_sbcon_i2c.h" |
| 81 | #include "hw/net/lan9118.h" |
| 82 | #include "net/net.h" |
| 83 | #include "hw/core/split-irq.h" |
| 84 | #include "hw/core/qdev-clock.h" |
| 85 | #include "qom/object.h" |
| 86 | #include "hw/core/irq.h" |
| 87 | |
| 88 | #define MPS2TZ_NUMIRQ_MAX 96 |
| 89 | #define MPS2TZ_RAM_MAX 5 |
| 90 | |
| 91 | typedef enum MPS2TZFPGAType { |
| 92 | FPGA_AN505, |
| 93 | FPGA_AN521, |
| 94 | FPGA_AN524, |
| 95 | FPGA_AN547, |
| 96 | FPGA_AN555, |
| 97 | } MPS2TZFPGAType; |
| 98 | |
| 99 | /* |
| 100 | * Define the layout of RAM in a board, including which parts are |
| 101 | * behind which MPCs. |
| 102 | * mrindex specifies the index into mms->ram[] to use for the backing RAM; |
| 103 | * -1 means "use the system RAM". |
| 104 | */ |
| 105 | typedef struct RAMInfo { |
| 106 | const char *name; |
| 107 | uint32_t base; |
| 108 | uint32_t size; |
| 109 | int mpc; /* MPC number, -1 for "not behind an MPC" */ |
| 110 | int mrindex; |
| 111 | int flags; |
| 112 | } RAMInfo; |
| 113 | |
| 114 | /* |
| 115 | * Flag values: |
| 116 | * IS_ALIAS: this RAM area is an alias to the upstream end of the |
| 117 | * MPC specified by its .mpc value |
| 118 | * IS_ROM: this RAM area is read-only |
| 119 | */ |
| 120 | #define IS_ALIAS 1 |
| 121 | #define IS_ROM 2 |
| 122 | |
| 123 | struct MPS2TZMachineClass { |
| 124 | MachineClass parent; |
| 125 | MPS2TZFPGAType fpga_type; |
| 126 | uint32_t scc_id; |
| 127 | uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ |
| 128 | uint32_t apb_periph_frq; /* APB peripheral frequency in Hz */ |
| 129 | uint32_t len_oscclk; |
| 130 | const uint32_t *oscclk; |
| 131 | uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ |
| 132 | bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ |
| 133 | bool fpgaio_has_dbgctrl; /* Does FPGAIO have DBGCTRL register? */ |
| 134 | bool fpgaio_has_gpioalt2; /* Does FPGAIO have GPIOALT2 register? */ |
| 135 | int numirq; /* Number of external interrupts */ |
| 136 | int uart_overflow_irq; /* number of the combined UART overflow IRQ */ |
| 137 | uint32_t init_svtor; /* init-svtor setting for SSE */ |
| 138 | uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ |
| 139 | uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ |
| 140 | uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ |
| 141 | uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ |
| 142 | uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ |
| 143 | const RAMInfo *raminfo; |
| 144 | const char *armsse_type; |
| 145 | uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ |
| 146 | }; |
| 147 | |
| 148 | struct MPS2TZMachineState { |
| 149 | MachineState parent; |
| 150 | |
| 151 | ARMSSE iotkit; |
| 152 | MemoryRegion ram[MPS2TZ_RAM_MAX]; |
| 153 | MemoryRegion eth_usb_container; |
| 154 | |
| 155 | MPS2SCC scc; |
| 156 | MPS2FPGAIO fpgaio; |
| 157 | TZPPC ppc[5]; |
| 158 | TZMPC mpc[3]; |
| 159 | PL022State spi[5]; |
| 160 | ArmSbconI2CState i2c[5]; |
| 161 | UnimplementedDeviceState i2s_audio; |
| 162 | UnimplementedDeviceState gpio[4]; |
| 163 | UnimplementedDeviceState gfx; |
| 164 | UnimplementedDeviceState cldc; |
| 165 | UnimplementedDeviceState usb; |
| 166 | UnimplementedDeviceState ta[3]; /* timing adatper */ |
| 167 | UnimplementedDeviceState qspi_controller[3]; |
| 168 | PL031State rtc; |
| 169 | PL080State dma[4]; |
| 170 | TZMSC msc[4]; |
| 171 | CMSDKAPBUART uart[6]; |
| 172 | SplitIRQ sec_resp_splitter; |
| 173 | OrIRQState uart_irq_orgate; |
| 174 | DeviceState *lan9118; |
| 175 | SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; |
| 176 | Clock *sysclk; |
| 177 | Clock *s32kclk; |
| 178 | |
| 179 | bool remap; |
| 180 | qemu_irq remap_irq; |
| 181 | }; |
| 182 | |
| 183 | #define TYPE_MPS2TZ_MACHINE "mps2tz" |
| 184 | #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") |
| 185 | #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") |
| 186 | #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") |
| 187 | #define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") |
| 188 | #define TYPE_MPS3TZ_AN555_MACHINE MACHINE_TYPE_NAME("mps3-an555") |
| 189 | |
| 190 | OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) |
| 191 | |
| 192 | /* Slow 32Khz S32KCLK frequency in Hz */ |
| 193 | #define S32KCLK_FRQ (32 * 1000) |
| 194 | |
| 195 | /* |
| 196 | * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit |
| 197 | * emulation of that much guest RAM, so artificially make it smaller. |
| 198 | */ |
| 199 | #if HOST_LONG_BITS == 32 |
| 200 | #define MPS3_DDR_SIZE (1 * GiB) |
| 201 | #else |
| 202 | #define MPS3_DDR_SIZE (2 * GiB) |
| 203 | #endif |
| 204 | |
| 205 | /* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ |
| 206 | #define MPU_REGION_DEFAULT UINT32_MAX |
| 207 | |
| 208 | static const uint32_t an505_oscclk[] = { |
| 209 | 40000000, |
| 210 | 24580000, |
| 211 | 25000000, |
| 212 | }; |
| 213 | |
| 214 | static const uint32_t an524_oscclk[] = { |
| 215 | 24000000, |
| 216 | 32000000, |
| 217 | 50000000, |
| 218 | 50000000, |
| 219 | 24576000, |
| 220 | 23750000, |
| 221 | }; |
| 222 | |
| 223 | static const uint32_t an555_oscclk[] = { |
| 224 | 24000000, |
| 225 | 25000000, |
| 226 | 30000000, |
| 227 | 50000000, |
| 228 | 24576000, |
| 229 | 23750000, |
| 230 | }; |
| 231 | |
| 232 | static const RAMInfo an505_raminfo[] = { { |
| 233 | .name = "ssram-0", |
| 234 | .base = 0x00000000, |
| 235 | .size = 0x00400000, |
| 236 | .mpc = 0, |
| 237 | .mrindex = 0, |
| 238 | }, { |
| 239 | .name = "ssram-1", |
| 240 | .base = 0x28000000, |
| 241 | .size = 0x00200000, |
| 242 | .mpc = 1, |
| 243 | .mrindex = 1, |
| 244 | }, { |
| 245 | .name = "ssram-2", |
| 246 | .base = 0x28200000, |
| 247 | .size = 0x00200000, |
| 248 | .mpc = 2, |
| 249 | .mrindex = 2, |
| 250 | }, { |
| 251 | .name = "ssram-0-alias", |
| 252 | .base = 0x00400000, |
| 253 | .size = 0x00400000, |
| 254 | .mpc = 0, |
| 255 | .mrindex = 3, |
| 256 | .flags = IS_ALIAS, |
| 257 | }, { |
| 258 | /* Use the largest bit of contiguous RAM as our "system memory" */ |
| 259 | .name = "mps.ram", |
| 260 | .base = 0x80000000, |
| 261 | .size = 16 * MiB, |
| 262 | .mpc = -1, |
| 263 | .mrindex = -1, |
| 264 | }, { |
| 265 | .name = NULL, |
| 266 | }, |
| 267 | }; |
| 268 | |
| 269 | /* |
| 270 | * Note that the addresses and MPC numbering here should match up |
| 271 | * with those used in remap_memory(), which can swap the BRAM and QSPI. |
| 272 | */ |
| 273 | static const RAMInfo an524_raminfo[] = { { |
| 274 | .name = "bram", |
| 275 | .base = 0x00000000, |
| 276 | .size = 512 * KiB, |
| 277 | .mpc = 0, |
| 278 | .mrindex = 0, |
| 279 | }, { |
| 280 | /* We don't model QSPI flash yet; for now expose it as simple ROM */ |
| 281 | .name = "QSPI", |
| 282 | .base = 0x28000000, |
| 283 | .size = 8 * MiB, |
| 284 | .mpc = 1, |
| 285 | .mrindex = 1, |
| 286 | .flags = IS_ROM, |
| 287 | }, { |
| 288 | .name = "DDR", |
| 289 | .base = 0x60000000, |
| 290 | .size = MPS3_DDR_SIZE, |
| 291 | .mpc = 2, |
| 292 | .mrindex = -1, |
| 293 | }, { |
| 294 | .name = NULL, |
| 295 | }, |
| 296 | }; |
| 297 | |
| 298 | static const RAMInfo an547_raminfo[] = { { |
| 299 | .name = "sram", |
| 300 | .base = 0x01000000, |
| 301 | .size = 2 * MiB, |
| 302 | .mpc = 0, |
| 303 | .mrindex = 1, |
| 304 | }, { |
| 305 | .name = "sram 2", |
| 306 | .base = 0x21000000, |
| 307 | .size = 4 * MiB, |
| 308 | .mpc = -1, |
| 309 | .mrindex = 3, |
| 310 | }, { |
| 311 | /* We don't model QSPI flash yet; for now expose it as simple ROM */ |
| 312 | .name = "QSPI", |
| 313 | .base = 0x28000000, |
| 314 | .size = 8 * MiB, |
| 315 | .mpc = 1, |
| 316 | .mrindex = 4, |
| 317 | .flags = IS_ROM, |
| 318 | }, { |
| 319 | .name = "DDR", |
| 320 | .base = 0x60000000, |
| 321 | .size = MPS3_DDR_SIZE, |
| 322 | .mpc = 2, |
| 323 | .mrindex = -1, |
| 324 | }, { |
| 325 | .name = NULL, |
| 326 | }, |
| 327 | }; |
| 328 | |
| 329 | static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) |
| 330 | { |
| 331 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 332 | const RAMInfo *p; |
| 333 | const RAMInfo *found = NULL; |
| 334 | |
| 335 | for (p = mmc->raminfo; p->name; p++) { |
| 336 | if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { |
| 337 | /* There should only be one entry in the array for this MPC */ |
| 338 | g_assert(!found); |
| 339 | found = p; |
| 340 | } |
| 341 | } |
| 342 | /* if raminfo array doesn't have an entry for each MPC this is a bug */ |
| 343 | assert(found); |
| 344 | return found; |
| 345 | } |
| 346 | |
| 347 | static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, |
| 348 | const RAMInfo *raminfo) |
| 349 | { |
| 350 | /* Return an initialized MemoryRegion for the RAMInfo. */ |
| 351 | MemoryRegion *ram; |
| 352 | |
| 353 | if (raminfo->mrindex < 0) { |
| 354 | /* Means this RAMInfo is for QEMU's "system memory" */ |
| 355 | MachineState *machine = MACHINE(mms); |
| 356 | assert(!(raminfo->flags & IS_ROM)); |
| 357 | return machine->ram; |
| 358 | } |
| 359 | |
| 360 | assert(raminfo->mrindex < MPS2TZ_RAM_MAX); |
| 361 | ram = &mms->ram[raminfo->mrindex]; |
| 362 | |
| 363 | memory_region_init_ram(ram, NULL, raminfo->name, |
| 364 | raminfo->size, &error_fatal); |
| 365 | if (raminfo->flags & IS_ROM) { |
| 366 | memory_region_set_readonly(ram, true); |
| 367 | } |
| 368 | return ram; |
| 369 | } |
| 370 | |
| 371 | /* Create an alias of an entire original MemoryRegion @orig |
| 372 | * located at @base in the memory map. |
| 373 | */ |
| 374 | static void make_ram_alias(MemoryRegion *mr, const char *name, |
| 375 | MemoryRegion *orig, hwaddr base) |
| 376 | { |
| 377 | memory_region_init_alias(mr, NULL, name, orig, 0, |
| 378 | memory_region_size(orig)); |
| 379 | memory_region_add_subregion(get_system_memory(), base, mr); |
| 380 | } |
| 381 | |
| 382 | static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) |
| 383 | { |
| 384 | /* |
| 385 | * Return a qemu_irq which will signal IRQ n to all CPUs in the |
| 386 | * SSE. The irqno should be as the CPU sees it, so the first |
| 387 | * external-to-the-SSE interrupt is 32. |
| 388 | */ |
| 389 | MachineClass *mc = MACHINE_GET_CLASS(mms); |
| 390 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 391 | |
| 392 | assert(irqno >= 32 && irqno < (mmc->numirq + 32)); |
| 393 | |
| 394 | /* |
| 395 | * Convert from "CPU irq number" (as listed in the FPGA image |
| 396 | * documentation) to the SSE external-interrupt number. |
| 397 | */ |
| 398 | irqno -= 32; |
| 399 | |
| 400 | if (mc->max_cpus > 1) { |
| 401 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); |
| 402 | } else { |
| 403 | return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | /* Union describing the device-specific extra data we pass to the devfn. */ |
| 408 | typedef union PPCExtraData { |
| 409 | bool i2c_internal; |
| 410 | } PPCExtraData; |
| 411 | |
| 412 | /* Most of the devices in the AN505 FPGA image sit behind |
| 413 | * Peripheral Protection Controllers. These data structures |
| 414 | * define the layout of which devices sit behind which PPCs. |
| 415 | * The devfn for each port is a function which creates, configures |
| 416 | * and initializes the device, returning the MemoryRegion which |
| 417 | * needs to be plugged into the downstream end of the PPC port. |
| 418 | */ |
| 419 | typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, |
| 420 | const char *name, hwaddr size, |
| 421 | const int *irqs, |
| 422 | const PPCExtraData *extradata); |
| 423 | |
| 424 | typedef struct PPCPortInfo { |
| 425 | const char *name; |
| 426 | MakeDevFn *devfn; |
| 427 | void *opaque; |
| 428 | hwaddr addr; |
| 429 | hwaddr size; |
| 430 | int irqs[3]; /* currently no device needs more IRQ lines than this */ |
| 431 | PPCExtraData extradata; /* to pass device-specific info to the devfn */ |
| 432 | } PPCPortInfo; |
| 433 | |
| 434 | typedef struct PPCInfo { |
| 435 | const char *name; |
| 436 | PPCPortInfo ports[TZ_NUM_PORTS]; |
| 437 | } PPCInfo; |
| 438 | |
| 439 | static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, |
| 440 | void *opaque, |
| 441 | const char *name, hwaddr size, |
| 442 | const int *irqs, |
| 443 | const PPCExtraData *extradata) |
| 444 | { |
| 445 | /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, |
| 446 | * and return a pointer to its MemoryRegion. |
| 447 | */ |
| 448 | UnimplementedDeviceState *uds = opaque; |
| 449 | |
| 450 | object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); |
| 451 | qdev_prop_set_string(DEVICE(uds), "name", name); |
| 452 | qdev_prop_set_uint64(DEVICE(uds), "size", size); |
| 453 | sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); |
| 454 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); |
| 455 | } |
| 456 | |
| 457 | static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, |
| 458 | const char *name, hwaddr size, |
| 459 | const int *irqs, const PPCExtraData *extradata) |
| 460 | { |
| 461 | /* The irq[] array is rx, tx, combined, in that order */ |
| 462 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 463 | CMSDKAPBUART *uart = opaque; |
| 464 | int i = uart - &mms->uart[0]; |
| 465 | SysBusDevice *s; |
| 466 | DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); |
| 467 | |
| 468 | object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); |
| 469 | qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); |
| 470 | qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); |
| 471 | sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); |
| 472 | s = SYS_BUS_DEVICE(uart); |
| 473 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1])); |
| 474 | sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0])); |
| 475 | sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); |
| 476 | sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); |
| 477 | sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); |
| 478 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); |
| 479 | } |
| 480 | |
| 481 | static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, |
| 482 | const char *name, hwaddr size, |
| 483 | const int *irqs, const PPCExtraData *extradata) |
| 484 | { |
| 485 | MPS2SCC *scc = opaque; |
| 486 | DeviceState *sccdev; |
| 487 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 488 | QList *oscclk; |
| 489 | uint32_t i; |
| 490 | |
| 491 | object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); |
| 492 | sccdev = DEVICE(scc); |
| 493 | qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); |
| 494 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
| 495 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
| 496 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
| 497 | |
| 498 | oscclk = qlist_new(); |
| 499 | for (i = 0; i < mmc->len_oscclk; i++) { |
| 500 | qlist_append_int(oscclk, mmc->oscclk[i]); |
| 501 | } |
| 502 | qdev_prop_set_array(sccdev, "oscclk", oscclk); |
| 503 | |
| 504 | sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); |
| 505 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); |
| 506 | } |
| 507 | |
| 508 | static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, |
| 509 | const char *name, hwaddr size, |
| 510 | const int *irqs, const PPCExtraData *extradata) |
| 511 | { |
| 512 | MPS2FPGAIO *fpgaio = opaque; |
| 513 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 514 | |
| 515 | object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); |
| 516 | qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); |
| 517 | qdev_prop_set_bit(DEVICE(fpgaio), "has-switches", mmc->fpgaio_has_switches); |
| 518 | qdev_prop_set_bit(DEVICE(fpgaio), "has-dbgctrl", mmc->fpgaio_has_dbgctrl); |
| 519 | qdev_prop_set_bit(DEVICE(fpgaio), "has-gpioalt2", mmc->fpgaio_has_gpioalt2); |
| 520 | sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); |
| 521 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); |
| 522 | } |
| 523 | |
| 524 | static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, |
| 525 | const char *name, hwaddr size, |
| 526 | const int *irqs, |
| 527 | const PPCExtraData *extradata) |
| 528 | { |
| 529 | SysBusDevice *s; |
| 530 | |
| 531 | /* In hardware this is a LAN9220; the LAN9118 is software compatible |
| 532 | * except that it doesn't support the checksum-offload feature. |
| 533 | */ |
| 534 | mms->lan9118 = qdev_new(TYPE_LAN9118); |
| 535 | qemu_configure_nic_device(mms->lan9118, true, NULL); |
| 536 | |
| 537 | s = SYS_BUS_DEVICE(mms->lan9118); |
| 538 | sysbus_realize_and_unref(s, &error_fatal); |
| 539 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
| 540 | return sysbus_mmio_get_region(s, 0); |
| 541 | } |
| 542 | |
| 543 | static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, |
| 544 | const char *name, hwaddr size, |
| 545 | const int *irqs, |
| 546 | const PPCExtraData *extradata) |
| 547 | { |
| 548 | /* |
| 549 | * The AN524 makes the ethernet and USB share a PPC port. |
| 550 | * irqs[] is the ethernet IRQ. |
| 551 | */ |
| 552 | SysBusDevice *s; |
| 553 | |
| 554 | memory_region_init(&mms->eth_usb_container, OBJECT(mms), |
| 555 | "mps2-tz-eth-usb-container", 0x200000); |
| 556 | |
| 557 | /* |
| 558 | * In hardware this is a LAN9220; the LAN9118 is software compatible |
| 559 | * except that it doesn't support the checksum-offload feature. |
| 560 | */ |
| 561 | mms->lan9118 = qdev_new(TYPE_LAN9118); |
| 562 | qemu_configure_nic_device(mms->lan9118, true, NULL); |
| 563 | |
| 564 | s = SYS_BUS_DEVICE(mms->lan9118); |
| 565 | sysbus_realize_and_unref(s, &error_fatal); |
| 566 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
| 567 | |
| 568 | memory_region_add_subregion(&mms->eth_usb_container, |
| 569 | 0, sysbus_mmio_get_region(s, 0)); |
| 570 | |
| 571 | /* The USB OTG controller is an ISP1763; we don't have a model of it. */ |
| 572 | object_initialize_child(OBJECT(mms), "usb-otg", |
| 573 | &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); |
| 574 | qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); |
| 575 | qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); |
| 576 | s = SYS_BUS_DEVICE(&mms->usb); |
| 577 | sysbus_realize(s, &error_fatal); |
| 578 | |
| 579 | memory_region_add_subregion(&mms->eth_usb_container, |
| 580 | 0x100000, sysbus_mmio_get_region(s, 0)); |
| 581 | |
| 582 | return &mms->eth_usb_container; |
| 583 | } |
| 584 | |
| 585 | static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, |
| 586 | const char *name, hwaddr size, |
| 587 | const int *irqs, const PPCExtraData *extradata) |
| 588 | { |
| 589 | TZMPC *mpc = opaque; |
| 590 | int i = mpc - &mms->mpc[0]; |
| 591 | MemoryRegion *upstream; |
| 592 | const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); |
| 593 | MemoryRegion *ram = mr_for_raminfo(mms, raminfo); |
| 594 | |
| 595 | object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); |
| 596 | object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), |
| 597 | &error_fatal); |
| 598 | sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); |
| 599 | /* Map the upstream end of the MPC into system memory */ |
| 600 | upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); |
| 601 | memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); |
| 602 | /* and connect its interrupt to the IoTKit */ |
| 603 | qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, |
| 604 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), |
| 605 | "mpcexp_status", i)); |
| 606 | |
| 607 | /* Return the register interface MR for our caller to map behind the PPC */ |
| 608 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); |
| 609 | } |
| 610 | |
| 611 | static hwaddr boot_mem_base(MPS2TZMachineState *mms) |
| 612 | { |
| 613 | /* |
| 614 | * Return the canonical address of the block which will be mapped |
| 615 | * at address 0x0 (i.e. where the vector table is). |
| 616 | * This is usually 0, but if the AN524 alternate memory map is |
| 617 | * enabled it will be the base address of the QSPI block. |
| 618 | */ |
| 619 | return mms->remap ? 0x28000000 : 0; |
| 620 | } |
| 621 | |
| 622 | static void remap_memory(MPS2TZMachineState *mms, int map) |
| 623 | { |
| 624 | /* |
| 625 | * Remap the memory for the AN524. 'map' is the value of |
| 626 | * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 |
| 627 | * for the "option 1" mapping where QSPI is at address 0. |
| 628 | * |
| 629 | * Effectively we need to swap around the "upstream" ends of |
| 630 | * MPC 0 and MPC 1. |
| 631 | */ |
| 632 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 633 | int i; |
| 634 | |
| 635 | if (mmc->fpga_type != FPGA_AN524) { |
| 636 | return; |
| 637 | } |
| 638 | |
| 639 | memory_region_transaction_begin(); |
| 640 | for (i = 0; i < 2; i++) { |
| 641 | TZMPC *mpc = &mms->mpc[i]; |
| 642 | MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); |
| 643 | hwaddr addr = (i ^ map) ? 0x28000000 : 0; |
| 644 | |
| 645 | memory_region_set_address(upstream, addr); |
| 646 | } |
| 647 | memory_region_transaction_commit(); |
| 648 | } |
| 649 | |
| 650 | static void remap_irq_fn(void *opaque, int n, int level) |
| 651 | { |
| 652 | MPS2TZMachineState *mms = opaque; |
| 653 | |
| 654 | remap_memory(mms, level); |
| 655 | } |
| 656 | |
| 657 | static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, |
| 658 | const char *name, hwaddr size, |
| 659 | const int *irqs, const PPCExtraData *extradata) |
| 660 | { |
| 661 | /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ |
| 662 | PL080State *dma = opaque; |
| 663 | int i = dma - &mms->dma[0]; |
| 664 | SysBusDevice *s; |
| 665 | char *mscname = g_strdup_printf("%s-msc", name); |
| 666 | TZMSC *msc = &mms->msc[i]; |
| 667 | DeviceState *iotkitdev = DEVICE(&mms->iotkit); |
| 668 | MemoryRegion *msc_upstream; |
| 669 | MemoryRegion *msc_downstream; |
| 670 | |
| 671 | /* |
| 672 | * Each DMA device is a PL081 whose transaction master interface |
| 673 | * is guarded by a Master Security Controller. The downstream end of |
| 674 | * the MSC connects to the IoTKit AHB Slave Expansion port, so the |
| 675 | * DMA devices can see all devices and memory that the CPU does. |
| 676 | */ |
| 677 | object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); |
| 678 | msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); |
| 679 | object_property_set_link(OBJECT(msc), "downstream", |
| 680 | OBJECT(msc_downstream), &error_fatal); |
| 681 | object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); |
| 682 | sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); |
| 683 | |
| 684 | qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, |
| 685 | qdev_get_gpio_in_named(iotkitdev, |
| 686 | "mscexp_status", i)); |
| 687 | qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, |
| 688 | qdev_get_gpio_in_named(DEVICE(msc), |
| 689 | "irq_clear", 0)); |
| 690 | qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, |
| 691 | qdev_get_gpio_in_named(DEVICE(msc), |
| 692 | "cfg_nonsec", 0)); |
| 693 | qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), |
| 694 | ARRAY_SIZE(mms->ppc) + i, |
| 695 | qdev_get_gpio_in_named(DEVICE(msc), |
| 696 | "cfg_sec_resp", 0)); |
| 697 | msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); |
| 698 | |
| 699 | object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); |
| 700 | object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), |
| 701 | &error_fatal); |
| 702 | sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); |
| 703 | |
| 704 | s = SYS_BUS_DEVICE(dma); |
| 705 | /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ |
| 706 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
| 707 | sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); |
| 708 | sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); |
| 709 | |
| 710 | g_free(mscname); |
| 711 | return sysbus_mmio_get_region(s, 0); |
| 712 | } |
| 713 | |
| 714 | static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, |
| 715 | const char *name, hwaddr size, |
| 716 | const int *irqs, const PPCExtraData *extradata) |
| 717 | { |
| 718 | /* |
| 719 | * The AN505 has five PL022 SPI controllers. |
| 720 | * One of these should have the LCD controller behind it; the others |
| 721 | * are connected only to the FPGA's "general purpose SPI connector" |
| 722 | * or "shield" expansion connectors. |
| 723 | * Note that if we do implement devices behind SPI, the chip select |
| 724 | * lines are set via the "MISC" register in the MPS2 FPGAIO device. |
| 725 | */ |
| 726 | PL022State *spi = opaque; |
| 727 | SysBusDevice *s; |
| 728 | |
| 729 | object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); |
| 730 | sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); |
| 731 | s = SYS_BUS_DEVICE(spi); |
| 732 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); |
| 733 | return sysbus_mmio_get_region(s, 0); |
| 734 | } |
| 735 | |
| 736 | static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, |
| 737 | const char *name, hwaddr size, |
| 738 | const int *irqs, const PPCExtraData *extradata) |
| 739 | { |
| 740 | ArmSbconI2CState *i2c = opaque; |
| 741 | SysBusDevice *s; |
| 742 | |
| 743 | object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); |
| 744 | s = SYS_BUS_DEVICE(i2c); |
| 745 | sysbus_realize(s, &error_fatal); |
| 746 | |
| 747 | /* |
| 748 | * If this is an internal-use-only i2c bus, mark it full |
| 749 | * so that user-created i2c devices are not plugged into it. |
| 750 | * If we implement models of any on-board i2c devices that |
| 751 | * plug in to one of the internal-use-only buses, then we will |
| 752 | * need to create and plugging those in here before we mark the |
| 753 | * bus as full. |
| 754 | */ |
| 755 | if (extradata->i2c_internal) { |
| 756 | BusState *qbus = qdev_get_child_bus(DEVICE(i2c), "i2c"); |
| 757 | qbus_mark_full(qbus); |
| 758 | } |
| 759 | |
| 760 | return sysbus_mmio_get_region(s, 0); |
| 761 | } |
| 762 | |
| 763 | static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, |
| 764 | const char *name, hwaddr size, |
| 765 | const int *irqs, const PPCExtraData *extradata) |
| 766 | { |
| 767 | PL031State *pl031 = opaque; |
| 768 | SysBusDevice *s; |
| 769 | |
| 770 | object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); |
| 771 | s = SYS_BUS_DEVICE(pl031); |
| 772 | sysbus_realize(s, &error_fatal); |
| 773 | /* |
| 774 | * The board docs don't give an IRQ number for the PL031, so |
| 775 | * presumably it is not connected. |
| 776 | */ |
| 777 | return sysbus_mmio_get_region(s, 0); |
| 778 | } |
| 779 | |
| 780 | static void create_non_mpc_ram(MPS2TZMachineState *mms) |
| 781 | { |
| 782 | /* |
| 783 | * Handle the RAMs which are either not behind MPCs or which are |
| 784 | * aliases to another MPC. |
| 785 | */ |
| 786 | const RAMInfo *p; |
| 787 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 788 | |
| 789 | for (p = mmc->raminfo; p->name; p++) { |
| 790 | if (p->flags & IS_ALIAS) { |
| 791 | SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); |
| 792 | MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); |
| 793 | make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); |
| 794 | } else if (p->mpc == -1) { |
| 795 | /* RAM not behind an MPC */ |
| 796 | MemoryRegion *mr = mr_for_raminfo(mms, p); |
| 797 | memory_region_add_subregion(get_system_memory(), p->base, mr); |
| 798 | } |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | static uint32_t boot_ram_size(MPS2TZMachineState *mms) |
| 803 | { |
| 804 | /* Return the size of the RAM block at guest address zero */ |
| 805 | const RAMInfo *p; |
| 806 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 807 | |
| 808 | /* |
| 809 | * Use a per-board specification (for when the boot RAM is in |
| 810 | * the SSE and so doesn't have a RAMInfo list entry) |
| 811 | */ |
| 812 | if (mmc->boot_ram_size) { |
| 813 | return mmc->boot_ram_size; |
| 814 | } |
| 815 | |
| 816 | for (p = mmc->raminfo; p->name; p++) { |
| 817 | if (p->base == boot_mem_base(mms)) { |
| 818 | return p->size; |
| 819 | } |
| 820 | } |
| 821 | g_assert_not_reached(); |
| 822 | } |
| 823 | |
| 824 | static void mps2tz_common_init(MachineState *machine) |
| 825 | { |
| 826 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); |
| 827 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
| 828 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 829 | MemoryRegion *system_memory = get_system_memory(); |
| 830 | DeviceState *iotkitdev; |
| 831 | DeviceState *dev_splitter; |
| 832 | const PPCInfo *ppcs; |
| 833 | int num_ppcs; |
| 834 | int i; |
| 835 | |
| 836 | if (machine->ram_size != mc->default_ram_size) { |
| 837 | char *sz = size_to_str(mc->default_ram_size); |
| 838 | error_report("Invalid RAM size, should be %s", sz); |
| 839 | g_free(sz); |
| 840 | exit(EXIT_FAILURE); |
| 841 | } |
| 842 | |
| 843 | /* These clocks don't need migration because they are fixed-frequency */ |
| 844 | mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); |
| 845 | clock_set_hz(mms->sysclk, mmc->sysclk_frq); |
| 846 | mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); |
| 847 | clock_set_hz(mms->s32kclk, S32KCLK_FRQ); |
| 848 | |
| 849 | object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, |
| 850 | mmc->armsse_type); |
| 851 | iotkitdev = DEVICE(&mms->iotkit); |
| 852 | object_property_set_link(OBJECT(&mms->iotkit), "memory", |
| 853 | OBJECT(system_memory), &error_abort); |
| 854 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); |
| 855 | qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); |
| 856 | if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { |
| 857 | qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); |
| 858 | } |
| 859 | if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { |
| 860 | qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); |
| 861 | } |
| 862 | if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { |
| 863 | if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { |
| 864 | qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); |
| 865 | } |
| 866 | if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { |
| 867 | qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); |
| 868 | } |
| 869 | } |
| 870 | qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); |
| 871 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); |
| 872 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); |
| 873 | sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); |
| 874 | |
| 875 | /* |
| 876 | * If this board has more than one CPU, then we need to create splitters |
| 877 | * to feed the IRQ inputs for each CPU in the SSE from each device in the |
| 878 | * board. If there is only one CPU, we can just wire the device IRQ |
| 879 | * directly to the SSE's IRQ input. |
| 880 | */ |
| 881 | assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); |
| 882 | if (mc->max_cpus > 1) { |
| 883 | for (i = 0; i < mmc->numirq; i++) { |
| 884 | char *name = g_strdup_printf("mps2-irq-splitter%d", i); |
| 885 | SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; |
| 886 | |
| 887 | object_initialize_child_with_props(OBJECT(machine), name, |
| 888 | splitter, sizeof(*splitter), |
| 889 | TYPE_SPLIT_IRQ, &error_fatal, |
| 890 | NULL); |
| 891 | g_free(name); |
| 892 | |
| 893 | object_property_set_int(OBJECT(splitter), "num-lines", 2, |
| 894 | &error_fatal); |
| 895 | qdev_realize(DEVICE(splitter), NULL, &error_fatal); |
| 896 | qdev_connect_gpio_out(DEVICE(splitter), 0, |
| 897 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), |
| 898 | "EXP_IRQ", i)); |
| 899 | qdev_connect_gpio_out(DEVICE(splitter), 1, |
| 900 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), |
| 901 | "EXP_CPU1_IRQ", i)); |
| 902 | } |
| 903 | } |
| 904 | |
| 905 | /* The sec_resp_cfg output from the IoTKit must be split into multiple |
| 906 | * lines, one for each of the PPCs we create here, plus one per MSC. |
| 907 | */ |
| 908 | object_initialize_child(OBJECT(machine), "sec-resp-splitter", |
| 909 | &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); |
| 910 | object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", |
| 911 | ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), |
| 912 | &error_fatal); |
| 913 | qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); |
| 914 | dev_splitter = DEVICE(&mms->sec_resp_splitter); |
| 915 | qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, |
| 916 | qdev_get_gpio_in(dev_splitter, 0)); |
| 917 | |
| 918 | /* |
| 919 | * The IoTKit sets up much of the memory layout, including |
| 920 | * the aliases between secure and non-secure regions in the |
| 921 | * address space, and also most of the devices in the system. |
| 922 | * The FPGA itself contains various RAMs and some additional devices. |
| 923 | * The FPGA images have an odd combination of different RAMs, |
| 924 | * because in hardware they are different implementations and |
| 925 | * connected to different buses, giving varying performance/size |
| 926 | * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily |
| 927 | * call the largest lump our "system memory". |
| 928 | */ |
| 929 | |
| 930 | /* |
| 931 | * The overflow IRQs for all UARTs are ORed together. |
| 932 | * Tx, Rx and "combined" IRQs are sent to the NVIC separately. |
| 933 | * Create the OR gate for this: it has one input for the TX overflow |
| 934 | * and one for the RX overflow for each UART we might have. |
| 935 | * (If the board has fewer than the maximum possible number of UARTs |
| 936 | * those inputs are never wired up and are treated as always-zero.) |
| 937 | */ |
| 938 | object_initialize_child(OBJECT(mms), "uart-irq-orgate", |
| 939 | &mms->uart_irq_orgate, TYPE_OR_IRQ); |
| 940 | object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", |
| 941 | 2 * ARRAY_SIZE(mms->uart), |
| 942 | &error_fatal); |
| 943 | qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); |
| 944 | qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, |
| 945 | get_sse_irq_in(mms, mmc->uart_overflow_irq)); |
| 946 | |
| 947 | /* Most of the devices in the FPGA are behind Peripheral Protection |
| 948 | * Controllers. The required order for initializing things is: |
| 949 | * + initialize the PPC |
| 950 | * + initialize, configure and realize downstream devices |
| 951 | * + connect downstream device MemoryRegions to the PPC |
| 952 | * + realize the PPC |
| 953 | * + map the PPC's MemoryRegions to the places in the address map |
| 954 | * where the downstream devices should appear |
| 955 | * + wire up the PPC's control lines to the IoTKit object |
| 956 | */ |
| 957 | |
| 958 | const PPCInfo an505_ppcs[] = { { |
| 959 | .name = "apb_ppcexp0", |
| 960 | .ports = { |
| 961 | { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, |
| 962 | { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, |
| 963 | { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, |
| 964 | }, |
| 965 | }, { |
| 966 | .name = "apb_ppcexp1", |
| 967 | .ports = { |
| 968 | { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, |
| 969 | { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, |
| 970 | { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, |
| 971 | { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, |
| 972 | { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, |
| 973 | { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, |
| 974 | { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, |
| 975 | { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, |
| 976 | { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, |
| 977 | { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, |
| 978 | { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000, {}, |
| 979 | { .i2c_internal = true /* touchscreen */ } }, |
| 980 | { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000, {}, |
| 981 | { .i2c_internal = true /* audio conf */ } }, |
| 982 | { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000, {}, |
| 983 | { .i2c_internal = false /* shield 0 */ } }, |
| 984 | { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000, {}, |
| 985 | { .i2c_internal = false /* shield 1 */ } }, |
| 986 | }, |
| 987 | }, { |
| 988 | .name = "apb_ppcexp2", |
| 989 | .ports = { |
| 990 | { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, |
| 991 | { "i2s-audio", make_unimp_dev, &mms->i2s_audio, |
| 992 | 0x40301000, 0x1000 }, |
| 993 | { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, |
| 994 | }, |
| 995 | }, { |
| 996 | .name = "ahb_ppcexp0", |
| 997 | .ports = { |
| 998 | { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, |
| 999 | { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, |
| 1000 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, |
| 1001 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, |
| 1002 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, |
| 1003 | { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, |
| 1004 | }, |
| 1005 | }, { |
| 1006 | .name = "ahb_ppcexp1", |
| 1007 | .ports = { |
| 1008 | { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, |
| 1009 | { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, |
| 1010 | { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, |
| 1011 | { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, |
| 1012 | }, |
| 1013 | }, |
| 1014 | }; |
| 1015 | |
| 1016 | const PPCInfo an524_ppcs[] = { { |
| 1017 | .name = "apb_ppcexp0", |
| 1018 | .ports = { |
| 1019 | { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, |
| 1020 | { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, |
| 1021 | { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, |
| 1022 | }, |
| 1023 | }, { |
| 1024 | .name = "apb_ppcexp1", |
| 1025 | .ports = { |
| 1026 | { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000, {}, |
| 1027 | { .i2c_internal = true /* touchscreen */ } }, |
| 1028 | { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000, {}, |
| 1029 | { .i2c_internal = true /* audio conf */ } }, |
| 1030 | { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, |
| 1031 | { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, |
| 1032 | { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, |
| 1033 | { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000, {}, |
| 1034 | { .i2c_internal = false /* shield 0 */ } }, |
| 1035 | { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000, {}, |
| 1036 | { .i2c_internal = false /* shield 1 */ } }, |
| 1037 | { /* port 7 reserved */ }, |
| 1038 | { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000, {}, |
| 1039 | { .i2c_internal = true /* DDR4 EEPROM */ } }, |
| 1040 | }, |
| 1041 | }, { |
| 1042 | .name = "apb_ppcexp2", |
| 1043 | .ports = { |
| 1044 | { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, |
| 1045 | { "i2s-audio", make_unimp_dev, &mms->i2s_audio, |
| 1046 | 0x41301000, 0x1000 }, |
| 1047 | { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, |
| 1048 | { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, |
| 1049 | { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, |
| 1050 | { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, |
| 1051 | { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, |
| 1052 | { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, |
| 1053 | { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, |
| 1054 | { /* port 9 reserved */ }, |
| 1055 | { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, |
| 1056 | { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, |
| 1057 | }, |
| 1058 | }, { |
| 1059 | .name = "ahb_ppcexp0", |
| 1060 | .ports = { |
| 1061 | { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, |
| 1062 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
| 1063 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
| 1064 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, |
| 1065 | { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, |
| 1066 | }, |
| 1067 | }, |
| 1068 | }; |
| 1069 | |
| 1070 | const PPCInfo an547_ppcs[] = { { |
| 1071 | .name = "apb_ppcexp0", |
| 1072 | .ports = { |
| 1073 | { /* port 0 USER MEM APB0 */ }, |
| 1074 | { /* port 1 USER MEM APB0 */ }, |
| 1075 | { /* port 2 reserved */ }, |
| 1076 | { /* port 3 reserved */ }, |
| 1077 | { /* port 4 NPU APB0 */ }, |
| 1078 | { /* port 5 NPU APB1 */ }, |
| 1079 | { /* port 6 reserved */ }, |
| 1080 | { /* port 7 reserved */ }, |
| 1081 | { /* port 8 reserved */ }, |
| 1082 | { /* port 9 reserved */ }, |
| 1083 | { /* port 10 reserved */ }, |
| 1084 | { /* port 11 reserved */ }, |
| 1085 | { /* port 12 reserved */ }, |
| 1086 | { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 }, |
| 1087 | { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, |
| 1088 | { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, |
| 1089 | }, |
| 1090 | }, { |
| 1091 | .name = "apb_ppcexp1", |
| 1092 | .ports = { |
| 1093 | { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, |
| 1094 | { .i2c_internal = true /* touchscreen */ } }, |
| 1095 | { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, |
| 1096 | { .i2c_internal = true /* audio conf */ } }, |
| 1097 | { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, |
| 1098 | { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, |
| 1099 | { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, |
| 1100 | { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, |
| 1101 | { .i2c_internal = false /* shield 0 */ } }, |
| 1102 | { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, |
| 1103 | { .i2c_internal = false /* shield 1 */ } }, |
| 1104 | { /* port 7 reserved */ }, |
| 1105 | { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, |
| 1106 | { .i2c_internal = true /* DDR4 EEPROM */ } }, |
| 1107 | }, |
| 1108 | }, { |
| 1109 | .name = "apb_ppcexp2", |
| 1110 | .ports = { |
| 1111 | { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, |
| 1112 | { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, |
| 1113 | { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, |
| 1114 | { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, |
| 1115 | { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, |
| 1116 | { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, |
| 1117 | { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, |
| 1118 | { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, |
| 1119 | { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, |
| 1120 | { /* port 9 reserved */ }, |
| 1121 | { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, |
| 1122 | { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, |
| 1123 | }, |
| 1124 | }, { |
| 1125 | .name = "ahb_ppcexp0", |
| 1126 | .ports = { |
| 1127 | { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, |
| 1128 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
| 1129 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
| 1130 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, |
| 1131 | { /* port 4 USER AHB interface 0 */ }, |
| 1132 | { /* port 5 USER AHB interface 1 */ }, |
| 1133 | { /* port 6 USER AHB interface 2 */ }, |
| 1134 | { /* port 7 USER AHB interface 3 */ }, |
| 1135 | { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, |
| 1136 | }, |
| 1137 | }, { |
| 1138 | .name = "ahb_ppcexp1", |
| 1139 | .ports = { |
| 1140 | { /* port 0 reserved */ }, |
| 1141 | { "dma1", make_dma, &mms->dma[1], 0x41201000, 0x1000, { 62, 60, 61 } }, |
| 1142 | { "dma2", make_dma, &mms->dma[2], 0x41202000, 0x1000, { 65, 63, 64 } }, |
| 1143 | { "dma3", make_dma, &mms->dma[3], 0x41203000, 0x1000, { 68, 66, 67 } }, |
| 1144 | }, |
| 1145 | }, |
| 1146 | }; |
| 1147 | |
| 1148 | const PPCInfo an555_ppcs[] = { { |
| 1149 | .name = "apb_ppcexp0", |
| 1150 | .ports = { |
| 1151 | { "sram-timing-adapter", make_unimp_dev, &mms->ta[0], 0x41700000, 0x1000 }, |
| 1152 | { "qspi-timing-adapter", make_unimp_dev, &mms->ta[1], 0x41701000, 0x1000 }, |
| 1153 | { "ddr4-timing-adapter", make_unimp_dev, &mms->ta[2], 0x41702000, 0x1000 }, |
| 1154 | }, |
| 1155 | }, { |
| 1156 | .name = "apb_ppcexp1", |
| 1157 | .ports = { |
| 1158 | { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000, {}, |
| 1159 | { .i2c_internal = true /* touchscreen */ } }, |
| 1160 | { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000, {}, |
| 1161 | { .i2c_internal = true /* audio conf */ } }, |
| 1162 | { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53 } }, |
| 1163 | { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54 } }, |
| 1164 | { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55 } }, |
| 1165 | { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000, {}, |
| 1166 | { .i2c_internal = false /* shield 0 */ } }, |
| 1167 | { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000, {}, |
| 1168 | { .i2c_internal = false /* shield 1 */ } }, |
| 1169 | { /* port 7 reserved */ }, |
| 1170 | { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000, {}, |
| 1171 | { .i2c_internal = true /* DDR4 EEPROM */ } }, |
| 1172 | }, |
| 1173 | }, { |
| 1174 | .name = "apb_ppcexp2", |
| 1175 | .ports = { |
| 1176 | { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, |
| 1177 | { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000, 0x1000 }, |
| 1178 | { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 }, |
| 1179 | { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, { 33, 34, 43 } }, |
| 1180 | { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, { 35, 36, 44 } }, |
| 1181 | { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, { 37, 38, 45 } }, |
| 1182 | { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, { 39, 40, 46 } }, |
| 1183 | { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, { 41, 42, 47 } }, |
| 1184 | { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, { 125, 126, 127 } }, |
| 1185 | { /* port 9 reserved */ }, |
| 1186 | { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, |
| 1187 | { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, |
| 1188 | }, |
| 1189 | }, { |
| 1190 | .name = "ahb_ppcexp0", |
| 1191 | .ports = { |
| 1192 | { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, |
| 1193 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, |
| 1194 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, |
| 1195 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, |
| 1196 | { /* port 4 USER AHB interface 0 */ }, |
| 1197 | { /* port 5 USER AHB interface 1 */ }, |
| 1198 | { /* port 6 USER AHB interface 2 */ }, |
| 1199 | { /* port 7 USER AHB interface 3 */ }, |
| 1200 | { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } }, |
| 1201 | { /* port 9 reserved */ }, |
| 1202 | { /* port 10 reserved */ }, |
| 1203 | { /* port 11 reserved */ }, |
| 1204 | { /* port 12 reserved */ }, |
| 1205 | { "qspi-controller0", make_unimp_dev, &mms->qspi_controller[0], |
| 1206 | 0x41800000, 0x1000 }, |
| 1207 | { "qspi-controller1", make_unimp_dev, &mms->qspi_controller[1], |
| 1208 | 0x41801000, 0x1000 }, |
| 1209 | { "qspi-controller2", make_unimp_dev, &mms->qspi_controller[2], |
| 1210 | 0x41802000, 0x1000 }, |
| 1211 | }, |
| 1212 | }, { |
| 1213 | .name = "ahb_ppcexp1", |
| 1214 | .ports = { |
| 1215 | { "dma0", make_dma, &mms->dma[0], 0x41200000, 0x1000, { 59, 57, 58 } }, |
| 1216 | { "dma1", make_dma, &mms->dma[1], 0x41201000, 0x1000, { 62, 60, 61 } }, |
| 1217 | { "dma2", make_dma, &mms->dma[2], 0x41202000, 0x1000, { 65, 63, 64 } }, |
| 1218 | { "dma3", make_dma, &mms->dma[3], 0x41203000, 0x1000, { 68, 66, 67 } }, |
| 1219 | }, |
| 1220 | }, |
| 1221 | }; |
| 1222 | |
| 1223 | switch (mmc->fpga_type) { |
| 1224 | case FPGA_AN505: |
| 1225 | case FPGA_AN521: |
| 1226 | ppcs = an505_ppcs; |
| 1227 | num_ppcs = ARRAY_SIZE(an505_ppcs); |
| 1228 | break; |
| 1229 | case FPGA_AN524: |
| 1230 | ppcs = an524_ppcs; |
| 1231 | num_ppcs = ARRAY_SIZE(an524_ppcs); |
| 1232 | break; |
| 1233 | case FPGA_AN547: |
| 1234 | ppcs = an547_ppcs; |
| 1235 | num_ppcs = ARRAY_SIZE(an547_ppcs); |
| 1236 | break; |
| 1237 | case FPGA_AN555: |
| 1238 | ppcs = an555_ppcs; |
| 1239 | num_ppcs = ARRAY_SIZE(an555_ppcs); |
| 1240 | break; |
| 1241 | default: |
| 1242 | g_assert_not_reached(); |
| 1243 | } |
| 1244 | |
| 1245 | for (i = 0; i < num_ppcs; i++) { |
| 1246 | const PPCInfo *ppcinfo = &ppcs[i]; |
| 1247 | TZPPC *ppc = &mms->ppc[i]; |
| 1248 | DeviceState *ppcdev; |
| 1249 | int port; |
| 1250 | char *gpioname; |
| 1251 | |
| 1252 | object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, |
| 1253 | TYPE_TZ_PPC); |
| 1254 | ppcdev = DEVICE(ppc); |
| 1255 | |
| 1256 | for (port = 0; port < TZ_NUM_PORTS; port++) { |
| 1257 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; |
| 1258 | MemoryRegion *mr; |
| 1259 | char *portname; |
| 1260 | |
| 1261 | if (!pinfo->devfn) { |
| 1262 | continue; |
| 1263 | } |
| 1264 | |
| 1265 | mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, |
| 1266 | pinfo->irqs, &pinfo->extradata); |
| 1267 | portname = g_strdup_printf("port[%d]", port); |
| 1268 | object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), |
| 1269 | &error_fatal); |
| 1270 | g_free(portname); |
| 1271 | } |
| 1272 | |
| 1273 | sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); |
| 1274 | |
| 1275 | for (port = 0; port < TZ_NUM_PORTS; port++) { |
| 1276 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; |
| 1277 | |
| 1278 | if (!pinfo->devfn) { |
| 1279 | continue; |
| 1280 | } |
| 1281 | sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); |
| 1282 | |
| 1283 | gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); |
| 1284 | qdev_connect_gpio_out_named(iotkitdev, gpioname, port, |
| 1285 | qdev_get_gpio_in_named(ppcdev, |
| 1286 | "cfg_nonsec", |
| 1287 | port)); |
| 1288 | g_free(gpioname); |
| 1289 | gpioname = g_strdup_printf("%s_ap", ppcinfo->name); |
| 1290 | qdev_connect_gpio_out_named(iotkitdev, gpioname, port, |
| 1291 | qdev_get_gpio_in_named(ppcdev, |
| 1292 | "cfg_ap", port)); |
| 1293 | g_free(gpioname); |
| 1294 | } |
| 1295 | |
| 1296 | gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); |
| 1297 | qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, |
| 1298 | qdev_get_gpio_in_named(ppcdev, |
| 1299 | "irq_enable", 0)); |
| 1300 | g_free(gpioname); |
| 1301 | gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); |
| 1302 | qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, |
| 1303 | qdev_get_gpio_in_named(ppcdev, |
| 1304 | "irq_clear", 0)); |
| 1305 | g_free(gpioname); |
| 1306 | gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); |
| 1307 | qdev_connect_gpio_out_named(ppcdev, "irq", 0, |
| 1308 | qdev_get_gpio_in_named(iotkitdev, |
| 1309 | gpioname, 0)); |
| 1310 | g_free(gpioname); |
| 1311 | |
| 1312 | qdev_connect_gpio_out(dev_splitter, i, |
| 1313 | qdev_get_gpio_in_named(ppcdev, |
| 1314 | "cfg_sec_resp", 0)); |
| 1315 | } |
| 1316 | |
| 1317 | create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); |
| 1318 | |
| 1319 | if (mmc->fpga_type == FPGA_AN547) { |
| 1320 | create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x1000); |
| 1321 | create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x1000); |
| 1322 | } |
| 1323 | |
| 1324 | if (mmc->fpga_type == FPGA_AN555) { |
| 1325 | create_unimplemented_device("SRAM MPC", 0x57000000, 0x1000); |
| 1326 | create_unimplemented_device("QSPI MPC", 0x57001000, 0x1000); |
| 1327 | create_unimplemented_device("DDR4 MPC", 0x57002000, 0x1000); |
| 1328 | } |
| 1329 | |
| 1330 | create_non_mpc_ram(mms); |
| 1331 | |
| 1332 | if (mmc->fpga_type == FPGA_AN524) { |
| 1333 | /* |
| 1334 | * Connect the line from the SCC so that we can remap when the |
| 1335 | * guest updates that register. |
| 1336 | */ |
| 1337 | mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); |
| 1338 | qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, |
| 1339 | mms->remap_irq); |
| 1340 | } |
| 1341 | |
| 1342 | armv7m_load_kernel(mms->iotkit.armv7m[0].cpu, machine->kernel_filename, |
| 1343 | 0, boot_ram_size(mms)); |
| 1344 | } |
| 1345 | |
| 1346 | static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, |
| 1347 | int *iregion, bool *exempt, bool *ns, bool *nsc) |
| 1348 | { |
| 1349 | /* |
| 1350 | * The MPS2 TZ FPGA images have IDAUs in them which are connected to |
| 1351 | * the Master Security Controllers. These have the same logic as |
| 1352 | * is used by the IoTKit for the IDAU connected to the CPU, except |
| 1353 | * that MSCs don't care about the NSC attribute. |
| 1354 | */ |
| 1355 | int region = extract32(address, 28, 4); |
| 1356 | |
| 1357 | *ns = !(region & 1); |
| 1358 | *nsc = false; |
| 1359 | /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ |
| 1360 | *exempt = (address & 0xeff00000) == 0xe0000000; |
| 1361 | *iregion = region; |
| 1362 | } |
| 1363 | |
| 1364 | static char *mps2_get_remap(Object *obj, Error **errp) |
| 1365 | { |
| 1366 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); |
| 1367 | const char *val = mms->remap ? "QSPI" : "BRAM"; |
| 1368 | return g_strdup(val); |
| 1369 | } |
| 1370 | |
| 1371 | static void mps2_set_remap(Object *obj, const char *value, Error **errp) |
| 1372 | { |
| 1373 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); |
| 1374 | |
| 1375 | if (!strcmp(value, "BRAM")) { |
| 1376 | mms->remap = false; |
| 1377 | } else if (!strcmp(value, "QSPI")) { |
| 1378 | mms->remap = true; |
| 1379 | } else { |
| 1380 | error_setg(errp, "Invalid remap value"); |
| 1381 | error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); |
| 1382 | } |
| 1383 | } |
| 1384 | |
| 1385 | static void mps2_machine_reset(MachineState *machine, ResetType type) |
| 1386 | { |
| 1387 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); |
| 1388 | |
| 1389 | /* |
| 1390 | * Set the initial memory mapping before triggering the reset of |
| 1391 | * the rest of the system, so that the guest image loader and CPU |
| 1392 | * reset see the correct mapping. |
| 1393 | */ |
| 1394 | remap_memory(mms, mms->remap); |
| 1395 | qemu_devices_reset(type); |
| 1396 | } |
| 1397 | |
| 1398 | static void mps2tz_class_init(ObjectClass *oc, const void *data) |
| 1399 | { |
| 1400 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1401 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); |
| 1402 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1403 | |
| 1404 | mc->init = mps2tz_common_init; |
| 1405 | mc->reset = mps2_machine_reset; |
| 1406 | iic->check = mps2_tz_idau_check; |
| 1407 | |
| 1408 | /* Most machines leave these at the SSE defaults */ |
| 1409 | mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; |
| 1410 | mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; |
| 1411 | mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; |
| 1412 | mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; |
| 1413 | } |
| 1414 | |
| 1415 | static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) |
| 1416 | { |
| 1417 | /* |
| 1418 | * Set mc->default_ram_size and default_ram_id from the |
| 1419 | * information in mmc->raminfo. |
| 1420 | */ |
| 1421 | MachineClass *mc = MACHINE_CLASS(mmc); |
| 1422 | const RAMInfo *p; |
| 1423 | |
| 1424 | for (p = mmc->raminfo; p->name; p++) { |
| 1425 | if (p->mrindex < 0) { |
| 1426 | /* Found the entry for "system memory" */ |
| 1427 | mc->default_ram_size = p->size; |
| 1428 | mc->default_ram_id = p->name; |
| 1429 | return; |
| 1430 | } |
| 1431 | } |
| 1432 | g_assert_not_reached(); |
| 1433 | } |
| 1434 | |
| 1435 | static void mps2tz_an505_class_init(ObjectClass *oc, const void *data) |
| 1436 | { |
| 1437 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1438 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1439 | static const char * const valid_cpu_types[] = { |
| 1440 | ARM_CPU_TYPE_NAME("cortex-m33"), |
| 1441 | NULL |
| 1442 | }; |
| 1443 | |
| 1444 | mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; |
| 1445 | mc->default_cpus = 1; |
| 1446 | mc->min_cpus = mc->default_cpus; |
| 1447 | mc->max_cpus = mc->default_cpus; |
| 1448 | mmc->fpga_type = FPGA_AN505; |
| 1449 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
| 1450 | mc->valid_cpu_types = valid_cpu_types; |
| 1451 | mmc->scc_id = 0x41045050; |
| 1452 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
| 1453 | mmc->apb_periph_frq = mmc->sysclk_frq; |
| 1454 | mmc->oscclk = an505_oscclk; |
| 1455 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
| 1456 | mmc->fpgaio_num_leds = 2; |
| 1457 | mmc->fpgaio_has_switches = false; |
| 1458 | mmc->fpgaio_has_dbgctrl = false; |
| 1459 | mmc->fpgaio_has_gpioalt2 = false; |
| 1460 | mmc->numirq = 92; |
| 1461 | mmc->uart_overflow_irq = 47; |
| 1462 | mmc->init_svtor = 0x10000000; |
| 1463 | mmc->sram_addr_width = 15; |
| 1464 | mmc->raminfo = an505_raminfo; |
| 1465 | mmc->armsse_type = TYPE_IOTKIT; |
| 1466 | mmc->boot_ram_size = 0; |
| 1467 | mps2tz_set_default_ram_info(mmc); |
| 1468 | } |
| 1469 | |
| 1470 | static void mps2tz_an521_class_init(ObjectClass *oc, const void *data) |
| 1471 | { |
| 1472 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1473 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1474 | static const char * const valid_cpu_types[] = { |
| 1475 | ARM_CPU_TYPE_NAME("cortex-m33"), |
| 1476 | NULL |
| 1477 | }; |
| 1478 | |
| 1479 | mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; |
| 1480 | mc->default_cpus = 2; |
| 1481 | mc->min_cpus = mc->default_cpus; |
| 1482 | mc->max_cpus = mc->default_cpus; |
| 1483 | mmc->fpga_type = FPGA_AN521; |
| 1484 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
| 1485 | mc->valid_cpu_types = valid_cpu_types; |
| 1486 | mmc->scc_id = 0x41045210; |
| 1487 | mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ |
| 1488 | mmc->apb_periph_frq = mmc->sysclk_frq; |
| 1489 | mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ |
| 1490 | mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); |
| 1491 | mmc->fpgaio_num_leds = 2; |
| 1492 | mmc->fpgaio_has_switches = false; |
| 1493 | mmc->fpgaio_has_dbgctrl = false; |
| 1494 | mmc->fpgaio_has_gpioalt2 = false; |
| 1495 | mmc->numirq = 92; |
| 1496 | mmc->uart_overflow_irq = 47; |
| 1497 | mmc->init_svtor = 0x10000000; |
| 1498 | mmc->sram_addr_width = 15; |
| 1499 | mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ |
| 1500 | mmc->armsse_type = TYPE_SSE200; |
| 1501 | mmc->boot_ram_size = 0; |
| 1502 | mps2tz_set_default_ram_info(mmc); |
| 1503 | } |
| 1504 | |
| 1505 | static void mps3tz_an524_class_init(ObjectClass *oc, const void *data) |
| 1506 | { |
| 1507 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1508 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1509 | static const char * const valid_cpu_types[] = { |
| 1510 | ARM_CPU_TYPE_NAME("cortex-m33"), |
| 1511 | NULL |
| 1512 | }; |
| 1513 | |
| 1514 | mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; |
| 1515 | mc->default_cpus = 2; |
| 1516 | mc->min_cpus = mc->default_cpus; |
| 1517 | mc->max_cpus = mc->default_cpus; |
| 1518 | mmc->fpga_type = FPGA_AN524; |
| 1519 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); |
| 1520 | mc->valid_cpu_types = valid_cpu_types; |
| 1521 | mmc->scc_id = 0x41045240; |
| 1522 | mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ |
| 1523 | mmc->apb_periph_frq = mmc->sysclk_frq; |
| 1524 | mmc->oscclk = an524_oscclk; |
| 1525 | mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); |
| 1526 | mmc->fpgaio_num_leds = 10; |
| 1527 | mmc->fpgaio_has_switches = true; |
| 1528 | mmc->fpgaio_has_dbgctrl = false; |
| 1529 | mmc->fpgaio_has_gpioalt2 = false; |
| 1530 | mmc->numirq = 95; |
| 1531 | mmc->uart_overflow_irq = 47; |
| 1532 | mmc->init_svtor = 0x10000000; |
| 1533 | mmc->sram_addr_width = 15; |
| 1534 | mmc->raminfo = an524_raminfo; |
| 1535 | mmc->armsse_type = TYPE_SSE200; |
| 1536 | mmc->boot_ram_size = 0; |
| 1537 | mps2tz_set_default_ram_info(mmc); |
| 1538 | |
| 1539 | object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); |
| 1540 | object_class_property_set_description(oc, "remap", |
| 1541 | "Set memory mapping. Valid values " |
| 1542 | "are BRAM (default) and QSPI."); |
| 1543 | } |
| 1544 | |
| 1545 | static void mps3tz_an547_class_init(ObjectClass *oc, const void *data) |
| 1546 | { |
| 1547 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1548 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1549 | static const char * const valid_cpu_types[] = { |
| 1550 | ARM_CPU_TYPE_NAME("cortex-m55"), |
| 1551 | NULL |
| 1552 | }; |
| 1553 | |
| 1554 | mc->desc = "ARM MPS3 with AN547 FPGA image for Cortex-M55"; |
| 1555 | mc->default_cpus = 1; |
| 1556 | mc->min_cpus = mc->default_cpus; |
| 1557 | mc->max_cpus = mc->default_cpus; |
| 1558 | mmc->fpga_type = FPGA_AN547; |
| 1559 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"); |
| 1560 | mc->valid_cpu_types = valid_cpu_types; |
| 1561 | mmc->scc_id = 0x41055470; |
| 1562 | mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ |
| 1563 | mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ |
| 1564 | mmc->oscclk = an524_oscclk; /* same as AN524 */ |
| 1565 | mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); |
| 1566 | mmc->fpgaio_num_leds = 10; |
| 1567 | mmc->fpgaio_has_switches = true; |
| 1568 | mmc->fpgaio_has_dbgctrl = true; |
| 1569 | mmc->fpgaio_has_gpioalt2 = false; |
| 1570 | mmc->numirq = 96; |
| 1571 | mmc->uart_overflow_irq = 48; |
| 1572 | mmc->init_svtor = 0x00000000; |
| 1573 | mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; |
| 1574 | mmc->sram_addr_width = 21; |
| 1575 | mmc->raminfo = an547_raminfo; |
| 1576 | mmc->armsse_type = TYPE_SSE300; |
| 1577 | mmc->boot_ram_size = 512 * KiB; |
| 1578 | mps2tz_set_default_ram_info(mmc); |
| 1579 | } |
| 1580 | |
| 1581 | static void mps3tz_an555_class_init(ObjectClass *oc, const void *data) |
| 1582 | { |
| 1583 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1584 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); |
| 1585 | static const char * const valid_cpu_types[] = { |
| 1586 | ARM_CPU_TYPE_NAME("cortex-m85"), |
| 1587 | NULL |
| 1588 | }; |
| 1589 | |
| 1590 | mc->desc = "ARM MPS3 with AN555 FPGA image for Cortex-M85"; |
| 1591 | mc->default_cpus = 1; |
| 1592 | mc->min_cpus = mc->default_cpus; |
| 1593 | mc->max_cpus = mc->default_cpus; |
| 1594 | mmc->fpga_type = FPGA_AN555; |
| 1595 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m85"); |
| 1596 | mc->valid_cpu_types = valid_cpu_types; |
| 1597 | mmc->scc_id = 0x41055551; |
| 1598 | mmc->sysclk_frq = 25 * 1000 * 1000; /* 25MHz */ |
| 1599 | mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */ |
| 1600 | mmc->oscclk = an555_oscclk; |
| 1601 | mmc->len_oscclk = ARRAY_SIZE(an555_oscclk); |
| 1602 | mmc->fpgaio_num_leds = 10; |
| 1603 | mmc->fpgaio_has_switches = true; |
| 1604 | mmc->fpgaio_has_dbgctrl = true; |
| 1605 | mmc->fpgaio_has_gpioalt2 = true; |
| 1606 | mmc->numirq = 96; |
| 1607 | mmc->uart_overflow_irq = 48; |
| 1608 | mmc->init_svtor = 0x00000000; |
| 1609 | mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 8; |
| 1610 | mmc->sram_addr_width = 21; |
| 1611 | mmc->raminfo = an547_raminfo; /* same as AN547*/ |
| 1612 | mmc->armsse_type = TYPE_SSE310; |
| 1613 | mmc->boot_ram_size = 512 * KiB; |
| 1614 | mps2tz_set_default_ram_info(mmc); |
| 1615 | } |
| 1616 | |
| 1617 | static const TypeInfo mps2tz_info = { |
| 1618 | .name = TYPE_MPS2TZ_MACHINE, |
| 1619 | .parent = TYPE_MACHINE, |
| 1620 | .abstract = true, |
| 1621 | .instance_size = sizeof(MPS2TZMachineState), |
| 1622 | .class_size = sizeof(MPS2TZMachineClass), |
| 1623 | .class_init = mps2tz_class_init, |
| 1624 | .interfaces = (const InterfaceInfo[]) { |
| 1625 | { TYPE_IDAU_INTERFACE }, |
| 1626 | { } |
| 1627 | }, |
| 1628 | }; |
| 1629 | |
| 1630 | static const TypeInfo mps2tz_an505_info = { |
| 1631 | .name = TYPE_MPS2TZ_AN505_MACHINE, |
| 1632 | .parent = TYPE_MPS2TZ_MACHINE, |
| 1633 | .class_init = mps2tz_an505_class_init, |
| 1634 | .interfaces = arm_machine_interfaces, |
| 1635 | }; |
| 1636 | |
| 1637 | static const TypeInfo mps2tz_an521_info = { |
| 1638 | .name = TYPE_MPS2TZ_AN521_MACHINE, |
| 1639 | .parent = TYPE_MPS2TZ_MACHINE, |
| 1640 | .class_init = mps2tz_an521_class_init, |
| 1641 | .interfaces = arm_machine_interfaces, |
| 1642 | }; |
| 1643 | |
| 1644 | static const TypeInfo mps3tz_an524_info = { |
| 1645 | .name = TYPE_MPS3TZ_AN524_MACHINE, |
| 1646 | .parent = TYPE_MPS2TZ_MACHINE, |
| 1647 | .class_init = mps3tz_an524_class_init, |
| 1648 | .interfaces = arm_machine_interfaces, |
| 1649 | }; |
| 1650 | |
| 1651 | static const TypeInfo mps3tz_an547_info = { |
| 1652 | .name = TYPE_MPS3TZ_AN547_MACHINE, |
| 1653 | .parent = TYPE_MPS2TZ_MACHINE, |
| 1654 | .class_init = mps3tz_an547_class_init, |
| 1655 | .interfaces = arm_machine_interfaces, |
| 1656 | }; |
| 1657 | |
| 1658 | static const TypeInfo mps3tz_an555_info = { |
| 1659 | .name = TYPE_MPS3TZ_AN555_MACHINE, |
| 1660 | .parent = TYPE_MPS2TZ_MACHINE, |
| 1661 | .class_init = mps3tz_an555_class_init, |
| 1662 | .interfaces = arm_machine_interfaces, |
| 1663 | }; |
| 1664 | |
| 1665 | static void mps2tz_machine_init(void) |
| 1666 | { |
| 1667 | type_register_static(&mps2tz_info); |
| 1668 | type_register_static(&mps2tz_an505_info); |
| 1669 | type_register_static(&mps2tz_an521_info); |
| 1670 | type_register_static(&mps3tz_an524_info); |
| 1671 | type_register_static(&mps3tz_an547_info); |
| 1672 | type_register_static(&mps3tz_an555_info); |
| 1673 | } |
| 1674 | |
| 1675 | type_init(mps2tz_machine_init); |