| 1 | /* |
| 2 | * ARM V2M MPS2 board emulation. |
| 3 | * |
| 4 | * Copyright (c) 2017 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger |
| 13 | * FPGA but is otherwise the same as the 2). Since the CPU itself |
| 14 | * and most of the devices are in the FPGA, the details of the board |
| 15 | * as seen by the guest depend significantly on the FPGA image. |
| 16 | * We model the following FPGA images: |
| 17 | * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 |
| 18 | * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 |
| 19 | * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500 |
| 20 | * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 |
| 21 | * |
| 22 | * Links to the TRM for the board itself and to the various Application |
| 23 | * Notes which document the FPGA images can be found here: |
| 24 | * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system |
| 25 | */ |
| 26 | |
| 27 | #include "qemu/osdep.h" |
| 28 | #include "qemu/units.h" |
| 29 | #include "qemu/cutils.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "hw/arm/boot.h" |
| 33 | #include "hw/arm/armv7m.h" |
| 34 | #include "hw/arm/machines-qom.h" |
| 35 | #include "hw/core/or-irq.h" |
| 36 | #include "hw/core/boards.h" |
| 37 | #include "system/address-spaces.h" |
| 38 | #include "system/system.h" |
| 39 | #include "hw/core/qdev-properties.h" |
| 40 | #include "hw/misc/unimp.h" |
| 41 | #include "hw/char/cmsdk-apb-uart.h" |
| 42 | #include "hw/timer/cmsdk-apb-timer.h" |
| 43 | #include "hw/timer/cmsdk-apb-dualtimer.h" |
| 44 | #include "hw/misc/mps2-scc.h" |
| 45 | #include "hw/misc/mps2-fpgaio.h" |
| 46 | #include "hw/ssi/pl022.h" |
| 47 | #include "hw/i2c/arm_sbcon_i2c.h" |
| 48 | #include "hw/net/lan9118.h" |
| 49 | #include "net/net.h" |
| 50 | #include "hw/watchdog/cmsdk-apb-watchdog.h" |
| 51 | #include "hw/core/qdev-clock.h" |
| 52 | #include "qobject/qlist.h" |
| 53 | #include "qom/object.h" |
| 54 | |
| 55 | typedef enum MPS2FPGAType { |
| 56 | FPGA_AN385, |
| 57 | FPGA_AN386, |
| 58 | FPGA_AN500, |
| 59 | FPGA_AN511, |
| 60 | } MPS2FPGAType; |
| 61 | |
| 62 | struct MPS2MachineClass { |
| 63 | MachineClass parent; |
| 64 | MPS2FPGAType fpga_type; |
| 65 | uint32_t scc_id; |
| 66 | bool has_block_ram; |
| 67 | hwaddr ethernet_base; |
| 68 | hwaddr psram_base; |
| 69 | }; |
| 70 | |
| 71 | struct MPS2MachineState { |
| 72 | MachineState parent; |
| 73 | |
| 74 | ARMv7MState armv7m; |
| 75 | MemoryRegion ssram1; |
| 76 | MemoryRegion ssram1_m; |
| 77 | MemoryRegion ssram23; |
| 78 | MemoryRegion ssram23_m; |
| 79 | MemoryRegion blockram; |
| 80 | MemoryRegion blockram_m1; |
| 81 | MemoryRegion blockram_m2; |
| 82 | MemoryRegion blockram_m3; |
| 83 | MemoryRegion sram; |
| 84 | /* FPGA APB subsystem */ |
| 85 | MPS2SCC scc; |
| 86 | MPS2FPGAIO fpgaio; |
| 87 | /* CMSDK APB subsystem */ |
| 88 | CMSDKAPBDualTimer dualtimer; |
| 89 | CMSDKAPBWatchdog watchdog; |
| 90 | CMSDKAPBTimer timer[2]; |
| 91 | Clock *sysclk; |
| 92 | Clock *refclk; |
| 93 | }; |
| 94 | |
| 95 | #define TYPE_MPS2_MACHINE "mps2" |
| 96 | #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") |
| 97 | #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") |
| 98 | #define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500") |
| 99 | #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") |
| 100 | |
| 101 | OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE) |
| 102 | |
| 103 | /* Main SYSCLK frequency in Hz */ |
| 104 | #define SYSCLK_FRQ 25000000 |
| 105 | |
| 106 | /* |
| 107 | * The Application Notes don't say anything about how the |
| 108 | * systick reference clock is configured. (Quite possibly |
| 109 | * they don't have one at all.) This 1MHz clock matches the |
| 110 | * pre-existing behaviour that used to be hardcoded in the |
| 111 | * armv7m_systick implementation. |
| 112 | */ |
| 113 | #define REFCLK_FRQ (1 * 1000 * 1000) |
| 114 | |
| 115 | /* Initialize the auxiliary RAM region @mr and map it into |
| 116 | * the memory map at @base. |
| 117 | */ |
| 118 | static void make_ram(MemoryRegion *mr, const char *name, |
| 119 | hwaddr base, hwaddr size) |
| 120 | { |
| 121 | memory_region_init_ram(mr, NULL, name, size, &error_fatal); |
| 122 | memory_region_add_subregion(get_system_memory(), base, mr); |
| 123 | } |
| 124 | |
| 125 | /* Create an alias of an entire original MemoryRegion @orig |
| 126 | * located at @base in the memory map. |
| 127 | */ |
| 128 | static void make_ram_alias(MemoryRegion *mr, const char *name, |
| 129 | MemoryRegion *orig, hwaddr base) |
| 130 | { |
| 131 | memory_region_init_alias(mr, NULL, name, orig, 0, |
| 132 | memory_region_size(orig)); |
| 133 | memory_region_add_subregion(get_system_memory(), base, mr); |
| 134 | } |
| 135 | |
| 136 | static void mps2_common_init(MachineState *machine) |
| 137 | { |
| 138 | MPS2MachineState *mms = MPS2_MACHINE(machine); |
| 139 | MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); |
| 140 | MemoryRegion *system_memory = get_system_memory(); |
| 141 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 142 | DeviceState *armv7m, *sccdev; |
| 143 | QList *oscclk; |
| 144 | int i; |
| 145 | |
| 146 | if (machine->ram_size != mc->default_ram_size) { |
| 147 | char *sz = size_to_str(mc->default_ram_size); |
| 148 | error_report("Invalid RAM size, should be %s", sz); |
| 149 | g_free(sz); |
| 150 | exit(EXIT_FAILURE); |
| 151 | } |
| 152 | |
| 153 | /* This clock doesn't need migration because it is fixed-frequency */ |
| 154 | mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); |
| 155 | clock_set_hz(mms->sysclk, SYSCLK_FRQ); |
| 156 | |
| 157 | mms->refclk = clock_new(OBJECT(machine), "REFCLK"); |
| 158 | clock_set_hz(mms->refclk, REFCLK_FRQ); |
| 159 | |
| 160 | /* The FPGA images have an odd combination of different RAMs, |
| 161 | * because in hardware they are different implementations and |
| 162 | * connected to different buses, giving varying performance/size |
| 163 | * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily |
| 164 | * call the 16MB our "system memory", as it's the largest lump. |
| 165 | * |
| 166 | * AN385/AN386/AN511: |
| 167 | * 0x21000000 .. 0x21ffffff : PSRAM (16MB) |
| 168 | * AN385/AN386/AN500: |
| 169 | * 0x00000000 .. 0x003fffff : ZBT SSRAM1 |
| 170 | * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 |
| 171 | * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 |
| 172 | * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 |
| 173 | * AN385/AN386 only: |
| 174 | * 0x01000000 .. 0x01003fff : block RAM (16K) |
| 175 | * 0x01004000 .. 0x01007fff : mirror of above |
| 176 | * 0x01008000 .. 0x0100bfff : mirror of above |
| 177 | * 0x0100c000 .. 0x0100ffff : mirror of above |
| 178 | * AN511 only: |
| 179 | * 0x00000000 .. 0x0003ffff : FPGA block RAM |
| 180 | * 0x00400000 .. 0x007fffff : ZBT SSRAM1 |
| 181 | * 0x20000000 .. 0x2001ffff : SRAM |
| 182 | * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 |
| 183 | * AN500 only: |
| 184 | * 0x60000000 .. 0x60ffffff : PSRAM (16MB) |
| 185 | * |
| 186 | * The AN385/AN386 has a feature where the lowest 16K can be mapped |
| 187 | * either to the bottom of the ZBT SSRAM1 or to the block RAM. |
| 188 | * This is of no use for QEMU so we don't implement it (as if |
| 189 | * zbt_boot_ctrl is always zero). |
| 190 | */ |
| 191 | memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram); |
| 192 | |
| 193 | if (mmc->has_block_ram) { |
| 194 | make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); |
| 195 | make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", |
| 196 | &mms->blockram, 0x01004000); |
| 197 | make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", |
| 198 | &mms->blockram, 0x01008000); |
| 199 | make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", |
| 200 | &mms->blockram, 0x0100c000); |
| 201 | } |
| 202 | |
| 203 | switch (mmc->fpga_type) { |
| 204 | case FPGA_AN385: |
| 205 | case FPGA_AN386: |
| 206 | case FPGA_AN500: |
| 207 | make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); |
| 208 | make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); |
| 209 | make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); |
| 210 | make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", |
| 211 | &mms->ssram23, 0x20400000); |
| 212 | break; |
| 213 | case FPGA_AN511: |
| 214 | make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); |
| 215 | make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); |
| 216 | make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); |
| 217 | make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); |
| 218 | break; |
| 219 | default: |
| 220 | g_assert_not_reached(); |
| 221 | } |
| 222 | |
| 223 | object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); |
| 224 | armv7m = DEVICE(&mms->armv7m); |
| 225 | switch (mmc->fpga_type) { |
| 226 | case FPGA_AN385: |
| 227 | case FPGA_AN386: |
| 228 | qdev_prop_set_uint32(armv7m, "num-irq", 32); |
| 229 | break; |
| 230 | case FPGA_AN500: |
| 231 | /* The AN500 configures its Cortex-M7 with 16 MPU regions */ |
| 232 | qdev_prop_set_uint32(armv7m, "mpu-ns-regions", 16); |
| 233 | qdev_prop_set_uint32(armv7m, "num-irq", 32); |
| 234 | break; |
| 235 | case FPGA_AN511: |
| 236 | qdev_prop_set_uint32(armv7m, "num-irq", 64); |
| 237 | break; |
| 238 | default: |
| 239 | g_assert_not_reached(); |
| 240 | } |
| 241 | qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); |
| 242 | qdev_connect_clock_in(armv7m, "refclk", mms->refclk); |
| 243 | qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); |
| 244 | qdev_prop_set_bit(armv7m, "enable-bitband", true); |
| 245 | object_property_set_link(OBJECT(&mms->armv7m), "memory", |
| 246 | OBJECT(system_memory), &error_abort); |
| 247 | sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); |
| 248 | |
| 249 | create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); |
| 250 | create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); |
| 251 | create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); |
| 252 | create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); |
| 253 | create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); |
| 254 | create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); |
| 255 | /* These three ranges all cover multiple devices; we may implement |
| 256 | * some of them below (in which case the real device takes precedence |
| 257 | * over the unimplemented-region mapping). |
| 258 | */ |
| 259 | create_unimplemented_device("CMSDK APB peripheral region @0x40000000", |
| 260 | 0x40000000, 0x00010000); |
| 261 | create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", |
| 262 | 0x40010000, 0x00010000); |
| 263 | create_unimplemented_device("Extra peripheral region @0x40020000", |
| 264 | 0x40020000, 0x00010000); |
| 265 | |
| 266 | create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); |
| 267 | create_unimplemented_device("VGA", 0x41000000, 0x0200000); |
| 268 | |
| 269 | switch (mmc->fpga_type) { |
| 270 | case FPGA_AN385: |
| 271 | case FPGA_AN386: |
| 272 | case FPGA_AN500: |
| 273 | { |
| 274 | /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. |
| 275 | * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. |
| 276 | */ |
| 277 | Object *orgate; |
| 278 | DeviceState *orgate_dev; |
| 279 | |
| 280 | orgate = object_new(TYPE_OR_IRQ); |
| 281 | object_property_set_int(orgate, "num-lines", 6, &error_fatal); |
| 282 | qdev_realize(DEVICE(orgate), NULL, &error_fatal); |
| 283 | orgate_dev = DEVICE(orgate); |
| 284 | qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); |
| 285 | |
| 286 | for (i = 0; i < 5; i++) { |
| 287 | DeviceState *dev; |
| 288 | SysBusDevice *s; |
| 289 | |
| 290 | static const hwaddr uartbase[] = {0x40004000, 0x40005000, |
| 291 | 0x40006000, 0x40007000, |
| 292 | 0x40009000}; |
| 293 | /* RX irq number; TX irq is always one greater */ |
| 294 | static const int uartirq[] = {0, 2, 4, 18, 20}; |
| 295 | qemu_irq txovrint = NULL, rxovrint = NULL; |
| 296 | |
| 297 | if (i < 3) { |
| 298 | txovrint = qdev_get_gpio_in(orgate_dev, i * 2); |
| 299 | rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); |
| 300 | } |
| 301 | |
| 302 | dev = qdev_new(TYPE_CMSDK_APB_UART); |
| 303 | s = SYS_BUS_DEVICE(dev); |
| 304 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 305 | qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); |
| 306 | sysbus_realize_and_unref(s, &error_fatal); |
| 307 | sysbus_mmio_map(s, 0, uartbase[i]); |
| 308 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1)); |
| 309 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i])); |
| 310 | sysbus_connect_irq(s, 2, txovrint); |
| 311 | sysbus_connect_irq(s, 3, rxovrint); |
| 312 | } |
| 313 | break; |
| 314 | } |
| 315 | case FPGA_AN511: |
| 316 | { |
| 317 | /* The overflow IRQs for all UARTs are ORed together. |
| 318 | * Tx and Rx IRQs for each UART are ORed together. |
| 319 | */ |
| 320 | Object *orgate; |
| 321 | DeviceState *orgate_dev; |
| 322 | |
| 323 | orgate = object_new(TYPE_OR_IRQ); |
| 324 | object_property_set_int(orgate, "num-lines", 10, &error_fatal); |
| 325 | qdev_realize(DEVICE(orgate), NULL, &error_fatal); |
| 326 | orgate_dev = DEVICE(orgate); |
| 327 | qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); |
| 328 | |
| 329 | for (i = 0; i < 5; i++) { |
| 330 | /* system irq numbers for the combined tx/rx for each UART */ |
| 331 | static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; |
| 332 | static const hwaddr uartbase[] = {0x40004000, 0x40005000, |
| 333 | 0x4002c000, 0x4002d000, |
| 334 | 0x4002e000}; |
| 335 | Object *txrx_orgate; |
| 336 | DeviceState *txrx_orgate_dev, *dev; |
| 337 | SysBusDevice *s; |
| 338 | |
| 339 | txrx_orgate = object_new(TYPE_OR_IRQ); |
| 340 | object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); |
| 341 | qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal); |
| 342 | txrx_orgate_dev = DEVICE(txrx_orgate); |
| 343 | qdev_connect_gpio_out(txrx_orgate_dev, 0, |
| 344 | qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); |
| 345 | |
| 346 | dev = qdev_new(TYPE_CMSDK_APB_UART); |
| 347 | s = SYS_BUS_DEVICE(dev); |
| 348 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 349 | qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); |
| 350 | sysbus_realize_and_unref(s, &error_fatal); |
| 351 | sysbus_mmio_map(s, 0, uartbase[i]); |
| 352 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0)); |
| 353 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1)); |
| 354 | sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); |
| 355 | sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); |
| 356 | } |
| 357 | break; |
| 358 | } |
| 359 | default: |
| 360 | g_assert_not_reached(); |
| 361 | } |
| 362 | for (i = 0; i < 4; i++) { |
| 363 | static const hwaddr gpiobase[] = {0x40010000, 0x40011000, |
| 364 | 0x40012000, 0x40013000}; |
| 365 | create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); |
| 366 | } |
| 367 | |
| 368 | /* CMSDK APB subsystem */ |
| 369 | for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { |
| 370 | g_autofree char *name = g_strdup_printf("timer%d", i); |
| 371 | hwaddr base = 0x40000000 + i * 0x1000; |
| 372 | int irqno = 8 + i; |
| 373 | SysBusDevice *sbd; |
| 374 | |
| 375 | object_initialize_child(OBJECT(mms), name, &mms->timer[i], |
| 376 | TYPE_CMSDK_APB_TIMER); |
| 377 | sbd = SYS_BUS_DEVICE(&mms->timer[i]); |
| 378 | qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); |
| 379 | sysbus_realize_and_unref(sbd, &error_fatal); |
| 380 | sysbus_mmio_map(sbd, 0, base); |
| 381 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); |
| 382 | } |
| 383 | |
| 384 | object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, |
| 385 | TYPE_CMSDK_APB_DUALTIMER); |
| 386 | qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); |
| 387 | sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); |
| 388 | sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, |
| 389 | qdev_get_gpio_in(armv7m, 10)); |
| 390 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); |
| 391 | object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, |
| 392 | TYPE_CMSDK_APB_WATCHDOG); |
| 393 | qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); |
| 394 | sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); |
| 395 | sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, |
| 396 | qdev_get_gpio_in_named(armv7m, "NMI", 0)); |
| 397 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); |
| 398 | |
| 399 | /* FPGA APB subsystem */ |
| 400 | object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); |
| 401 | sccdev = DEVICE(&mms->scc); |
| 402 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
| 403 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
| 404 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
| 405 | /* All these FPGA images have the same OSCCLK configuration */ |
| 406 | oscclk = qlist_new(); |
| 407 | qlist_append_int(oscclk, 50000000); |
| 408 | qlist_append_int(oscclk, 24576000); |
| 409 | qlist_append_int(oscclk, 25000000); |
| 410 | qdev_prop_set_array(sccdev, "oscclk", oscclk); |
| 411 | |
| 412 | sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); |
| 413 | sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); |
| 414 | object_initialize_child(OBJECT(mms), "fpgaio", |
| 415 | &mms->fpgaio, TYPE_MPS2_FPGAIO); |
| 416 | qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); |
| 417 | sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); |
| 418 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); |
| 419 | sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */ |
| 420 | qdev_get_gpio_in(armv7m, 22)); |
| 421 | for (i = 0; i < 2; i++) { |
| 422 | static const int spi_irqno[] = {11, 24}; |
| 423 | static const hwaddr spibase[] = {0x40020000, /* APB */ |
| 424 | 0x40021000, /* LCD */ |
| 425 | 0x40026000, /* Shield0 */ |
| 426 | 0x40027000}; /* Shield1 */ |
| 427 | DeviceState *orgate_dev; |
| 428 | Object *orgate; |
| 429 | int j; |
| 430 | |
| 431 | orgate = object_new(TYPE_OR_IRQ); |
| 432 | object_property_set_int(orgate, "num-lines", 2, &error_fatal); |
| 433 | orgate_dev = DEVICE(orgate); |
| 434 | qdev_realize(orgate_dev, NULL, &error_fatal); |
| 435 | qdev_connect_gpio_out(orgate_dev, 0, |
| 436 | qdev_get_gpio_in(armv7m, spi_irqno[i])); |
| 437 | for (j = 0; j < 2; j++) { |
| 438 | sysbus_create_simple(TYPE_PL022, spibase[2 * i + j], |
| 439 | qdev_get_gpio_in(orgate_dev, j)); |
| 440 | } |
| 441 | } |
| 442 | for (i = 0; i < 4; i++) { |
| 443 | static const hwaddr i2cbase[] = {0x40022000, /* Touch */ |
| 444 | 0x40023000, /* Audio */ |
| 445 | 0x40029000, /* Shield0 */ |
| 446 | 0x4002a000}; /* Shield1 */ |
| 447 | DeviceState *dev; |
| 448 | |
| 449 | dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); |
| 450 | if (i < 2) { |
| 451 | /* |
| 452 | * internal-only bus: mark it full to avoid user-created |
| 453 | * i2c devices being plugged into it. |
| 454 | */ |
| 455 | BusState *qbus = qdev_get_child_bus(dev, "i2c"); |
| 456 | qbus_mark_full(qbus); |
| 457 | } |
| 458 | } |
| 459 | create_unimplemented_device("i2s", 0x40024000, 0x400); |
| 460 | |
| 461 | /* In hardware this is a LAN9220; the LAN9118 is software compatible |
| 462 | * except that it doesn't support the checksum-offload feature. |
| 463 | */ |
| 464 | lan9118_init(mmc->ethernet_base, |
| 465 | qdev_get_gpio_in(armv7m, |
| 466 | mmc->fpga_type == FPGA_AN511 ? 47 : 13)); |
| 467 | |
| 468 | armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename, |
| 469 | 0, 0x400000); |
| 470 | } |
| 471 | |
| 472 | static void mps2_class_init(ObjectClass *oc, const void *data) |
| 473 | { |
| 474 | MachineClass *mc = MACHINE_CLASS(oc); |
| 475 | |
| 476 | mc->init = mps2_common_init; |
| 477 | mc->max_cpus = 1; |
| 478 | mc->default_ram_size = 16 * MiB; |
| 479 | mc->default_ram_id = "mps.ram"; |
| 480 | } |
| 481 | |
| 482 | static void mps2_an385_class_init(ObjectClass *oc, const void *data) |
| 483 | { |
| 484 | MachineClass *mc = MACHINE_CLASS(oc); |
| 485 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); |
| 486 | static const char * const valid_cpu_types[] = { |
| 487 | ARM_CPU_TYPE_NAME("cortex-m3"), |
| 488 | NULL |
| 489 | }; |
| 490 | |
| 491 | mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; |
| 492 | mmc->fpga_type = FPGA_AN385; |
| 493 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
| 494 | mc->valid_cpu_types = valid_cpu_types; |
| 495 | mmc->scc_id = 0x41043850; |
| 496 | mmc->psram_base = 0x21000000; |
| 497 | mmc->ethernet_base = 0x40200000; |
| 498 | mmc->has_block_ram = true; |
| 499 | } |
| 500 | |
| 501 | static void mps2_an386_class_init(ObjectClass *oc, const void *data) |
| 502 | { |
| 503 | MachineClass *mc = MACHINE_CLASS(oc); |
| 504 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); |
| 505 | static const char * const valid_cpu_types[] = { |
| 506 | ARM_CPU_TYPE_NAME("cortex-m4"), |
| 507 | NULL |
| 508 | }; |
| 509 | |
| 510 | mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4"; |
| 511 | mmc->fpga_type = FPGA_AN386; |
| 512 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); |
| 513 | mc->valid_cpu_types = valid_cpu_types; |
| 514 | mmc->scc_id = 0x41043860; |
| 515 | mmc->psram_base = 0x21000000; |
| 516 | mmc->ethernet_base = 0x40200000; |
| 517 | mmc->has_block_ram = true; |
| 518 | } |
| 519 | |
| 520 | static void mps2_an500_class_init(ObjectClass *oc, const void *data) |
| 521 | { |
| 522 | MachineClass *mc = MACHINE_CLASS(oc); |
| 523 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); |
| 524 | static const char * const valid_cpu_types[] = { |
| 525 | ARM_CPU_TYPE_NAME("cortex-m7"), |
| 526 | NULL |
| 527 | }; |
| 528 | |
| 529 | mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7"; |
| 530 | mmc->fpga_type = FPGA_AN500; |
| 531 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7"); |
| 532 | mc->valid_cpu_types = valid_cpu_types; |
| 533 | mmc->scc_id = 0x41045000; |
| 534 | mmc->psram_base = 0x60000000; |
| 535 | mmc->ethernet_base = 0xa0000000; |
| 536 | mmc->has_block_ram = false; |
| 537 | } |
| 538 | |
| 539 | static void mps2_an511_class_init(ObjectClass *oc, const void *data) |
| 540 | { |
| 541 | MachineClass *mc = MACHINE_CLASS(oc); |
| 542 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); |
| 543 | static const char * const valid_cpu_types[] = { |
| 544 | ARM_CPU_TYPE_NAME("cortex-m3"), |
| 545 | NULL |
| 546 | }; |
| 547 | |
| 548 | mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; |
| 549 | mmc->fpga_type = FPGA_AN511; |
| 550 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
| 551 | mc->valid_cpu_types = valid_cpu_types; |
| 552 | mmc->scc_id = 0x41045110; |
| 553 | mmc->psram_base = 0x21000000; |
| 554 | mmc->ethernet_base = 0x40200000; |
| 555 | mmc->has_block_ram = false; |
| 556 | } |
| 557 | |
| 558 | static const TypeInfo mps2_info = { |
| 559 | .name = TYPE_MPS2_MACHINE, |
| 560 | .parent = TYPE_MACHINE, |
| 561 | .abstract = true, |
| 562 | .instance_size = sizeof(MPS2MachineState), |
| 563 | .class_size = sizeof(MPS2MachineClass), |
| 564 | .class_init = mps2_class_init, |
| 565 | }; |
| 566 | |
| 567 | static const TypeInfo mps2_an385_info = { |
| 568 | .name = TYPE_MPS2_AN385_MACHINE, |
| 569 | .parent = TYPE_MPS2_MACHINE, |
| 570 | .class_init = mps2_an385_class_init, |
| 571 | .interfaces = arm_machine_interfaces, |
| 572 | }; |
| 573 | |
| 574 | static const TypeInfo mps2_an386_info = { |
| 575 | .name = TYPE_MPS2_AN386_MACHINE, |
| 576 | .parent = TYPE_MPS2_MACHINE, |
| 577 | .class_init = mps2_an386_class_init, |
| 578 | .interfaces = arm_machine_interfaces, |
| 579 | }; |
| 580 | |
| 581 | static const TypeInfo mps2_an500_info = { |
| 582 | .name = TYPE_MPS2_AN500_MACHINE, |
| 583 | .parent = TYPE_MPS2_MACHINE, |
| 584 | .class_init = mps2_an500_class_init, |
| 585 | .interfaces = arm_machine_interfaces, |
| 586 | }; |
| 587 | |
| 588 | static const TypeInfo mps2_an511_info = { |
| 589 | .name = TYPE_MPS2_AN511_MACHINE, |
| 590 | .parent = TYPE_MPS2_MACHINE, |
| 591 | .class_init = mps2_an511_class_init, |
| 592 | .interfaces = arm_machine_interfaces, |
| 593 | }; |
| 594 | |
| 595 | static void mps2_machine_init(void) |
| 596 | { |
| 597 | type_register_static(&mps2_info); |
| 598 | type_register_static(&mps2_an385_info); |
| 599 | type_register_static(&mps2_an386_info); |
| 600 | type_register_static(&mps2_an500_info); |
| 601 | type_register_static(&mps2_an511_info); |
| 602 | } |
| 603 | |
| 604 | type_init(mps2_machine_init); |