| 1 | /* |
| 2 | * SmartFusion2 SOM starter kit(from Emcraft) emulation. |
| 3 | * |
| 4 | * M2S-FG484 SOM hardware architecture specification: |
| 5 | * https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf |
| 6 | * |
| 7 | * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> |
| 8 | * |
| 9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 10 | * of this software and associated documentation files (the "Software"), to deal |
| 11 | * in the Software without restriction, including without limitation the rights |
| 12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 13 | * copies of the Software, and to permit persons to whom the Software is |
| 14 | * furnished to do so, subject to the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice shall be included in |
| 17 | * all copies or substantial portions of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 25 | * THE SOFTWARE. |
| 26 | */ |
| 27 | |
| 28 | #include "qemu/osdep.h" |
| 29 | #include "qemu/units.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "hw/core/boards.h" |
| 33 | #include "hw/core/qdev-properties.h" |
| 34 | #include "hw/arm/boot.h" |
| 35 | #include "hw/arm/machines-qom.h" |
| 36 | #include "hw/core/qdev-clock.h" |
| 37 | #include "system/address-spaces.h" |
| 38 | #include "hw/arm/msf2-soc.h" |
| 39 | |
| 40 | #define DDR_BASE_ADDRESS 0xA0000000 |
| 41 | #define DDR_SIZE (64 * MiB) |
| 42 | |
| 43 | #define M2S010_ENVM_SIZE (256 * KiB) |
| 44 | #define M2S010_ESRAM_SIZE (64 * KiB) |
| 45 | |
| 46 | static void emcraft_sf2_s2s010_init(MachineState *machine) |
| 47 | { |
| 48 | DeviceState *dev; |
| 49 | DeviceState *spi_flash; |
| 50 | MSF2State *soc; |
| 51 | DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); |
| 52 | qemu_irq cs_line; |
| 53 | BusState *spi_bus; |
| 54 | MemoryRegion *sysmem = get_system_memory(); |
| 55 | MemoryRegion *ddr = g_new(MemoryRegion, 1); |
| 56 | Clock *m3clk; |
| 57 | |
| 58 | memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, |
| 59 | &error_fatal); |
| 60 | memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); |
| 61 | |
| 62 | dev = qdev_new(TYPE_MSF2_SOC); |
| 63 | object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); |
| 64 | qdev_prop_set_string(dev, "part-name", "M2S010"); |
| 65 | qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); |
| 66 | qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); |
| 67 | |
| 68 | /* |
| 69 | * CPU clock and peripheral clocks(APB0, APB1)are configurable |
| 70 | * in Libero. CPU clock is divided by APB0 and APB1 divisors for |
| 71 | * peripherals. Emcraft's SoM kit comes with these settings by default. |
| 72 | */ |
| 73 | /* This clock doesn't need migration because it is fixed-frequency */ |
| 74 | m3clk = clock_new(OBJECT(machine), "m3clk"); |
| 75 | clock_set_hz(m3clk, 142 * 1000000); |
| 76 | qdev_connect_clock_in(dev, "m3clk", m3clk); |
| 77 | qdev_prop_set_uint32(dev, "apb0div", 2); |
| 78 | qdev_prop_set_uint32(dev, "apb1div", 2); |
| 79 | |
| 80 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 81 | |
| 82 | soc = MSF2_SOC(dev); |
| 83 | |
| 84 | /* Attach SPI flash to SPI0 controller */ |
| 85 | spi_bus = qdev_get_child_bus(dev, "spi0"); |
| 86 | spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */ |
| 87 | qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 0x8); |
| 88 | if (dinfo) { |
| 89 | qdev_prop_set_drive_err(spi_flash, "drive", |
| 90 | blk_by_legacy_dinfo(dinfo), &error_fatal); |
| 91 | } |
| 92 | qdev_realize_and_unref(spi_flash, spi_bus, &error_fatal); |
| 93 | cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); |
| 94 | sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); |
| 95 | |
| 96 | armv7m_load_kernel(soc->armv7m.cpu, machine->kernel_filename, |
| 97 | 0, soc->envm_size); |
| 98 | } |
| 99 | |
| 100 | static void emcraft_sf2_machine_init(MachineClass *mc) |
| 101 | { |
| 102 | static const char * const valid_cpu_types[] = { |
| 103 | ARM_CPU_TYPE_NAME("cortex-m3"), |
| 104 | NULL |
| 105 | }; |
| 106 | |
| 107 | mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; |
| 108 | mc->init = emcraft_sf2_s2s010_init; |
| 109 | mc->valid_cpu_types = valid_cpu_types; |
| 110 | } |
| 111 | |
| 112 | DEFINE_MACHINE_ARM("emcraft-sf2", emcraft_sf2_machine_init) |