| 1 | /* |
| 2 | * Arm Musca-B1 test chip board emulation |
| 3 | * |
| 4 | * Copyright (c) 2019 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * The Musca boards are a reference implementation of a system using |
| 14 | * the SSE-200 subsystem for embedded: |
| 15 | * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board |
| 16 | * https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board |
| 17 | * We model the A and B1 variants of this board, as described in the TRMs: |
| 18 | * https://developer.arm.com/documentation/101107/latest/ |
| 19 | * https://developer.arm.com/documentation/101312/latest/ |
| 20 | */ |
| 21 | |
| 22 | #include "qemu/osdep.h" |
| 23 | #include "qemu/error-report.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "system/address-spaces.h" |
| 26 | #include "system/system.h" |
| 27 | #include "hw/arm/boot.h" |
| 28 | #include "hw/arm/armsse.h" |
| 29 | #include "hw/arm/machines-qom.h" |
| 30 | #include "hw/core/boards.h" |
| 31 | #include "hw/char/pl011.h" |
| 32 | #include "hw/core/split-irq.h" |
| 33 | #include "hw/misc/tz-mpc.h" |
| 34 | #include "hw/misc/tz-ppc.h" |
| 35 | #include "hw/misc/unimp.h" |
| 36 | #include "hw/rtc/pl031.h" |
| 37 | #include "hw/core/qdev-clock.h" |
| 38 | #include "qom/object.h" |
| 39 | |
| 40 | #define MUSCA_NUMIRQ_MAX 96 |
| 41 | #define MUSCA_PPC_MAX 3 |
| 42 | #define MUSCA_MPC_MAX 5 |
| 43 | |
| 44 | typedef struct MPCInfo MPCInfo; |
| 45 | |
| 46 | typedef enum MuscaType { |
| 47 | MUSCA_A, |
| 48 | MUSCA_B1, |
| 49 | } MuscaType; |
| 50 | |
| 51 | struct MuscaMachineClass { |
| 52 | MachineClass parent; |
| 53 | MuscaType type; |
| 54 | uint32_t init_svtor; |
| 55 | int sram_addr_width; |
| 56 | int num_irqs; |
| 57 | const MPCInfo *mpc_info; |
| 58 | int num_mpcs; |
| 59 | }; |
| 60 | |
| 61 | struct MuscaMachineState { |
| 62 | MachineState parent; |
| 63 | |
| 64 | ARMSSE sse; |
| 65 | /* RAM and flash */ |
| 66 | MemoryRegion ram[MUSCA_MPC_MAX]; |
| 67 | SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX]; |
| 68 | SplitIRQ sec_resp_splitter; |
| 69 | TZPPC ppc[MUSCA_PPC_MAX]; |
| 70 | MemoryRegion container; |
| 71 | UnimplementedDeviceState eflash[2]; |
| 72 | UnimplementedDeviceState qspi; |
| 73 | TZMPC mpc[MUSCA_MPC_MAX]; |
| 74 | UnimplementedDeviceState mhu[2]; |
| 75 | UnimplementedDeviceState pwm[3]; |
| 76 | UnimplementedDeviceState i2s; |
| 77 | PL011State uart[2]; |
| 78 | UnimplementedDeviceState i2c[2]; |
| 79 | UnimplementedDeviceState spi; |
| 80 | UnimplementedDeviceState scc; |
| 81 | UnimplementedDeviceState timer; |
| 82 | PL031State rtc; |
| 83 | UnimplementedDeviceState pvt; |
| 84 | UnimplementedDeviceState sdio; |
| 85 | UnimplementedDeviceState gpio; |
| 86 | UnimplementedDeviceState cryptoisland; |
| 87 | Clock *sysclk; |
| 88 | Clock *s32kclk; |
| 89 | }; |
| 90 | |
| 91 | #define TYPE_MUSCA_MACHINE "musca" |
| 92 | #define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a") |
| 93 | #define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1") |
| 94 | |
| 95 | OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) |
| 96 | |
| 97 | /* |
| 98 | * Main SYSCLK frequency in Hz |
| 99 | * TODO this should really be different for the two cores, but we |
| 100 | * don't model that in our SSE-200 model yet. |
| 101 | */ |
| 102 | #define SYSCLK_FRQ 40000000 |
| 103 | /* Slow 32Khz S32KCLK frequency in Hz */ |
| 104 | #define S32KCLK_FRQ (32 * 1000) |
| 105 | |
| 106 | static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) |
| 107 | { |
| 108 | /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ |
| 109 | assert(irqno < MUSCA_NUMIRQ_MAX); |
| 110 | |
| 111 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * Most of the devices in the Musca board sit behind Peripheral Protection |
| 116 | * Controllers. These data structures define the layout of which devices |
| 117 | * sit behind which PPCs. |
| 118 | * The devfn for each port is a function which creates, configures |
| 119 | * and initializes the device, returning the MemoryRegion which |
| 120 | * needs to be plugged into the downstream end of the PPC port. |
| 121 | */ |
| 122 | typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque, |
| 123 | const char *name, hwaddr size); |
| 124 | |
| 125 | typedef struct PPCPortInfo { |
| 126 | const char *name; |
| 127 | MakeDevFn *devfn; |
| 128 | void *opaque; |
| 129 | hwaddr addr; |
| 130 | hwaddr size; |
| 131 | } PPCPortInfo; |
| 132 | |
| 133 | typedef struct PPCInfo { |
| 134 | const char *name; |
| 135 | PPCPortInfo ports[TZ_NUM_PORTS]; |
| 136 | } PPCInfo; |
| 137 | |
| 138 | static MemoryRegion *make_unimp_dev(MuscaMachineState *mms, |
| 139 | void *opaque, const char *name, hwaddr size) |
| 140 | { |
| 141 | /* |
| 142 | * Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, |
| 143 | * and return a pointer to its MemoryRegion. |
| 144 | */ |
| 145 | UnimplementedDeviceState *uds = opaque; |
| 146 | |
| 147 | object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); |
| 148 | qdev_prop_set_string(DEVICE(uds), "name", name); |
| 149 | qdev_prop_set_uint64(DEVICE(uds), "size", size); |
| 150 | sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); |
| 151 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); |
| 152 | } |
| 153 | |
| 154 | typedef enum MPCInfoType { |
| 155 | MPC_RAM, |
| 156 | MPC_ROM, |
| 157 | MPC_CRYPTOISLAND, |
| 158 | } MPCInfoType; |
| 159 | |
| 160 | struct MPCInfo { |
| 161 | const char *name; |
| 162 | hwaddr addr; |
| 163 | hwaddr size; |
| 164 | MPCInfoType type; |
| 165 | }; |
| 166 | |
| 167 | /* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */ |
| 168 | static const MPCInfo a_mpc_info[] = { { |
| 169 | .name = "qspi", |
| 170 | .type = MPC_ROM, |
| 171 | .addr = 0x00200000, |
| 172 | .size = 0x00800000, |
| 173 | }, { |
| 174 | .name = "sram", |
| 175 | .type = MPC_RAM, |
| 176 | .addr = 0x00000000, |
| 177 | .size = 0x00200000, |
| 178 | } |
| 179 | }; |
| 180 | |
| 181 | static const MPCInfo b1_mpc_info[] = { { |
| 182 | .name = "qspi", |
| 183 | .type = MPC_ROM, |
| 184 | .addr = 0x00000000, |
| 185 | .size = 0x02000000, |
| 186 | }, { |
| 187 | .name = "sram", |
| 188 | .type = MPC_RAM, |
| 189 | .addr = 0x0a400000, |
| 190 | .size = 0x00080000, |
| 191 | }, { |
| 192 | .name = "eflash0", |
| 193 | .type = MPC_ROM, |
| 194 | .addr = 0x0a000000, |
| 195 | .size = 0x00200000, |
| 196 | }, { |
| 197 | .name = "eflash1", |
| 198 | .type = MPC_ROM, |
| 199 | .addr = 0x0a200000, |
| 200 | .size = 0x00200000, |
| 201 | }, { |
| 202 | .name = "cryptoisland", |
| 203 | .type = MPC_CRYPTOISLAND, |
| 204 | .addr = 0x0a000000, |
| 205 | .size = 0x00200000, |
| 206 | } |
| 207 | }; |
| 208 | |
| 209 | static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque, |
| 210 | const char *name, hwaddr size) |
| 211 | { |
| 212 | /* |
| 213 | * Create an MPC and the RAM or flash behind it. |
| 214 | * MPC 0: eFlash 0 |
| 215 | * MPC 1: eFlash 1 |
| 216 | * MPC 2: SRAM |
| 217 | * MPC 3: QSPI flash |
| 218 | * MPC 4: CryptoIsland |
| 219 | * For now we implement the flash regions as ROM (ie not programmable) |
| 220 | * (with their control interface memory regions being unimplemented |
| 221 | * stubs behind the PPCs). |
| 222 | * The whole CryptoIsland region behind its MPC is an unimplemented stub. |
| 223 | */ |
| 224 | MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); |
| 225 | TZMPC *mpc = opaque; |
| 226 | int i = mpc - &mms->mpc[0]; |
| 227 | MemoryRegion *downstream; |
| 228 | MemoryRegion *upstream; |
| 229 | UnimplementedDeviceState *uds; |
| 230 | char *mpcname; |
| 231 | const MPCInfo *mpcinfo = mmc->mpc_info; |
| 232 | |
| 233 | mpcname = g_strdup_printf("%s-mpc", mpcinfo[i].name); |
| 234 | |
| 235 | switch (mpcinfo[i].type) { |
| 236 | case MPC_ROM: |
| 237 | downstream = &mms->ram[i]; |
| 238 | memory_region_init_rom(downstream, NULL, mpcinfo[i].name, |
| 239 | mpcinfo[i].size, &error_fatal); |
| 240 | break; |
| 241 | case MPC_RAM: |
| 242 | downstream = &mms->ram[i]; |
| 243 | memory_region_init_ram(downstream, NULL, mpcinfo[i].name, |
| 244 | mpcinfo[i].size, &error_fatal); |
| 245 | break; |
| 246 | case MPC_CRYPTOISLAND: |
| 247 | /* We don't implement the CryptoIsland yet */ |
| 248 | uds = &mms->cryptoisland; |
| 249 | object_initialize_child(OBJECT(mms), name, uds, |
| 250 | TYPE_UNIMPLEMENTED_DEVICE); |
| 251 | qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name); |
| 252 | qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size); |
| 253 | sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); |
| 254 | downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); |
| 255 | break; |
| 256 | default: |
| 257 | g_assert_not_reached(); |
| 258 | } |
| 259 | |
| 260 | object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); |
| 261 | object_property_set_link(OBJECT(mpc), "downstream", OBJECT(downstream), |
| 262 | &error_fatal); |
| 263 | sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); |
| 264 | /* Map the upstream end of the MPC into system memory */ |
| 265 | upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); |
| 266 | memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream); |
| 267 | /* and connect its interrupt to the SSE-200 */ |
| 268 | qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, |
| 269 | qdev_get_gpio_in_named(DEVICE(&mms->sse), |
| 270 | "mpcexp_status", i)); |
| 271 | |
| 272 | g_free(mpcname); |
| 273 | /* Return the register interface MR for our caller to map behind the PPC */ |
| 274 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); |
| 275 | } |
| 276 | |
| 277 | static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque, |
| 278 | const char *name, hwaddr size) |
| 279 | { |
| 280 | PL031State *rtc = opaque; |
| 281 | |
| 282 | object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031); |
| 283 | sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal); |
| 284 | sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39)); |
| 285 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); |
| 286 | } |
| 287 | |
| 288 | static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque, |
| 289 | const char *name, hwaddr size) |
| 290 | { |
| 291 | PL011State *uart = opaque; |
| 292 | int i = uart - &mms->uart[0]; |
| 293 | int irqbase = 7 + i * 6; |
| 294 | SysBusDevice *s; |
| 295 | |
| 296 | object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011); |
| 297 | qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); |
| 298 | sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); |
| 299 | s = SYS_BUS_DEVICE(uart); |
| 300 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */ |
| 301 | sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */ |
| 302 | sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */ |
| 303 | sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */ |
| 304 | sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */ |
| 305 | sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */ |
| 306 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); |
| 307 | } |
| 308 | |
| 309 | static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque, |
| 310 | const char *name, hwaddr size) |
| 311 | { |
| 312 | /* |
| 313 | * Create the container MemoryRegion for all the devices that live |
| 314 | * behind the Musca-A PPC's single port. These devices don't have a PPC |
| 315 | * port each, but we use the PPCPortInfo struct as a convenient way |
| 316 | * to describe them. Note that addresses here are relative to the base |
| 317 | * address of the PPC port region: 0x40100000, and devices appear both |
| 318 | * at the 0x4... NS region and the 0x5... S region. |
| 319 | */ |
| 320 | int i; |
| 321 | MemoryRegion *container = &mms->container; |
| 322 | |
| 323 | const PPCPortInfo devices[] = { |
| 324 | { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 }, |
| 325 | { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 }, |
| 326 | { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 }, |
| 327 | { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 }, |
| 328 | { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, |
| 329 | { "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 }, |
| 330 | { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 }, |
| 331 | { "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 }, |
| 332 | { "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 }, |
| 333 | { "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 }, |
| 334 | { "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 }, |
| 335 | { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 }, |
| 336 | { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 }, |
| 337 | { "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 }, |
| 338 | { "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 }, |
| 339 | { "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 }, |
| 340 | }; |
| 341 | |
| 342 | memory_region_init(container, OBJECT(mms), "musca-device-container", size); |
| 343 | |
| 344 | for (i = 0; i < ARRAY_SIZE(devices); i++) { |
| 345 | const PPCPortInfo *pinfo = &devices[i]; |
| 346 | MemoryRegion *mr; |
| 347 | |
| 348 | mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); |
| 349 | memory_region_add_subregion(container, pinfo->addr, mr); |
| 350 | } |
| 351 | |
| 352 | return &mms->container; |
| 353 | } |
| 354 | |
| 355 | static void musca_init(MachineState *machine) |
| 356 | { |
| 357 | MuscaMachineState *mms = MUSCA_MACHINE(machine); |
| 358 | MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms); |
| 359 | MemoryRegion *system_memory = get_system_memory(); |
| 360 | DeviceState *ssedev; |
| 361 | DeviceState *dev_splitter; |
| 362 | const PPCInfo *ppcs; |
| 363 | int num_ppcs; |
| 364 | int i; |
| 365 | |
| 366 | assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX); |
| 367 | assert(mmc->num_mpcs <= MUSCA_MPC_MAX); |
| 368 | |
| 369 | mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); |
| 370 | clock_set_hz(mms->sysclk, SYSCLK_FRQ); |
| 371 | mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); |
| 372 | clock_set_hz(mms->s32kclk, S32KCLK_FRQ); |
| 373 | |
| 374 | object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, |
| 375 | TYPE_SSE200); |
| 376 | ssedev = DEVICE(&mms->sse); |
| 377 | object_property_set_link(OBJECT(&mms->sse), "memory", |
| 378 | OBJECT(system_memory), &error_fatal); |
| 379 | qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); |
| 380 | qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); |
| 381 | qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); |
| 382 | qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); |
| 383 | qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); |
| 384 | /* |
| 385 | * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for |
| 386 | * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. |
| 387 | */ |
| 388 | if (mmc->type == MUSCA_B1) { |
| 389 | qdev_prop_set_bit(ssedev, "CPU0_FPU", true); |
| 390 | qdev_prop_set_bit(ssedev, "CPU0_DSP", true); |
| 391 | } |
| 392 | sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal); |
| 393 | |
| 394 | /* |
| 395 | * We need to create splitters to feed the IRQ inputs |
| 396 | * for each CPU in the SSE-200 from each device in the board. |
| 397 | */ |
| 398 | for (i = 0; i < mmc->num_irqs; i++) { |
| 399 | char *name = g_strdup_printf("musca-irq-splitter%d", i); |
| 400 | SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; |
| 401 | |
| 402 | object_initialize_child_with_props(OBJECT(machine), name, splitter, |
| 403 | sizeof(*splitter), TYPE_SPLIT_IRQ, |
| 404 | &error_fatal, NULL); |
| 405 | g_free(name); |
| 406 | |
| 407 | object_property_set_int(OBJECT(splitter), "num-lines", 2, |
| 408 | &error_fatal); |
| 409 | qdev_realize(DEVICE(splitter), NULL, &error_fatal); |
| 410 | qdev_connect_gpio_out(DEVICE(splitter), 0, |
| 411 | qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i)); |
| 412 | qdev_connect_gpio_out(DEVICE(splitter), 1, |
| 413 | qdev_get_gpio_in_named(ssedev, |
| 414 | "EXP_CPU1_IRQ", i)); |
| 415 | } |
| 416 | |
| 417 | /* |
| 418 | * The sec_resp_cfg output from the SSE-200 must be split into multiple |
| 419 | * lines, one for each of the PPCs we create here. |
| 420 | */ |
| 421 | object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter", |
| 422 | &mms->sec_resp_splitter, |
| 423 | sizeof(mms->sec_resp_splitter), |
| 424 | TYPE_SPLIT_IRQ, &error_fatal, NULL); |
| 425 | |
| 426 | object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", |
| 427 | ARRAY_SIZE(mms->ppc), &error_fatal); |
| 428 | qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); |
| 429 | dev_splitter = DEVICE(&mms->sec_resp_splitter); |
| 430 | qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0, |
| 431 | qdev_get_gpio_in(dev_splitter, 0)); |
| 432 | |
| 433 | /* |
| 434 | * Most of the devices in the board are behind Peripheral Protection |
| 435 | * Controllers. The required order for initializing things is: |
| 436 | * + initialize the PPC |
| 437 | * + initialize, configure and realize downstream devices |
| 438 | * + connect downstream device MemoryRegions to the PPC |
| 439 | * + realize the PPC |
| 440 | * + map the PPC's MemoryRegions to the places in the address map |
| 441 | * where the downstream devices should appear |
| 442 | * + wire up the PPC's control lines to the SSE object |
| 443 | * |
| 444 | * The PPC mapping differs for the -A and -B1 variants; the -A version |
| 445 | * is much simpler, using only a single port of a single PPC and putting |
| 446 | * all the devices behind that. |
| 447 | */ |
| 448 | const PPCInfo a_ppcs[] = { { |
| 449 | .name = "ahb_ppcexp0", |
| 450 | .ports = { |
| 451 | { "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 }, |
| 452 | }, |
| 453 | }, |
| 454 | }; |
| 455 | |
| 456 | /* |
| 457 | * Devices listed with an 0x4.. address appear in both the NS 0x4.. region |
| 458 | * and the 0x5.. S region. Devices listed with an 0x5.. address appear |
| 459 | * only in the S region. |
| 460 | */ |
| 461 | const PPCInfo b1_ppcs[] = { { |
| 462 | .name = "apb_ppcexp0", |
| 463 | .ports = { |
| 464 | { "eflash0", make_unimp_dev, &mms->eflash[0], |
| 465 | 0x52400000, 0x1000 }, |
| 466 | { "eflash1", make_unimp_dev, &mms->eflash[1], |
| 467 | 0x52500000, 0x1000 }, |
| 468 | { "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 }, |
| 469 | { "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 }, |
| 470 | { "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 }, |
| 471 | { "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 }, |
| 472 | { "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 }, |
| 473 | { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 }, |
| 474 | { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 }, |
| 475 | { }, /* port 9: unused */ |
| 476 | { }, /* port 10: unused */ |
| 477 | { }, /* port 11: unused */ |
| 478 | { }, /* port 12: unused */ |
| 479 | { }, /* port 13: unused */ |
| 480 | { "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 }, |
| 481 | }, |
| 482 | }, { |
| 483 | .name = "apb_ppcexp1", |
| 484 | .ports = { |
| 485 | { "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 }, |
| 486 | { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 }, |
| 487 | { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 }, |
| 488 | { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 }, |
| 489 | { "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 }, |
| 490 | { "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 }, |
| 491 | { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 }, |
| 492 | { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 }, |
| 493 | { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 }, |
| 494 | { "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 }, |
| 495 | { "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 }, |
| 496 | { "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 }, |
| 497 | { "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 }, |
| 498 | { "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 }, |
| 499 | }, |
| 500 | }, { |
| 501 | .name = "ahb_ppcexp0", |
| 502 | .ports = { |
| 503 | { }, /* port 0: unused */ |
| 504 | { "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 }, |
| 505 | }, |
| 506 | }, |
| 507 | }; |
| 508 | |
| 509 | switch (mmc->type) { |
| 510 | case MUSCA_A: |
| 511 | ppcs = a_ppcs; |
| 512 | num_ppcs = ARRAY_SIZE(a_ppcs); |
| 513 | break; |
| 514 | case MUSCA_B1: |
| 515 | ppcs = b1_ppcs; |
| 516 | num_ppcs = ARRAY_SIZE(b1_ppcs); |
| 517 | break; |
| 518 | default: |
| 519 | g_assert_not_reached(); |
| 520 | } |
| 521 | assert(num_ppcs <= MUSCA_PPC_MAX); |
| 522 | |
| 523 | for (i = 0; i < num_ppcs; i++) { |
| 524 | const PPCInfo *ppcinfo = &ppcs[i]; |
| 525 | TZPPC *ppc = &mms->ppc[i]; |
| 526 | DeviceState *ppcdev; |
| 527 | int port; |
| 528 | char *gpioname; |
| 529 | |
| 530 | object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, |
| 531 | TYPE_TZ_PPC); |
| 532 | ppcdev = DEVICE(ppc); |
| 533 | |
| 534 | for (port = 0; port < TZ_NUM_PORTS; port++) { |
| 535 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; |
| 536 | MemoryRegion *mr; |
| 537 | char *portname; |
| 538 | |
| 539 | if (!pinfo->devfn) { |
| 540 | continue; |
| 541 | } |
| 542 | |
| 543 | mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); |
| 544 | portname = g_strdup_printf("port[%d]", port); |
| 545 | object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), |
| 546 | &error_fatal); |
| 547 | g_free(portname); |
| 548 | } |
| 549 | |
| 550 | sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); |
| 551 | |
| 552 | for (port = 0; port < TZ_NUM_PORTS; port++) { |
| 553 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; |
| 554 | |
| 555 | if (!pinfo->devfn) { |
| 556 | continue; |
| 557 | } |
| 558 | sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); |
| 559 | |
| 560 | gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); |
| 561 | qdev_connect_gpio_out_named(ssedev, gpioname, port, |
| 562 | qdev_get_gpio_in_named(ppcdev, |
| 563 | "cfg_nonsec", |
| 564 | port)); |
| 565 | g_free(gpioname); |
| 566 | gpioname = g_strdup_printf("%s_ap", ppcinfo->name); |
| 567 | qdev_connect_gpio_out_named(ssedev, gpioname, port, |
| 568 | qdev_get_gpio_in_named(ppcdev, |
| 569 | "cfg_ap", port)); |
| 570 | g_free(gpioname); |
| 571 | } |
| 572 | |
| 573 | gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); |
| 574 | qdev_connect_gpio_out_named(ssedev, gpioname, 0, |
| 575 | qdev_get_gpio_in_named(ppcdev, |
| 576 | "irq_enable", 0)); |
| 577 | g_free(gpioname); |
| 578 | gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); |
| 579 | qdev_connect_gpio_out_named(ssedev, gpioname, 0, |
| 580 | qdev_get_gpio_in_named(ppcdev, |
| 581 | "irq_clear", 0)); |
| 582 | g_free(gpioname); |
| 583 | gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); |
| 584 | qdev_connect_gpio_out_named(ppcdev, "irq", 0, |
| 585 | qdev_get_gpio_in_named(ssedev, |
| 586 | gpioname, 0)); |
| 587 | g_free(gpioname); |
| 588 | |
| 589 | qdev_connect_gpio_out(dev_splitter, i, |
| 590 | qdev_get_gpio_in_named(ppcdev, |
| 591 | "cfg_sec_resp", 0)); |
| 592 | } |
| 593 | |
| 594 | armv7m_load_kernel(mms->sse.armv7m[0].cpu, machine->kernel_filename, |
| 595 | 0, 0x2000000); |
| 596 | } |
| 597 | |
| 598 | static void musca_class_init(ObjectClass *oc, const void *data) |
| 599 | { |
| 600 | MachineClass *mc = MACHINE_CLASS(oc); |
| 601 | static const char * const valid_cpu_types[] = { |
| 602 | ARM_CPU_TYPE_NAME("cortex-m33"), |
| 603 | NULL |
| 604 | }; |
| 605 | |
| 606 | mc->default_cpus = 2; |
| 607 | mc->min_cpus = mc->default_cpus; |
| 608 | mc->max_cpus = mc->default_cpus; |
| 609 | mc->valid_cpu_types = valid_cpu_types; |
| 610 | mc->init = musca_init; |
| 611 | } |
| 612 | |
| 613 | static void musca_a_class_init(ObjectClass *oc, const void *data) |
| 614 | { |
| 615 | MachineClass *mc = MACHINE_CLASS(oc); |
| 616 | MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc); |
| 617 | |
| 618 | mc->desc = "ARM Musca-A board (dual Cortex-M33)"; |
| 619 | mmc->type = MUSCA_A; |
| 620 | mmc->init_svtor = 0x10200000; |
| 621 | mmc->sram_addr_width = 15; |
| 622 | mmc->num_irqs = 64; |
| 623 | mmc->mpc_info = a_mpc_info; |
| 624 | mmc->num_mpcs = ARRAY_SIZE(a_mpc_info); |
| 625 | } |
| 626 | |
| 627 | static void musca_b1_class_init(ObjectClass *oc, const void *data) |
| 628 | { |
| 629 | MachineClass *mc = MACHINE_CLASS(oc); |
| 630 | MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc); |
| 631 | |
| 632 | mc->desc = "ARM Musca-B1 board (dual Cortex-M33)"; |
| 633 | mmc->type = MUSCA_B1; |
| 634 | /* |
| 635 | * This matches the DAPlink firmware which boots from QSPI. There |
| 636 | * is also a firmware blob which boots from the eFlash, which |
| 637 | * uses init_svtor = 0x1A000000. QEMU doesn't currently support that, |
| 638 | * though we could in theory expose a machine property on the command |
| 639 | * line to allow the user to request eFlash boot. |
| 640 | */ |
| 641 | mmc->init_svtor = 0x10000000; |
| 642 | mmc->sram_addr_width = 17; |
| 643 | mmc->num_irqs = 96; |
| 644 | mmc->mpc_info = b1_mpc_info; |
| 645 | mmc->num_mpcs = ARRAY_SIZE(b1_mpc_info); |
| 646 | } |
| 647 | |
| 648 | static const TypeInfo musca_info = { |
| 649 | .name = TYPE_MUSCA_MACHINE, |
| 650 | .parent = TYPE_MACHINE, |
| 651 | .abstract = true, |
| 652 | .instance_size = sizeof(MuscaMachineState), |
| 653 | .class_size = sizeof(MuscaMachineClass), |
| 654 | .class_init = musca_class_init, |
| 655 | }; |
| 656 | |
| 657 | static const TypeInfo musca_a_info = { |
| 658 | .name = TYPE_MUSCA_A_MACHINE, |
| 659 | .parent = TYPE_MUSCA_MACHINE, |
| 660 | .class_init = musca_a_class_init, |
| 661 | .interfaces = arm_machine_interfaces, |
| 662 | }; |
| 663 | |
| 664 | static const TypeInfo musca_b1_info = { |
| 665 | .name = TYPE_MUSCA_B1_MACHINE, |
| 666 | .parent = TYPE_MUSCA_MACHINE, |
| 667 | .class_init = musca_b1_class_init, |
| 668 | .interfaces = arm_machine_interfaces, |
| 669 | }; |
| 670 | |
| 671 | static void musca_machine_init(void) |
| 672 | { |
| 673 | type_register_static(&musca_info); |
| 674 | type_register_static(&musca_a_info); |
| 675 | type_register_static(&musca_b1_info); |
| 676 | } |
| 677 | |
| 678 | type_init(musca_machine_init); |