| 1 | /* |
| 2 | * Nuvoton NPCM8xx SoC family. |
| 3 | * |
| 4 | * Copyright 2022 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | |
| 19 | #include "hw/core/boards.h" |
| 20 | #include "hw/arm/boot.h" |
| 21 | #include "hw/arm/bsa.h" |
| 22 | #include "hw/arm/npcm8xx.h" |
| 23 | #include "hw/char/serial-mm.h" |
| 24 | #include "hw/intc/arm_gic.h" |
| 25 | #include "hw/core/loader.h" |
| 26 | #include "hw/misc/unimp.h" |
| 27 | #include "hw/core/qdev-clock.h" |
| 28 | #include "hw/core/qdev-properties.h" |
| 29 | #include "qapi/error.h" |
| 30 | #include "qemu/units.h" |
| 31 | #include "system/system.h" |
| 32 | |
| 33 | /* |
| 34 | * This covers the whole MMIO space. We'll use this to catch any MMIO accesses |
| 35 | * that aren't handled by a device. |
| 36 | */ |
| 37 | #define NPCM8XX_MMIO_BA 0x80000000 |
| 38 | #define NPCM8XX_MMIO_SZ 0x7ffd0000 |
| 39 | |
| 40 | /* OTP fuse array */ |
| 41 | #define NPCM8XX_OTP_BA 0xf0189000 |
| 42 | |
| 43 | /* GIC Distributor */ |
| 44 | #define NPCM8XX_GICD_BA 0xdfff9000 |
| 45 | #define NPCM8XX_GICC_BA 0xdfffa000 |
| 46 | |
| 47 | /* Core system modules. */ |
| 48 | #define NPCM8XX_CPUP_BA 0xf03fe000 |
| 49 | #define NPCM8XX_GCR_BA 0xf0800000 |
| 50 | #define NPCM8XX_CLK_BA 0xf0801000 |
| 51 | #define NPCM8XX_MC_BA 0xf0824000 |
| 52 | #define NPCM8XX_RNG_BA 0xf000b000 |
| 53 | |
| 54 | /* ADC Module */ |
| 55 | #define NPCM8XX_ADC_BA 0xf000c000 |
| 56 | |
| 57 | /* Internal AHB SRAM */ |
| 58 | #define NPCM8XX_RAM3_BA 0xc0008000 |
| 59 | #define NPCM8XX_RAM3_SZ (4 * KiB) |
| 60 | |
| 61 | /* Memory blocks at the end of the address space */ |
| 62 | #define NPCM8XX_RAM2_BA 0xfffb0000 |
| 63 | #define NPCM8XX_RAM2_SZ (256 * KiB) |
| 64 | #define NPCM8XX_ROM_BA 0xffff0100 |
| 65 | #define NPCM8XX_ROM_SZ (64 * KiB) |
| 66 | |
| 67 | /* SDHCI Modules */ |
| 68 | #define NPCM8XX_MMC_BA 0xf0842000 |
| 69 | |
| 70 | /* PCS Module */ |
| 71 | #define NPCM8XX_PCS_BA 0xf0780000 |
| 72 | |
| 73 | /* PSPI Modules */ |
| 74 | #define NPCM8XX_PSPI_BA 0xf0201000 |
| 75 | |
| 76 | /* Run PLL1 at 1600 MHz */ |
| 77 | #define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101 |
| 78 | /* Run the CPU from PLL1 and UART from PLL2 */ |
| 79 | #define NPCM8XX_CLKSEL_FIXUP_VAL 0x004aaba9 |
| 80 | |
| 81 | /* Clock configuration values to be fixed up when bypassing bootloader */ |
| 82 | |
| 83 | /* |
| 84 | * Interrupt lines going into the GIC. This does not include internal Cortex-A35 |
| 85 | * interrupts. |
| 86 | */ |
| 87 | enum NPCM8xxInterrupt { |
| 88 | NPCM8XX_ADC_IRQ = 0, |
| 89 | NPCM8XX_PECI_IRQ = 6, |
| 90 | NPCM8XX_KCS_HIB_IRQ = 9, |
| 91 | NPCM8XX_GMAC1_IRQ = 14, |
| 92 | NPCM8XX_GMAC2_IRQ, |
| 93 | NPCM8XX_GMAC3_IRQ, |
| 94 | NPCM8XX_GMAC4_IRQ, |
| 95 | NPCM8XX_MMC_IRQ = 26, |
| 96 | NPCM8XX_PSPI_IRQ = 28, |
| 97 | NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */ |
| 98 | NPCM8XX_TIMER1_IRQ, |
| 99 | NPCM8XX_TIMER2_IRQ, |
| 100 | NPCM8XX_TIMER3_IRQ, |
| 101 | NPCM8XX_TIMER4_IRQ, |
| 102 | NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */ |
| 103 | NPCM8XX_TIMER6_IRQ, |
| 104 | NPCM8XX_TIMER7_IRQ, |
| 105 | NPCM8XX_TIMER8_IRQ, |
| 106 | NPCM8XX_TIMER9_IRQ, |
| 107 | NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */ |
| 108 | NPCM8XX_TIMER11_IRQ, |
| 109 | NPCM8XX_TIMER12_IRQ, |
| 110 | NPCM8XX_TIMER13_IRQ, |
| 111 | NPCM8XX_TIMER14_IRQ, |
| 112 | NPCM8XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ |
| 113 | NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ |
| 114 | NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ |
| 115 | NPCM8XX_EHCI1_IRQ = 61, |
| 116 | NPCM8XX_OHCI1_IRQ, |
| 117 | NPCM8XX_EHCI2_IRQ, |
| 118 | NPCM8XX_OHCI2_IRQ, |
| 119 | NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */ |
| 120 | NPCM8XX_PWM1_IRQ, /* PWM module 1 */ |
| 121 | NPCM8XX_MFT0_IRQ = 96, /* MFT module 0 */ |
| 122 | NPCM8XX_MFT1_IRQ, /* MFT module 1 */ |
| 123 | NPCM8XX_MFT2_IRQ, /* MFT module 2 */ |
| 124 | NPCM8XX_MFT3_IRQ, /* MFT module 3 */ |
| 125 | NPCM8XX_MFT4_IRQ, /* MFT module 4 */ |
| 126 | NPCM8XX_MFT5_IRQ, /* MFT module 5 */ |
| 127 | NPCM8XX_MFT6_IRQ, /* MFT module 6 */ |
| 128 | NPCM8XX_MFT7_IRQ, /* MFT module 7 */ |
| 129 | NPCM8XX_PCI_MBOX1_IRQ = 105, |
| 130 | NPCM8XX_PCI_MBOX2_IRQ, |
| 131 | NPCM8XX_GPIO0_IRQ = 116, |
| 132 | NPCM8XX_GPIO1_IRQ, |
| 133 | NPCM8XX_GPIO2_IRQ, |
| 134 | NPCM8XX_GPIO3_IRQ, |
| 135 | NPCM8XX_GPIO4_IRQ, |
| 136 | NPCM8XX_GPIO5_IRQ, |
| 137 | NPCM8XX_GPIO6_IRQ, |
| 138 | NPCM8XX_GPIO7_IRQ, |
| 139 | NPCM8XX_SMBUS0_IRQ = 128, |
| 140 | NPCM8XX_SMBUS1_IRQ, |
| 141 | NPCM8XX_SMBUS2_IRQ, |
| 142 | NPCM8XX_SMBUS3_IRQ, |
| 143 | NPCM8XX_SMBUS4_IRQ, |
| 144 | NPCM8XX_SMBUS5_IRQ, |
| 145 | NPCM8XX_SMBUS6_IRQ, |
| 146 | NPCM8XX_SMBUS7_IRQ, |
| 147 | NPCM8XX_SMBUS8_IRQ, |
| 148 | NPCM8XX_SMBUS9_IRQ, |
| 149 | NPCM8XX_SMBUS10_IRQ, |
| 150 | NPCM8XX_SMBUS11_IRQ, |
| 151 | NPCM8XX_SMBUS12_IRQ, |
| 152 | NPCM8XX_SMBUS13_IRQ, |
| 153 | NPCM8XX_SMBUS14_IRQ, |
| 154 | NPCM8XX_SMBUS15_IRQ, |
| 155 | NPCM8XX_SMBUS16_IRQ, |
| 156 | NPCM8XX_SMBUS17_IRQ, |
| 157 | NPCM8XX_SMBUS18_IRQ, |
| 158 | NPCM8XX_SMBUS19_IRQ, |
| 159 | NPCM8XX_SMBUS20_IRQ, |
| 160 | NPCM8XX_SMBUS21_IRQ, |
| 161 | NPCM8XX_SMBUS22_IRQ, |
| 162 | NPCM8XX_SMBUS23_IRQ, |
| 163 | NPCM8XX_SMBUS24_IRQ, |
| 164 | NPCM8XX_SMBUS25_IRQ, |
| 165 | NPCM8XX_SMBUS26_IRQ, |
| 166 | NPCM8XX_UART0_IRQ = 192, |
| 167 | NPCM8XX_UART1_IRQ, |
| 168 | NPCM8XX_UART2_IRQ, |
| 169 | NPCM8XX_UART3_IRQ, |
| 170 | NPCM8XX_UART4_IRQ, |
| 171 | NPCM8XX_UART5_IRQ, |
| 172 | NPCM8XX_UART6_IRQ, |
| 173 | }; |
| 174 | |
| 175 | /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */ |
| 176 | #define NPCM8XX_NUM_IRQ (288) |
| 177 | #define NPCM8XX_PPI_BASE(cpu) \ |
| 178 | ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL) |
| 179 | |
| 180 | /* Register base address for each Timer Module */ |
| 181 | static const hwaddr npcm8xx_tim_addr[] = { |
| 182 | 0xf0008000, |
| 183 | 0xf0009000, |
| 184 | 0xf000a000, |
| 185 | }; |
| 186 | |
| 187 | /* Register base address for each 16550 UART */ |
| 188 | static const hwaddr npcm8xx_uart_addr[] = { |
| 189 | 0xf0000000, |
| 190 | 0xf0001000, |
| 191 | 0xf0002000, |
| 192 | 0xf0003000, |
| 193 | 0xf0004000, |
| 194 | 0xf0005000, |
| 195 | 0xf0006000, |
| 196 | }; |
| 197 | |
| 198 | /* Direct memory-mapped access to SPI0 CS0-1. */ |
| 199 | static const hwaddr npcm8xx_fiu0_flash_addr[] = { |
| 200 | 0x80000000, /* CS0 */ |
| 201 | 0x88000000, /* CS1 */ |
| 202 | }; |
| 203 | |
| 204 | /* Direct memory-mapped access to SPI1 CS0-3. */ |
| 205 | static const hwaddr npcm8xx_fiu1_flash_addr[] = { |
| 206 | 0x90000000, /* CS0 */ |
| 207 | 0x91000000, /* CS1 */ |
| 208 | 0x92000000, /* CS2 */ |
| 209 | 0x93000000, /* CS3 */ |
| 210 | }; |
| 211 | |
| 212 | /* Direct memory-mapped access to SPI3 CS0-3. */ |
| 213 | static const hwaddr npcm8xx_fiu3_flash_addr[] = { |
| 214 | 0xa0000000, /* CS0 */ |
| 215 | 0xa8000000, /* CS1 */ |
| 216 | 0xb0000000, /* CS2 */ |
| 217 | 0xb8000000, /* CS3 */ |
| 218 | }; |
| 219 | |
| 220 | /* Register base address for each PWM Module */ |
| 221 | static const hwaddr npcm8xx_pwm_addr[] = { |
| 222 | 0xf0103000, |
| 223 | 0xf0104000, |
| 224 | 0xf0105000, |
| 225 | }; |
| 226 | |
| 227 | /* Register base address for each MFT Module */ |
| 228 | static const hwaddr npcm8xx_mft_addr[] = { |
| 229 | 0xf0180000, |
| 230 | 0xf0181000, |
| 231 | 0xf0182000, |
| 232 | 0xf0183000, |
| 233 | 0xf0184000, |
| 234 | 0xf0185000, |
| 235 | 0xf0186000, |
| 236 | 0xf0187000, |
| 237 | }; |
| 238 | |
| 239 | /* Direct memory-mapped access to each SMBus Module. */ |
| 240 | static const hwaddr npcm8xx_smbus_addr[] = { |
| 241 | 0xf0080000, |
| 242 | 0xf0081000, |
| 243 | 0xf0082000, |
| 244 | 0xf0083000, |
| 245 | 0xf0084000, |
| 246 | 0xf0085000, |
| 247 | 0xf0086000, |
| 248 | 0xf0087000, |
| 249 | 0xf0088000, |
| 250 | 0xf0089000, |
| 251 | 0xf008a000, |
| 252 | 0xf008b000, |
| 253 | 0xf008c000, |
| 254 | 0xf008d000, |
| 255 | 0xf008e000, |
| 256 | 0xf008f000, |
| 257 | 0xfff00000, |
| 258 | 0xfff01000, |
| 259 | 0xfff02000, |
| 260 | 0xfff03000, |
| 261 | 0xfff04000, |
| 262 | 0xfff05000, |
| 263 | 0xfff06000, |
| 264 | 0xfff07000, |
| 265 | 0xfff08000, |
| 266 | 0xfff09000, |
| 267 | 0xfff0a000, |
| 268 | }; |
| 269 | |
| 270 | /* Register base address for each GMAC Module */ |
| 271 | static const hwaddr npcm8xx_gmac_addr[] = { |
| 272 | 0xf0802000, |
| 273 | 0xf0804000, |
| 274 | 0xf0806000, |
| 275 | 0xf0808000, |
| 276 | }; |
| 277 | |
| 278 | /* Register base address for each USB host EHCI registers */ |
| 279 | static const hwaddr npcm8xx_ehci_addr[] = { |
| 280 | 0xf0828100, |
| 281 | 0xf082a100, |
| 282 | }; |
| 283 | |
| 284 | /* Register base address for each USB host OHCI registers */ |
| 285 | static const hwaddr npcm8xx_ohci_addr[] = { |
| 286 | 0xf0829000, |
| 287 | 0xf082b000, |
| 288 | }; |
| 289 | |
| 290 | static const struct { |
| 291 | hwaddr regs_addr; |
| 292 | uint32_t reset_pu; |
| 293 | uint32_t reset_pd; |
| 294 | uint32_t reset_osrc; |
| 295 | uint32_t reset_odsc; |
| 296 | } npcm8xx_gpio[] = { |
| 297 | { |
| 298 | .regs_addr = 0xf0010000, |
| 299 | .reset_pu = 0x00000300, |
| 300 | .reset_pd = 0x000f0000, |
| 301 | }, { |
| 302 | .regs_addr = 0xf0011000, |
| 303 | .reset_pu = 0xe0fefe01, |
| 304 | .reset_pd = 0x07000000, |
| 305 | }, { |
| 306 | .regs_addr = 0xf0012000, |
| 307 | .reset_pu = 0xc00fffff, |
| 308 | .reset_pd = 0x3ff00000, |
| 309 | }, { |
| 310 | .regs_addr = 0xf0013000, |
| 311 | .reset_pd = 0x00003000, |
| 312 | }, { |
| 313 | .regs_addr = 0xf0014000, |
| 314 | .reset_pu = 0xffff0000, |
| 315 | }, { |
| 316 | .regs_addr = 0xf0015000, |
| 317 | .reset_pu = 0xff8387fe, |
| 318 | .reset_pd = 0x007c0001, |
| 319 | .reset_osrc = 0x08000000, |
| 320 | }, { |
| 321 | .regs_addr = 0xf0016000, |
| 322 | .reset_pu = 0x00000801, |
| 323 | .reset_pd = 0x00000302, |
| 324 | }, { |
| 325 | .regs_addr = 0xf0017000, |
| 326 | .reset_pu = 0x000002ff, |
| 327 | .reset_pd = 0x00000c00, |
| 328 | }, |
| 329 | }; |
| 330 | |
| 331 | static const struct { |
| 332 | const char *name; |
| 333 | hwaddr regs_addr; |
| 334 | int cs_count; |
| 335 | const hwaddr *flash_addr; |
| 336 | size_t flash_size; |
| 337 | } npcm8xx_fiu[] = { |
| 338 | { |
| 339 | .name = "fiu0", |
| 340 | .regs_addr = 0xfb000000, |
| 341 | .cs_count = ARRAY_SIZE(npcm8xx_fiu0_flash_addr), |
| 342 | .flash_addr = npcm8xx_fiu0_flash_addr, |
| 343 | .flash_size = 128 * MiB, |
| 344 | }, |
| 345 | { |
| 346 | .name = "fiu1", |
| 347 | .regs_addr = 0xfb002000, |
| 348 | .cs_count = ARRAY_SIZE(npcm8xx_fiu1_flash_addr), |
| 349 | .flash_addr = npcm8xx_fiu1_flash_addr, |
| 350 | .flash_size = 16 * MiB, |
| 351 | }, { |
| 352 | .name = "fiu3", |
| 353 | .regs_addr = 0xc0000000, |
| 354 | .cs_count = ARRAY_SIZE(npcm8xx_fiu3_flash_addr), |
| 355 | .flash_addr = npcm8xx_fiu3_flash_addr, |
| 356 | .flash_size = 128 * MiB, |
| 357 | }, |
| 358 | }; |
| 359 | |
| 360 | void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc, |
| 361 | struct arm_boot_info *binfo) |
| 362 | { |
| 363 | binfo->loader_start = NPCM8XX_LOADER_START; |
| 364 | binfo->smp_loader_start = NPCM8XX_SMP_LOADER_START; |
| 365 | binfo->smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR; |
| 366 | binfo->gic_cpu_if_addr = NPCM8XX_GICC_BA; |
| 367 | binfo->secure_boot = false; |
| 368 | binfo->board_id = -1; |
| 369 | binfo->board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR; |
| 370 | binfo->psci_conduit = QEMU_PSCI_CONDUIT_SMC; |
| 371 | binfo->ram_size = machine->ram_size; |
| 372 | |
| 373 | arm_load_kernel(&soc->cpu[0], machine, binfo); |
| 374 | } |
| 375 | |
| 376 | static void npcm8xx_init_fuses(NPCM8xxState *s) |
| 377 | { |
| 378 | NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); |
| 379 | uint32_t value; |
| 380 | |
| 381 | /* |
| 382 | * The initial mask of disabled modules indicates the chip derivative (e.g. |
| 383 | * NPCM750 or NPCM730). |
| 384 | */ |
| 385 | value = cpu_to_le32(nc->disabled_modules); |
| 386 | npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, |
| 387 | sizeof(value)); |
| 388 | } |
| 389 | |
| 390 | static void npcm8xx_write_adc_calibration(NPCM8xxState *s) |
| 391 | { |
| 392 | /* Both ADC and the fuse array must have realized. */ |
| 393 | QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4); |
| 394 | npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, |
| 395 | NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); |
| 396 | } |
| 397 | |
| 398 | static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n) |
| 399 | { |
| 400 | return qdev_get_gpio_in(DEVICE(&s->gic), n); |
| 401 | } |
| 402 | |
| 403 | static void npcm8xx_init(Object *obj) |
| 404 | { |
| 405 | NPCM8xxState *s = NPCM8XX(obj); |
| 406 | int i; |
| 407 | |
| 408 | object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, |
| 409 | TYPE_CPU_CLUSTER); |
| 410 | for (i = 0; i < NPCM8XX_MAX_NUM_CPUS; i++) { |
| 411 | object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu[i], |
| 412 | ARM_CPU_TYPE_NAME("cortex-a35")); |
| 413 | } |
| 414 | object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); |
| 415 | object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); |
| 416 | object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), |
| 417 | "power-on-straps"); |
| 418 | object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); |
| 419 | object_initialize_child(obj, "otp", &s->fuse_array, |
| 420 | TYPE_NPCM7XX_FUSE_ARRAY); |
| 421 | object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); |
| 422 | object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); |
| 423 | object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); |
| 424 | |
| 425 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { |
| 426 | object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); |
| 427 | } |
| 428 | |
| 429 | for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { |
| 430 | object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); |
| 431 | } |
| 432 | |
| 433 | |
| 434 | for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { |
| 435 | object_initialize_child(obj, "smbus[*]", &s->smbus[i], |
| 436 | TYPE_NPCM7XX_SMBUS); |
| 437 | DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i); |
| 438 | } |
| 439 | |
| 440 | for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { |
| 441 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_EHCI); |
| 442 | } |
| 443 | for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { |
| 444 | object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI); |
| 445 | } |
| 446 | |
| 447 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); |
| 448 | for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { |
| 449 | object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], |
| 450 | TYPE_NPCM7XX_FIU); |
| 451 | } |
| 452 | |
| 453 | for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { |
| 454 | object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); |
| 455 | } |
| 456 | |
| 457 | for (i = 0; i < ARRAY_SIZE(s->mft); i++) { |
| 458 | object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT); |
| 459 | } |
| 460 | |
| 461 | for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { |
| 462 | object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC); |
| 463 | } |
| 464 | object_initialize_child(obj, "pcs", &s->pcs, TYPE_NPCM_PCS); |
| 465 | |
| 466 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); |
| 467 | object_initialize_child(obj, "pspi", &s->pspi, TYPE_NPCM_PSPI); |
| 468 | } |
| 469 | |
| 470 | static void npcm8xx_realize(DeviceState *dev, Error **errp) |
| 471 | { |
| 472 | NPCM8xxState *s = NPCM8XX(dev); |
| 473 | NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s); |
| 474 | int i; |
| 475 | |
| 476 | if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { |
| 477 | error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64 |
| 478 | " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB); |
| 479 | return; |
| 480 | } |
| 481 | |
| 482 | /* CPUs */ |
| 483 | for (i = 0; i < nc->num_cpus; i++) { |
| 484 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
| 485 | arm_build_mp_affinity(i, NPCM8XX_MAX_NUM_CPUS), |
| 486 | &error_abort); |
| 487 | object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, |
| 488 | &error_abort); |
| 489 | object_property_set_int(OBJECT(&s->cpu[i]), "core-count", |
| 490 | nc->num_cpus, &error_abort); |
| 491 | |
| 492 | /* Disable security extensions. */ |
| 493 | object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, |
| 494 | &error_abort); |
| 495 | |
| 496 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
| 497 | return; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters here. */ |
| 502 | object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp); |
| 503 | object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp); |
| 504 | object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); |
| 505 | object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true, |
| 506 | errp); |
| 507 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
| 508 | return; |
| 509 | } |
| 510 | for (i = 0; i < nc->num_cpus; i++) { |
| 511 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, |
| 512 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); |
| 513 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, |
| 514 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); |
| 515 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, |
| 516 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VIRQ)); |
| 517 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, |
| 518 | qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VFIQ)); |
| 519 | |
| 520 | qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, |
| 521 | qdev_get_gpio_in(DEVICE(&s->gic), |
| 522 | NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL1_IRQ)); |
| 523 | qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, |
| 524 | qdev_get_gpio_in(DEVICE(&s->gic), |
| 525 | NPCM8XX_PPI_BASE(i) + ARCH_TIMER_VIRT_IRQ)); |
| 526 | qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, |
| 527 | qdev_get_gpio_in(DEVICE(&s->gic), |
| 528 | NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL2_IRQ)); |
| 529 | qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, |
| 530 | qdev_get_gpio_in(DEVICE(&s->gic), |
| 531 | NPCM8XX_PPI_BASE(i) + ARCH_TIMER_S_EL1_IRQ)); |
| 532 | } |
| 533 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); |
| 534 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); |
| 535 | |
| 536 | /* CPU cluster */ |
| 537 | qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); |
| 538 | qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); |
| 539 | |
| 540 | /* System Global Control Registers (GCR). Can fail due to user input. */ |
| 541 | object_property_set_int(OBJECT(&s->gcr), "disabled-modules", |
| 542 | nc->disabled_modules, &error_abort); |
| 543 | object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram)); |
| 544 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { |
| 545 | return; |
| 546 | } |
| 547 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); |
| 548 | |
| 549 | /* Clock Control Registers (CLK). Cannot fail. */ |
| 550 | sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); |
| 551 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); |
| 552 | |
| 553 | /* OTP fuse strap array. Cannot fail. */ |
| 554 | sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); |
| 555 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); |
| 556 | npcm8xx_init_fuses(s); |
| 557 | |
| 558 | /* Fake Memory Controller (MC). Cannot fail. */ |
| 559 | sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); |
| 560 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); |
| 561 | |
| 562 | /* ADC Modules. Cannot fail. */ |
| 563 | qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( |
| 564 | DEVICE(&s->clk), "adc-clock")); |
| 565 | sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); |
| 566 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); |
| 567 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
| 568 | npcm8xx_irq(s, NPCM8XX_ADC_IRQ)); |
| 569 | npcm8xx_write_adc_calibration(s); |
| 570 | |
| 571 | /* Timer Modules (TIM). Cannot fail. */ |
| 572 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) != ARRAY_SIZE(s->tim)); |
| 573 | for (i = 0; i < ARRAY_SIZE(s->tim); i++) { |
| 574 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); |
| 575 | int first_irq; |
| 576 | int j; |
| 577 | |
| 578 | /* Connect the timer clock. */ |
| 579 | qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out( |
| 580 | DEVICE(&s->clk), "timer-clock")); |
| 581 | |
| 582 | sysbus_realize(sbd, &error_abort); |
| 583 | sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]); |
| 584 | |
| 585 | first_irq = NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; |
| 586 | for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { |
| 587 | qemu_irq irq = npcm8xx_irq(s, first_irq + j); |
| 588 | sysbus_connect_irq(sbd, j, irq); |
| 589 | } |
| 590 | |
| 591 | /* IRQ for watchdogs */ |
| 592 | sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, |
| 593 | npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i)); |
| 594 | /* GPIO that connects clk module with watchdog */ |
| 595 | qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), |
| 596 | NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, |
| 597 | qdev_get_gpio_in_named(DEVICE(&s->clk), |
| 598 | NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); |
| 599 | } |
| 600 | |
| 601 | /* UART0..6 (16550 compatible) */ |
| 602 | for (i = 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) { |
| 603 | serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2, |
| 604 | npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200, |
| 605 | serial_hd(i), DEVICE_LITTLE_ENDIAN); |
| 606 | } |
| 607 | |
| 608 | /* Random Number Generator. Cannot fail. */ |
| 609 | sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); |
| 610 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); |
| 611 | |
| 612 | /* GPIO modules. Cannot fail. */ |
| 613 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) != ARRAY_SIZE(s->gpio)); |
| 614 | for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { |
| 615 | Object *obj = OBJECT(&s->gpio[i]); |
| 616 | |
| 617 | object_property_set_uint(obj, "reset-pullup", |
| 618 | npcm8xx_gpio[i].reset_pu, &error_abort); |
| 619 | object_property_set_uint(obj, "reset-pulldown", |
| 620 | npcm8xx_gpio[i].reset_pd, &error_abort); |
| 621 | object_property_set_uint(obj, "reset-osrc", |
| 622 | npcm8xx_gpio[i].reset_osrc, &error_abort); |
| 623 | object_property_set_uint(obj, "reset-odsc", |
| 624 | npcm8xx_gpio[i].reset_odsc, &error_abort); |
| 625 | sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); |
| 626 | sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr); |
| 627 | sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, |
| 628 | npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i)); |
| 629 | } |
| 630 | |
| 631 | /* SMBus modules. Cannot fail. */ |
| 632 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus)); |
| 633 | for (i = 0; i < ARRAY_SIZE(s->smbus); i++) { |
| 634 | Object *obj = OBJECT(&s->smbus[i]); |
| 635 | |
| 636 | sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); |
| 637 | sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]); |
| 638 | sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, |
| 639 | npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i)); |
| 640 | } |
| 641 | |
| 642 | /* USB Host */ |
| 643 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) != ARRAY_SIZE(s->ehci)); |
| 644 | for (i = 0; i < ARRAY_SIZE(s->ehci); i++) { |
| 645 | object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, |
| 646 | &error_abort); |
| 647 | sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); |
| 648 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[i]); |
| 649 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
| 650 | npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i)); |
| 651 | } |
| 652 | for (i = 0; i < ARRAY_SIZE(s->ohci); i++) { |
| 653 | object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus.0", |
| 654 | &error_abort); |
| 655 | object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, |
| 656 | &error_abort); |
| 657 | object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, |
| 658 | &error_abort); |
| 659 | sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); |
| 660 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[i]); |
| 661 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, |
| 662 | npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i)); |
| 663 | } |
| 664 | |
| 665 | /* PWM Modules. Cannot fail. */ |
| 666 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm)); |
| 667 | for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { |
| 668 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); |
| 669 | |
| 670 | qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( |
| 671 | DEVICE(&s->clk), "apb3-clock")); |
| 672 | sysbus_realize(sbd, &error_abort); |
| 673 | sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]); |
| 674 | sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i)); |
| 675 | } |
| 676 | |
| 677 | /* MFT Modules. Cannot fail. */ |
| 678 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) != ARRAY_SIZE(s->mft)); |
| 679 | for (i = 0; i < ARRAY_SIZE(s->mft); i++) { |
| 680 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]); |
| 681 | |
| 682 | qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", |
| 683 | qdev_get_clock_out(DEVICE(&s->clk), |
| 684 | "apb4-clock")); |
| 685 | sysbus_realize(sbd, &error_abort); |
| 686 | sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]); |
| 687 | sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i)); |
| 688 | } |
| 689 | |
| 690 | /* |
| 691 | * GMAC Modules. Cannot fail. |
| 692 | */ |
| 693 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gmac_addr) != ARRAY_SIZE(s->gmac)); |
| 694 | for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { |
| 695 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]); |
| 696 | |
| 697 | /* This is used to make sure that the NIC can create the device */ |
| 698 | qemu_configure_nic_device(DEVICE(sbd), false, NULL); |
| 699 | |
| 700 | /* |
| 701 | * The device exists regardless of whether it's connected to a QEMU |
| 702 | * netdev backend. So always instantiate it even if there is no |
| 703 | * backend. |
| 704 | */ |
| 705 | sysbus_realize(sbd, &error_abort); |
| 706 | sysbus_mmio_map(sbd, 0, npcm8xx_gmac_addr[i]); |
| 707 | /* |
| 708 | * N.B. The values for the second argument sysbus_connect_irq are |
| 709 | * chosen to match the registration order in npcm7xx_emc_realize. |
| 710 | */ |
| 711 | sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_GMAC1_IRQ + i)); |
| 712 | } |
| 713 | /* |
| 714 | * GMAC Physical Coding Sublayer(PCS) Module. Cannot fail. |
| 715 | */ |
| 716 | sysbus_realize(SYS_BUS_DEVICE(&s->pcs), &error_abort); |
| 717 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcs), 0, NPCM8XX_PCS_BA); |
| 718 | |
| 719 | /* |
| 720 | * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects |
| 721 | * specified, but this is a programming error. |
| 722 | */ |
| 723 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu)); |
| 724 | for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { |
| 725 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]); |
| 726 | int j; |
| 727 | |
| 728 | object_property_set_int(OBJECT(sbd), "cs-count", |
| 729 | npcm8xx_fiu[i].cs_count, &error_abort); |
| 730 | object_property_set_int(OBJECT(sbd), "flash-size", |
| 731 | npcm8xx_fiu[i].flash_size, &error_abort); |
| 732 | sysbus_realize(sbd, &error_abort); |
| 733 | |
| 734 | sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr); |
| 735 | for (j = 0; j < npcm8xx_fiu[i].cs_count; j++) { |
| 736 | sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]); |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | /* RAM2 (SRAM) */ |
| 741 | memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", |
| 742 | NPCM8XX_RAM2_SZ, &error_abort); |
| 743 | memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->sram); |
| 744 | |
| 745 | /* RAM3 (SRAM) */ |
| 746 | memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", |
| 747 | NPCM8XX_RAM3_SZ, &error_abort); |
| 748 | memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->ram3); |
| 749 | |
| 750 | /* Internal ROM */ |
| 751 | memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, |
| 752 | &error_abort); |
| 753 | memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->irom); |
| 754 | |
| 755 | /* SDHCI */ |
| 756 | sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); |
| 757 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); |
| 758 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, |
| 759 | npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); |
| 760 | |
| 761 | /* PSPI */ |
| 762 | sysbus_realize(SYS_BUS_DEVICE(&s->pspi), &error_abort); |
| 763 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pspi), 0, NPCM8XX_PSPI_BA); |
| 764 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pspi), 0, |
| 765 | npcm8xx_irq(s, NPCM8XX_PSPI_IRQ)); |
| 766 | |
| 767 | create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB); |
| 768 | create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB); |
| 769 | create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * KiB); |
| 770 | create_unimplemented_device("npcm8xx.pcierc", 0xe1000000, 64 * KiB); |
| 771 | create_unimplemented_device("npcm8xx.rootc", 0xe8000000, 128 * MiB); |
| 772 | create_unimplemented_device("npcm8xx.kcs", 0xf0007000, 4 * KiB); |
| 773 | create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * KiB); |
| 774 | create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * KiB); |
| 775 | create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * KiB); |
| 776 | create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * KiB); |
| 777 | create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * KiB); |
| 778 | create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB); |
| 779 | create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB); |
| 780 | create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB); |
| 781 | create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB); |
| 782 | create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB); |
| 783 | create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB); |
| 784 | create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * KiB); |
| 785 | create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * KiB); |
| 786 | create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * KiB); |
| 787 | create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * KiB); |
| 788 | create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * KiB); |
| 789 | create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * MiB); |
| 790 | create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * KiB); |
| 791 | create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * KiB); |
| 792 | create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * KiB); |
| 793 | create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * KiB); |
| 794 | create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * KiB); |
| 795 | create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * KiB); |
| 796 | create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * KiB); |
| 797 | create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * KiB); |
| 798 | create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * KiB); |
| 799 | create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * KiB); |
| 800 | create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * KiB); |
| 801 | create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * KiB); |
| 802 | create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * KiB); |
| 803 | create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * KiB); |
| 804 | create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * KiB); |
| 805 | create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * KiB); |
| 806 | create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * KiB); |
| 807 | create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * KiB); |
| 808 | create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * KiB); |
| 809 | create_unimplemented_device("npcm8xx.pci_mbox1", 0xf0848000, 64 * KiB); |
| 810 | create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * KiB); |
| 811 | create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * KiB); |
| 812 | create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * KiB); |
| 813 | create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * KiB); |
| 814 | create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * KiB); |
| 815 | create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * KiB); |
| 816 | create_unimplemented_device("npcm8xx.pci_mbox2", 0xf0868000, 64 * KiB); |
| 817 | create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * KiB); |
| 818 | create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * KiB); |
| 819 | create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * KiB); |
| 820 | create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * KiB); |
| 821 | create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * KiB); |
| 822 | create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * KiB); |
| 823 | create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * MiB); |
| 824 | create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * MiB); |
| 825 | create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * KiB); |
| 826 | create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256); |
| 827 | } |
| 828 | |
| 829 | static const Property npcm8xx_properties[] = { |
| 830 | DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION, |
| 831 | MemoryRegion *), |
| 832 | }; |
| 833 | |
| 834 | static void npcm8xx_class_init(ObjectClass *oc, const void *data) |
| 835 | { |
| 836 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 837 | NPCM8xxClass *nc = NPCM8XX_CLASS(oc); |
| 838 | |
| 839 | dc->realize = npcm8xx_realize; |
| 840 | dc->user_creatable = false; |
| 841 | nc->disabled_modules = 0x00000000; |
| 842 | nc->num_cpus = NPCM8XX_MAX_NUM_CPUS; |
| 843 | device_class_set_props(dc, npcm8xx_properties); |
| 844 | } |
| 845 | |
| 846 | static const TypeInfo npcm8xx_soc_types[] = { |
| 847 | { |
| 848 | .name = TYPE_NPCM8XX, |
| 849 | .parent = TYPE_DEVICE, |
| 850 | .instance_size = sizeof(NPCM8xxState), |
| 851 | .instance_init = npcm8xx_init, |
| 852 | .class_size = sizeof(NPCM8xxClass), |
| 853 | .class_init = npcm8xx_class_init, |
| 854 | }, |
| 855 | }; |
| 856 | |
| 857 | DEFINE_TYPES(npcm8xx_soc_types); |