| 1 | /* |
| 2 | * Machine definitions for boards featuring an NPCM8xx SoC. |
| 3 | * |
| 4 | * Copyright 2021 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | |
| 19 | #include "chardev/char.h" |
| 20 | #include "hw/core/boards.h" |
| 21 | #include "hw/arm/npcm8xx.h" |
| 22 | #include "hw/arm/machines-qom.h" |
| 23 | #include "hw/core/cpu.h" |
| 24 | #include "hw/core/loader.h" |
| 25 | #include "hw/core/qdev.h" |
| 26 | #include "hw/core/qdev-properties.h" |
| 27 | #include "qapi/error.h" |
| 28 | #include "qemu/error-report.h" |
| 29 | #include "qemu/datadir.h" |
| 30 | #include "qemu/units.h" |
| 31 | |
| 32 | #define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff |
| 33 | |
| 34 | static const char npcm8xx_default_bootrom[] = "npcm8xx_bootrom.bin"; |
| 35 | |
| 36 | static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc) |
| 37 | { |
| 38 | const char *bios_name = machine->firmware ?: npcm8xx_default_bootrom; |
| 39 | g_autofree char *filename = NULL; |
| 40 | int ret; |
| 41 | |
| 42 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 43 | if (!filename) { |
| 44 | error_report("Could not find ROM image '%s'", bios_name); |
| 45 | if (!machine->kernel_filename) { |
| 46 | /* We can't boot without a bootrom or a kernel image. */ |
| 47 | exit(1); |
| 48 | } |
| 49 | return; |
| 50 | } |
| 51 | ret = load_image_mr(filename, machine->ram); |
| 52 | if (ret < 0) { |
| 53 | error_report("Failed to load ROM image '%s'", filename); |
| 54 | exit(1); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no, |
| 59 | const char *flash_type, DriveInfo *dinfo) |
| 60 | { |
| 61 | DeviceState *flash; |
| 62 | qemu_irq flash_cs; |
| 63 | |
| 64 | flash = qdev_new(flash_type); |
| 65 | if (dinfo) { |
| 66 | qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); |
| 67 | } |
| 68 | qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); |
| 69 | |
| 70 | flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); |
| 71 | qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs); |
| 72 | } |
| 73 | |
| 74 | static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram) |
| 75 | { |
| 76 | memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram); |
| 77 | |
| 78 | object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), |
| 79 | &error_abort); |
| 80 | } |
| 81 | |
| 82 | static NPCM8xxState *npcm8xx_create_soc(MachineState *machine, |
| 83 | uint32_t hw_straps) |
| 84 | { |
| 85 | NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_GET_CLASS(machine); |
| 86 | Object *obj; |
| 87 | |
| 88 | obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", |
| 89 | &error_abort, NULL); |
| 90 | object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort); |
| 91 | |
| 92 | return NPCM8XX(obj); |
| 93 | } |
| 94 | |
| 95 | static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num) |
| 96 | { |
| 97 | g_assert(num < ARRAY_SIZE(soc->smbus)); |
| 98 | return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus")); |
| 99 | } |
| 100 | |
| 101 | static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine, |
| 102 | NPCM8xxState *soc, const int *fan_counts) |
| 103 | { |
| 104 | SplitIRQ *splitters = machine->fan_splitter; |
| 105 | |
| 106 | /* |
| 107 | * PWM 0~3 belong to module 0 output 0~3. |
| 108 | * PWM 4~7 belong to module 1 output 0~3. |
| 109 | */ |
| 110 | for (int i = 0; i < NPCM8XX_NR_PWM_MODULES; ++i) { |
| 111 | for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) { |
| 112 | int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j; |
| 113 | DeviceState *splitter; |
| 114 | |
| 115 | if (fan_counts[splitter_no] < 1) { |
| 116 | continue; |
| 117 | } |
| 118 | object_initialize_child(OBJECT(machine), "fan-splitter[*]", |
| 119 | &splitters[splitter_no], TYPE_SPLIT_IRQ); |
| 120 | splitter = DEVICE(&splitters[splitter_no]); |
| 121 | qdev_prop_set_uint16(splitter, "num-lines", |
| 122 | fan_counts[splitter_no]); |
| 123 | qdev_realize(splitter, NULL, &error_abort); |
| 124 | qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", |
| 125 | j, qdev_get_gpio_in(splitter, 0)); |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter, |
| 131 | int fan_no, int output_no) |
| 132 | { |
| 133 | DeviceState *fan; |
| 134 | int fan_input; |
| 135 | qemu_irq fan_duty_gpio; |
| 136 | |
| 137 | g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT); |
| 138 | /* |
| 139 | * Fan 0~1 belong to module 0 input 0~1. |
| 140 | * Fan 2~3 belong to module 1 input 0~1. |
| 141 | * ... |
| 142 | * Fan 14~15 belong to module 7 input 0~1. |
| 143 | * Fan 16~17 belong to module 0 input 2~3. |
| 144 | * Fan 18~19 belong to module 1 input 2~3. |
| 145 | */ |
| 146 | if (fan_no < 16) { |
| 147 | fan = DEVICE(&soc->mft[fan_no / 2]); |
| 148 | fan_input = fan_no % 2; |
| 149 | } else { |
| 150 | fan = DEVICE(&soc->mft[(fan_no - 16) / 2]); |
| 151 | fan_input = fan_no % 2 + 2; |
| 152 | } |
| 153 | |
| 154 | /* Connect the Fan to PWM module */ |
| 155 | fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input); |
| 156 | qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio); |
| 157 | } |
| 158 | |
| 159 | static void npcm845_evb_i2c_init(NPCM8xxState *soc) |
| 160 | { |
| 161 | /* tmp100 temperature sensor on SVB, tmp105 is compatible */ |
| 162 | i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48); |
| 163 | } |
| 164 | |
| 165 | static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *soc) |
| 166 | { |
| 167 | SplitIRQ *splitter = machine->fan_splitter; |
| 168 | static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0}; |
| 169 | |
| 170 | npcm8xx_init_pwm_splitter(machine, soc, fan_counts); |
| 171 | npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0); |
| 172 | npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1); |
| 173 | npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0); |
| 174 | npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1); |
| 175 | npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0); |
| 176 | npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); |
| 177 | npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0); |
| 178 | npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1); |
| 179 | npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0); |
| 180 | npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1); |
| 181 | npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0); |
| 182 | npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1); |
| 183 | npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0); |
| 184 | npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1); |
| 185 | npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0); |
| 186 | npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1); |
| 187 | } |
| 188 | |
| 189 | static void npcm845_evb_init(MachineState *machine) |
| 190 | { |
| 191 | NPCM8xxState *soc; |
| 192 | |
| 193 | soc = npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS); |
| 194 | npcm8xx_connect_dram(soc, machine->ram); |
| 195 | qdev_realize(DEVICE(soc), NULL, &error_fatal); |
| 196 | |
| 197 | npcm8xx_load_bootrom(machine, soc); |
| 198 | npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0)); |
| 199 | npcm845_evb_i2c_init(soc); |
| 200 | npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc); |
| 201 | npcm8xx_load_kernel(machine, soc, &NPCM8XX_MACHINE(machine)->bootinfo); |
| 202 | } |
| 203 | |
| 204 | static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type) |
| 205 | { |
| 206 | NPCM8xxClass *sc = NPCM8XX_CLASS(object_class_by_name(type)); |
| 207 | MachineClass *mc = MACHINE_CLASS(nmc); |
| 208 | |
| 209 | nmc->soc_type = type; |
| 210 | mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; |
| 211 | } |
| 212 | |
| 213 | static void npcm8xx_machine_class_init(ObjectClass *oc, const void *data) |
| 214 | { |
| 215 | MachineClass *mc = MACHINE_CLASS(oc); |
| 216 | static const char * const valid_cpu_types[] = { |
| 217 | ARM_CPU_TYPE_NAME("cortex-a35"), |
| 218 | NULL |
| 219 | }; |
| 220 | |
| 221 | mc->no_floppy = 1; |
| 222 | mc->no_cdrom = 1; |
| 223 | mc->no_parallel = 1; |
| 224 | mc->default_ram_id = "ram"; |
| 225 | mc->valid_cpu_types = valid_cpu_types; |
| 226 | } |
| 227 | |
| 228 | static void npcm845_evb_machine_class_init(ObjectClass *oc, const void *data) |
| 229 | { |
| 230 | NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc); |
| 231 | MachineClass *mc = MACHINE_CLASS(oc); |
| 232 | |
| 233 | npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX); |
| 234 | |
| 235 | mc->desc = "Nuvoton NPCM845 Evaluation Board (Cortex-A35)"; |
| 236 | mc->init = npcm845_evb_init; |
| 237 | mc->default_ram_size = 1 * GiB; |
| 238 | }; |
| 239 | |
| 240 | static const TypeInfo npcm8xx_machine_types[] = { |
| 241 | { |
| 242 | .name = TYPE_NPCM8XX_MACHINE, |
| 243 | .parent = TYPE_MACHINE, |
| 244 | .instance_size = sizeof(NPCM8xxMachine), |
| 245 | .class_size = sizeof(NPCM8xxMachineClass), |
| 246 | .class_init = npcm8xx_machine_class_init, |
| 247 | .abstract = true, |
| 248 | }, { |
| 249 | .name = MACHINE_TYPE_NAME("npcm845-evb"), |
| 250 | .parent = TYPE_NPCM8XX_MACHINE, |
| 251 | .class_init = npcm845_evb_machine_class_init, |
| 252 | .interfaces = aarch64_machine_interfaces, |
| 253 | }, |
| 254 | }; |
| 255 | |
| 256 | DEFINE_TYPES(npcm8xx_machine_types) |