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1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
24 #include "qapi/error.h"
25 #include "target/arm/cpu.h"
26 #include "system/address-spaces.h"
27 #include "exec/cpu-common.h"
28 #include "hw/core/irq.h"
29 #include "hw/core/qdev-properties.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/omap.h"
32 #include "hw/sd/sd.h"
33 #include "system/blockdev.h"
34 #include "system/system.h"
35 #include "hw/dma/soc_dma.h"
36 #include "system/qtest.h"
37 #include "system/reset.h"
38 #include "system/runstate.h"
39 #include "system/rtc.h"
40 #include "qemu/range.h"
41 #include "hw/core/sysbus.h"
42 #include "qemu/cutils.h"
43 #include "qemu/bcd.h"
44 #include "target/arm/cpu-qom.h"
45 #include "trace.h"
46
47 /* MPU OS timers */
48 struct omap_mpu_timer_s {
49 MemoryRegion iomem;
50 qemu_irq irq;
51 omap_clk clk;
52 uint32_t val;
53 int64_t time;
54 QEMUTimer *timer;
55 QEMUBH *tick;
56 int64_t rate;
57 int it_ena;
58
59 int enable;
60 int ptv;
61 int ar;
62 int st;
63 uint32_t reset_val;
64 };
65
66 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
67 {
68 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time;
69
70 if (timer->st && timer->enable && timer->rate)
71 return timer->val - muldiv64(distance >> (timer->ptv + 1),
72 timer->rate, NANOSECONDS_PER_SECOND);
73 else
74 return timer->val;
75 }
76
77 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
78 {
79 timer->val = omap_timer_read(timer);
80 timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
81 }
82
83 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
84 {
85 int64_t expires;
86
87 if (timer->enable && timer->st && timer->rate) {
88 timer->val = timer->reset_val; /* Should skip this on clk enable */
89 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
90 NANOSECONDS_PER_SECOND, timer->rate);
91
92 /* If timer expiry would be sooner than in about 1 ms and
93 * auto-reload isn't set, then fire immediately. This is a hack
94 * to make systems like PalmOS run in acceptable time. PalmOS
95 * sets the interval to a very low value and polls the status bit
96 * in a busy loop when it wants to sleep just a couple of CPU
97 * ticks. */
98 if (expires > (NANOSECONDS_PER_SECOND >> 10) || timer->ar) {
99 timer_mod(timer->timer, timer->time + expires);
100 } else {
101 qemu_bh_schedule(timer->tick);
102 }
103 } else
104 timer_del(timer->timer);
105 }
106
107 static void omap_timer_fire(void *opaque)
108 {
109 struct omap_mpu_timer_s *timer = opaque;
110
111 if (!timer->ar) {
112 timer->val = 0;
113 timer->st = 0;
114 }
115
116 if (timer->it_ena)
117 /* Edge-triggered irq */
118 qemu_irq_pulse(timer->irq);
119 }
120
121 static void omap_timer_tick(void *opaque)
122 {
123 struct omap_mpu_timer_s *timer = opaque;
124
125 omap_timer_sync(timer);
126 omap_timer_fire(timer);
127 omap_timer_update(timer);
128 }
129
130 static void omap_timer_clk_update(void *opaque, int line, int on)
131 {
132 struct omap_mpu_timer_s *timer = opaque;
133
134 omap_timer_sync(timer);
135 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
136 omap_timer_update(timer);
137 }
138
139 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
140 {
141 omap_clk_adduser(timer->clk,
142 qemu_allocate_irq(omap_timer_clk_update, timer, 0));
143 timer->rate = omap_clk_getrate(timer->clk);
144 }
145
146 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
147 unsigned size)
148 {
149 struct omap_mpu_timer_s *s = opaque;
150
151 if (size != 4) {
152 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
153 " with bad width %d\n", __func__, addr, size);
154 return 0;
155 }
156
157 switch (addr) {
158 case 0x00: /* CNTL_TIMER */
159 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
160
161 case 0x04: /* LOAD_TIM */
162 break;
163
164 case 0x08: /* READ_TIM */
165 return omap_timer_read(s);
166 }
167
168 OMAP_BAD_REG(addr);
169 return 0;
170 }
171
172 static void omap_mpu_timer_write(void *opaque, hwaddr addr,
173 uint64_t value, unsigned size)
174 {
175 struct omap_mpu_timer_s *s = opaque;
176
177 if (size != 4) {
178 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
179 " with bad width %d\n", __func__, addr, size);
180 return;
181 }
182
183 switch (addr) {
184 case 0x00: /* CNTL_TIMER */
185 omap_timer_sync(s);
186 s->enable = (value >> 5) & 1;
187 s->ptv = (value >> 2) & 7;
188 s->ar = (value >> 1) & 1;
189 s->st = value & 1;
190 omap_timer_update(s);
191 return;
192
193 case 0x04: /* LOAD_TIM */
194 s->reset_val = value;
195 return;
196
197 case 0x08: /* READ_TIM */
198 OMAP_RO_REG(addr);
199 break;
200
201 default:
202 OMAP_BAD_REG(addr);
203 }
204 }
205
206 static const MemoryRegionOps omap_mpu_timer_ops = {
207 .read = omap_mpu_timer_read,
208 .write = omap_mpu_timer_write,
209 .endianness = DEVICE_LITTLE_ENDIAN,
210 };
211
212 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
213 {
214 timer_del(s->timer);
215 s->enable = 0;
216 s->reset_val = 31337;
217 s->val = 0;
218 s->ptv = 0;
219 s->ar = 0;
220 s->st = 0;
221 s->it_ena = 1;
222 }
223
224 static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
225 hwaddr base,
226 qemu_irq irq, omap_clk clk)
227 {
228 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1);
229
230 s->irq = irq;
231 s->clk = clk;
232 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s);
233 s->tick = qemu_bh_new(omap_timer_fire, s);
234 omap_mpu_timer_reset(s);
235 omap_timer_clk_setup(s);
236
237 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s,
238 "omap-mpu-timer", 0x100);
239
240 memory_region_add_subregion(system_memory, base, &s->iomem);
241
242 return s;
243 }
244
245 /* Watchdog timer */
246 struct omap_watchdog_timer_s {
247 struct omap_mpu_timer_s timer;
248 MemoryRegion iomem;
249 uint8_t last_wr;
250 int mode;
251 int free;
252 int reset;
253 };
254
255 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
256 unsigned size)
257 {
258 struct omap_watchdog_timer_s *s = opaque;
259
260 if (size != 2) {
261 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
262 " with bad width %d\n", __func__, addr, size);
263 return 0;
264 }
265
266 switch (addr) {
267 case 0x00: /* CNTL_TIMER */
268 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
269 (s->timer.st << 7) | (s->free << 1);
270
271 case 0x04: /* READ_TIMER */
272 return omap_timer_read(&s->timer);
273
274 case 0x08: /* TIMER_MODE */
275 return s->mode << 15;
276 }
277
278 OMAP_BAD_REG(addr);
279 return 0;
280 }
281
282 static void omap_wd_timer_write(void *opaque, hwaddr addr,
283 uint64_t value, unsigned size)
284 {
285 struct omap_watchdog_timer_s *s = opaque;
286
287 if (size != 2) {
288 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
289 " with bad width %d\n", __func__, addr, size);
290 return;
291 }
292
293 switch (addr) {
294 case 0x00: /* CNTL_TIMER */
295 omap_timer_sync(&s->timer);
296 s->timer.ptv = (value >> 9) & 7;
297 s->timer.ar = (value >> 8) & 1;
298 s->timer.st = (value >> 7) & 1;
299 s->free = (value >> 1) & 1;
300 omap_timer_update(&s->timer);
301 break;
302
303 case 0x04: /* LOAD_TIMER */
304 s->timer.reset_val = value & 0xffff;
305 break;
306
307 case 0x08: /* TIMER_MODE */
308 if (!s->mode && ((value >> 15) & 1))
309 omap_clk_get(s->timer.clk);
310 s->mode |= (value >> 15) & 1;
311 if (s->last_wr == 0xf5) {
312 if ((value & 0xff) == 0xa0) {
313 if (s->mode) {
314 s->mode = 0;
315 omap_clk_put(s->timer.clk);
316 }
317 } else {
318 /* XXX: on T|E hardware somehow this has no effect,
319 * on Zire 71 it works as specified. */
320 s->reset = 1;
321 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
322 }
323 }
324 s->last_wr = value & 0xff;
325 break;
326
327 default:
328 OMAP_BAD_REG(addr);
329 }
330 }
331
332 static const MemoryRegionOps omap_wd_timer_ops = {
333 .read = omap_wd_timer_read,
334 .write = omap_wd_timer_write,
335 .endianness = DEVICE_NATIVE_ENDIAN,
336 };
337
338 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
339 {
340 timer_del(s->timer.timer);
341 if (!s->mode)
342 omap_clk_get(s->timer.clk);
343 s->mode = 1;
344 s->free = 1;
345 s->reset = 0;
346 s->timer.enable = 1;
347 s->timer.it_ena = 1;
348 s->timer.reset_val = 0xffff;
349 s->timer.val = 0;
350 s->timer.st = 0;
351 s->timer.ptv = 0;
352 s->timer.ar = 0;
353 omap_timer_update(&s->timer);
354 }
355
356 static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
357 hwaddr base,
358 qemu_irq irq, omap_clk clk)
359 {
360 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1);
361
362 s->timer.irq = irq;
363 s->timer.clk = clk;
364 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
365 omap_wd_timer_reset(s);
366 omap_timer_clk_setup(&s->timer);
367
368 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s,
369 "omap-wd-timer", 0x100);
370 memory_region_add_subregion(memory, base, &s->iomem);
371
372 return s;
373 }
374
375 /* 32-kHz timer */
376 struct omap_32khz_timer_s {
377 struct omap_mpu_timer_s timer;
378 MemoryRegion iomem;
379 };
380
381 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
382 unsigned size)
383 {
384 struct omap_32khz_timer_s *s = opaque;
385 int offset = addr & OMAP_MPUI_REG_MASK;
386
387 if (size != 4) {
388 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
389 " with bad width %d\n", __func__, addr, size);
390 return 0;
391 }
392
393 switch (offset) {
394 case 0x00: /* TVR */
395 return s->timer.reset_val;
396
397 case 0x04: /* TCR */
398 return omap_timer_read(&s->timer);
399
400 case 0x08: /* CR */
401 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
402
403 default:
404 break;
405 }
406 OMAP_BAD_REG(addr);
407 return 0;
408 }
409
410 static void omap_os_timer_write(void *opaque, hwaddr addr,
411 uint64_t value, unsigned size)
412 {
413 struct omap_32khz_timer_s *s = opaque;
414 int offset = addr & OMAP_MPUI_REG_MASK;
415
416 if (size != 4) {
417 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
418 " with bad width %d\n", __func__, addr, size);
419 return;
420 }
421
422 switch (offset) {
423 case 0x00: /* TVR */
424 s->timer.reset_val = value & 0x00ffffff;
425 break;
426
427 case 0x04: /* TCR */
428 OMAP_RO_REG(addr);
429 break;
430
431 case 0x08: /* CR */
432 s->timer.ar = (value >> 3) & 1;
433 s->timer.it_ena = (value >> 2) & 1;
434 if (s->timer.st != (value & 1) || (value & 2)) {
435 omap_timer_sync(&s->timer);
436 s->timer.enable = value & 1;
437 s->timer.st = value & 1;
438 omap_timer_update(&s->timer);
439 }
440 break;
441
442 default:
443 OMAP_BAD_REG(addr);
444 }
445 }
446
447 static const MemoryRegionOps omap_os_timer_ops = {
448 .read = omap_os_timer_read,
449 .write = omap_os_timer_write,
450 .endianness = DEVICE_NATIVE_ENDIAN,
451 };
452
453 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
454 {
455 timer_del(s->timer.timer);
456 s->timer.enable = 0;
457 s->timer.it_ena = 0;
458 s->timer.reset_val = 0x00ffffff;
459 s->timer.val = 0;
460 s->timer.st = 0;
461 s->timer.ptv = 0;
462 s->timer.ar = 1;
463 }
464
465 static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
466 hwaddr base,
467 qemu_irq irq, omap_clk clk)
468 {
469 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1);
470
471 s->timer.irq = irq;
472 s->timer.clk = clk;
473 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer);
474 omap_os_timer_reset(s);
475 omap_timer_clk_setup(&s->timer);
476
477 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s,
478 "omap-os-timer", 0x800);
479 memory_region_add_subregion(memory, base, &s->iomem);
480
481 return s;
482 }
483
484 /* Ultra Low-Power Device Module */
485 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
486 unsigned size)
487 {
488 struct omap_mpu_state_s *s = opaque;
489 uint16_t ret;
490
491 if (size != 2) {
492 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
493 " with bad width %d\n", __func__, addr, size);
494 return 0;
495 }
496
497 switch (addr) {
498 case 0x14: /* IT_STATUS */
499 ret = s->ulpd_pm_regs[addr >> 2];
500 s->ulpd_pm_regs[addr >> 2] = 0;
501 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
502 return ret;
503
504 case 0x18: /* Reserved */
505 case 0x1c: /* Reserved */
506 case 0x20: /* Reserved */
507 case 0x28: /* Reserved */
508 case 0x2c: /* Reserved */
509 OMAP_BAD_REG(addr);
510 /* fall through */
511 case 0x00: /* COUNTER_32_LSB */
512 case 0x04: /* COUNTER_32_MSB */
513 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
514 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
515 case 0x10: /* GAUGING_CTRL */
516 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
517 case 0x30: /* CLOCK_CTRL */
518 case 0x34: /* SOFT_REQ */
519 case 0x38: /* COUNTER_32_FIQ */
520 case 0x3c: /* DPLL_CTRL */
521 case 0x40: /* STATUS_REQ */
522 /* XXX: check clk::usecount state for every clock */
523 case 0x48: /* LOCL_TIME */
524 case 0x4c: /* APLL_CTRL */
525 case 0x50: /* POWER_CTRL */
526 return s->ulpd_pm_regs[addr >> 2];
527 }
528
529 OMAP_BAD_REG(addr);
530 return 0;
531 }
532
533 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
534 uint16_t diff, uint16_t value)
535 {
536 if (diff & (1 << 4)) /* USB_MCLK_EN */
537 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
538 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
539 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
540 }
541
542 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
543 uint16_t diff, uint16_t value)
544 {
545 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
546 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
547 if (diff & (1 << 1)) /* SOFT_COM_REQ */
548 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
549 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
550 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
551 if (diff & (1 << 3)) /* SOFT_USB_REQ */
552 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
553 }
554
555 static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
556 uint64_t value, unsigned size)
557 {
558 struct omap_mpu_state_s *s = opaque;
559 int64_t now, ticks;
560 int div, mult;
561 static const int bypass_div[4] = { 1, 2, 4, 4 };
562 uint16_t diff;
563
564 if (size != 2) {
565 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
566 " with bad width %d\n", __func__, addr, size);
567 return;
568 }
569
570 switch (addr) {
571 case 0x00: /* COUNTER_32_LSB */
572 case 0x04: /* COUNTER_32_MSB */
573 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
574 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
575 case 0x14: /* IT_STATUS */
576 case 0x40: /* STATUS_REQ */
577 OMAP_RO_REG(addr);
578 break;
579
580 case 0x10: /* GAUGING_CTRL */
581 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
582 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
583 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
584
585 if (value & 1)
586 s->ulpd_gauge_start = now;
587 else {
588 now -= s->ulpd_gauge_start;
589
590 /* 32-kHz ticks */
591 ticks = muldiv64(now, 32768, NANOSECONDS_PER_SECOND);
592 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
593 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
594 if (ticks >> 32) /* OVERFLOW_32K */
595 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
596
597 /* High frequency ticks */
598 ticks = muldiv64(now, 12000000, NANOSECONDS_PER_SECOND);
599 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
600 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
601 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
602 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
603
604 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
605 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
606 }
607 }
608 s->ulpd_pm_regs[addr >> 2] = value;
609 break;
610
611 case 0x18: /* Reserved */
612 case 0x1c: /* Reserved */
613 case 0x20: /* Reserved */
614 case 0x28: /* Reserved */
615 case 0x2c: /* Reserved */
616 OMAP_BAD_REG(addr);
617 /* fall through */
618 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
619 case 0x38: /* COUNTER_32_FIQ */
620 case 0x48: /* LOCL_TIME */
621 case 0x50: /* POWER_CTRL */
622 s->ulpd_pm_regs[addr >> 2] = value;
623 break;
624
625 case 0x30: /* CLOCK_CTRL */
626 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
627 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
628 omap_ulpd_clk_update(s, diff, value);
629 break;
630
631 case 0x34: /* SOFT_REQ */
632 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
633 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
634 omap_ulpd_req_update(s, diff, value);
635 break;
636
637 case 0x3c: /* DPLL_CTRL */
638 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
639 * omitted altogether, probably a typo. */
640 /* This register has identical semantics with DPLL(1:3) control
641 * registers, see omap_dpll_write() */
642 diff = s->ulpd_pm_regs[addr >> 2] & value;
643 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
644 if (diff & (0x3ff << 2)) {
645 if (value & (1 << 4)) { /* PLL_ENABLE */
646 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
647 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
648 } else {
649 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
650 mult = 1;
651 }
652 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
653 }
654
655 /* Enter the desired mode. */
656 s->ulpd_pm_regs[addr >> 2] =
657 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
658 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
659
660 /* Act as if the lock is restored. */
661 s->ulpd_pm_regs[addr >> 2] |= 2;
662 break;
663
664 case 0x4c: /* APLL_CTRL */
665 diff = s->ulpd_pm_regs[addr >> 2] & value;
666 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
667 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
668 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
669 (value & (1 << 0)) ? "apll" : "dpll4"));
670 break;
671
672 default:
673 OMAP_BAD_REG(addr);
674 }
675 }
676
677 static const MemoryRegionOps omap_ulpd_pm_ops = {
678 .read = omap_ulpd_pm_read,
679 .write = omap_ulpd_pm_write,
680 .endianness = DEVICE_NATIVE_ENDIAN,
681 };
682
683 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
684 {
685 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
686 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
687 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
688 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
689 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
690 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
691 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
692 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
693 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
694 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
695 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
696 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
697 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
698 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
699 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
700 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
701 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
702 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
703 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
704 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
705 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
706 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
707 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
708 }
709
710 static void omap_ulpd_pm_init(MemoryRegion *system_memory,
711 hwaddr base,
712 struct omap_mpu_state_s *mpu)
713 {
714 memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu,
715 "omap-ulpd-pm", 0x800);
716 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
717 omap_ulpd_pm_reset(mpu);
718 }
719
720 /* OMAP Pin Configuration */
721 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
722 unsigned size)
723 {
724 struct omap_mpu_state_s *s = opaque;
725
726 if (size != 4) {
727 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
728 " with bad width %d\n", __func__, addr, size);
729 return 0;
730 }
731
732 switch (addr) {
733 case 0x00: /* FUNC_MUX_CTRL_0 */
734 case 0x04: /* FUNC_MUX_CTRL_1 */
735 case 0x08: /* FUNC_MUX_CTRL_2 */
736 return s->func_mux_ctrl[addr >> 2];
737
738 case 0x0c: /* COMP_MODE_CTRL_0 */
739 return s->comp_mode_ctrl[0];
740
741 case 0x10: /* FUNC_MUX_CTRL_3 */
742 case 0x14: /* FUNC_MUX_CTRL_4 */
743 case 0x18: /* FUNC_MUX_CTRL_5 */
744 case 0x1c: /* FUNC_MUX_CTRL_6 */
745 case 0x20: /* FUNC_MUX_CTRL_7 */
746 case 0x24: /* FUNC_MUX_CTRL_8 */
747 case 0x28: /* FUNC_MUX_CTRL_9 */
748 case 0x2c: /* FUNC_MUX_CTRL_A */
749 case 0x30: /* FUNC_MUX_CTRL_B */
750 case 0x34: /* FUNC_MUX_CTRL_C */
751 case 0x38: /* FUNC_MUX_CTRL_D */
752 return s->func_mux_ctrl[(addr >> 2) - 1];
753
754 case 0x40: /* PULL_DWN_CTRL_0 */
755 case 0x44: /* PULL_DWN_CTRL_1 */
756 case 0x48: /* PULL_DWN_CTRL_2 */
757 case 0x4c: /* PULL_DWN_CTRL_3 */
758 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
759
760 case 0x50: /* GATE_INH_CTRL_0 */
761 return s->gate_inh_ctrl[0];
762
763 case 0x60: /* VOLTAGE_CTRL_0 */
764 return s->voltage_ctrl[0];
765
766 case 0x70: /* TEST_DBG_CTRL_0 */
767 return s->test_dbg_ctrl[0];
768
769 case 0x80: /* MOD_CONF_CTRL_0 */
770 return s->mod_conf_ctrl[0];
771 }
772
773 OMAP_BAD_REG(addr);
774 return 0;
775 }
776
777 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
778 uint32_t diff, uint32_t value)
779 {
780 if (s->compat1509) {
781 if (diff & (1 << 9)) /* BLUETOOTH */
782 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
783 (~value >> 9) & 1);
784 if (diff & (1 << 7)) /* USB.CLKO */
785 omap_clk_onoff(omap_findclk(s, "usb.clko"),
786 (value >> 7) & 1);
787 }
788 }
789
790 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
791 uint32_t diff, uint32_t value)
792 {
793 if (s->compat1509) {
794 if (diff & (1U << 31)) {
795 /* MCBSP3_CLK_HIZ_DI */
796 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);
797 }
798 if (diff & (1 << 1)) {
799 /* CLK32K */
800 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);
801 }
802 }
803 }
804
805 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
806 uint32_t diff, uint32_t value)
807 {
808 if (diff & (1U << 31)) {
809 /* CONF_MOD_UART3_CLK_MODE_R */
810 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
811 omap_findclk(s, ((value >> 31) & 1) ?
812 "ck_48m" : "armper_ck"));
813 }
814 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
815 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
816 omap_findclk(s, ((value >> 30) & 1) ?
817 "ck_48m" : "armper_ck"));
818 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
819 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
820 omap_findclk(s, ((value >> 29) & 1) ?
821 "ck_48m" : "armper_ck"));
822 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
823 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
824 omap_findclk(s, ((value >> 23) & 1) ?
825 "ck_48m" : "armper_ck"));
826 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
827 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
828 omap_findclk(s, ((value >> 12) & 1) ?
829 "ck_48m" : "armper_ck"));
830 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
831 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
832 }
833
834 static void omap_pin_cfg_write(void *opaque, hwaddr addr,
835 uint64_t value, unsigned size)
836 {
837 struct omap_mpu_state_s *s = opaque;
838 uint32_t diff;
839
840 if (size != 4) {
841 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
842 " with bad width %d\n", __func__, addr, size);
843 return;
844 }
845
846 switch (addr) {
847 case 0x00: /* FUNC_MUX_CTRL_0 */
848 diff = s->func_mux_ctrl[addr >> 2] ^ value;
849 s->func_mux_ctrl[addr >> 2] = value;
850 omap_pin_funcmux0_update(s, diff, value);
851 return;
852
853 case 0x04: /* FUNC_MUX_CTRL_1 */
854 diff = s->func_mux_ctrl[addr >> 2] ^ value;
855 s->func_mux_ctrl[addr >> 2] = value;
856 omap_pin_funcmux1_update(s, diff, value);
857 return;
858
859 case 0x08: /* FUNC_MUX_CTRL_2 */
860 s->func_mux_ctrl[addr >> 2] = value;
861 return;
862
863 case 0x0c: /* COMP_MODE_CTRL_0 */
864 s->comp_mode_ctrl[0] = value;
865 s->compat1509 = (value != 0x0000eaef);
866 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
867 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
868 return;
869
870 case 0x10: /* FUNC_MUX_CTRL_3 */
871 case 0x14: /* FUNC_MUX_CTRL_4 */
872 case 0x18: /* FUNC_MUX_CTRL_5 */
873 case 0x1c: /* FUNC_MUX_CTRL_6 */
874 case 0x20: /* FUNC_MUX_CTRL_7 */
875 case 0x24: /* FUNC_MUX_CTRL_8 */
876 case 0x28: /* FUNC_MUX_CTRL_9 */
877 case 0x2c: /* FUNC_MUX_CTRL_A */
878 case 0x30: /* FUNC_MUX_CTRL_B */
879 case 0x34: /* FUNC_MUX_CTRL_C */
880 case 0x38: /* FUNC_MUX_CTRL_D */
881 s->func_mux_ctrl[(addr >> 2) - 1] = value;
882 return;
883
884 case 0x40: /* PULL_DWN_CTRL_0 */
885 case 0x44: /* PULL_DWN_CTRL_1 */
886 case 0x48: /* PULL_DWN_CTRL_2 */
887 case 0x4c: /* PULL_DWN_CTRL_3 */
888 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
889 return;
890
891 case 0x50: /* GATE_INH_CTRL_0 */
892 s->gate_inh_ctrl[0] = value;
893 return;
894
895 case 0x60: /* VOLTAGE_CTRL_0 */
896 s->voltage_ctrl[0] = value;
897 return;
898
899 case 0x70: /* TEST_DBG_CTRL_0 */
900 s->test_dbg_ctrl[0] = value;
901 return;
902
903 case 0x80: /* MOD_CONF_CTRL_0 */
904 diff = s->mod_conf_ctrl[0] ^ value;
905 s->mod_conf_ctrl[0] = value;
906 omap_pin_modconf1_update(s, diff, value);
907 return;
908
909 default:
910 OMAP_BAD_REG(addr);
911 }
912 }
913
914 static const MemoryRegionOps omap_pin_cfg_ops = {
915 .read = omap_pin_cfg_read,
916 .write = omap_pin_cfg_write,
917 .endianness = DEVICE_NATIVE_ENDIAN,
918 };
919
920 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
921 {
922 /* Start in Compatibility Mode. */
923 mpu->compat1509 = 1;
924 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
925 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
926 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
927 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
928 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
929 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
930 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
931 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
932 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
933 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
934 }
935
936 static void omap_pin_cfg_init(MemoryRegion *system_memory,
937 hwaddr base,
938 struct omap_mpu_state_s *mpu)
939 {
940 memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu,
941 "omap-pin-cfg", 0x800);
942 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
943 omap_pin_cfg_reset(mpu);
944 }
945
946 /* Device Identification, Die Identification */
947 static uint64_t omap_id_read(void *opaque, hwaddr addr,
948 unsigned size)
949 {
950 if (size != 4) {
951 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
952 " with bad width %d\n", __func__, addr, size);
953 return 0;
954 }
955
956 switch (addr) {
957 case 0xfffe1800: /* DIE_ID_LSB */
958 return 0xc9581f0e;
959 case 0xfffe1804: /* DIE_ID_MSB */
960 return 0xa8858bfa;
961
962 case 0xfffe2000: /* PRODUCT_ID_LSB */
963 return 0x00aaaafc;
964 case 0xfffe2004: /* PRODUCT_ID_MSB */
965 return 0xcafeb574;
966
967 case 0xfffed400: /* JTAG_ID_LSB */
968 return 0x03310315; /* omap310 */
969
970 case 0xfffed404: /* JTAG_ID_MSB */
971 return 0xfb57402f; /* omap310 */
972 break;
973 }
974
975 OMAP_BAD_REG(addr);
976 return 0;
977 }
978
979 static void omap_id_write(void *opaque, hwaddr addr,
980 uint64_t value, unsigned size)
981 {
982 if (size != 4) {
983 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
984 " with bad width %d\n", __func__, addr, size);
985 return;
986 }
987
988 OMAP_BAD_REG(addr);
989 }
990
991 static const MemoryRegionOps omap_id_ops = {
992 .read = omap_id_read,
993 .write = omap_id_write,
994 .endianness = DEVICE_NATIVE_ENDIAN,
995 };
996
997 static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
998 {
999 memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu,
1000 "omap-id", 0x100000000ULL);
1001 memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem,
1002 0xfffe1800, 0x800);
1003 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
1004 memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem,
1005 0xfffed400, 0x100);
1006 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1007 }
1008
1009 /* MPUI Control (Dummy) */
1010 static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
1011 unsigned size)
1012 {
1013 struct omap_mpu_state_s *s = opaque;
1014
1015 if (size != 4) {
1016 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1017 " with bad width %d\n", __func__, addr, size);
1018 return 0;
1019 }
1020
1021 switch (addr) {
1022 case 0x00: /* CTRL */
1023 return s->mpui_ctrl;
1024 case 0x04: /* DEBUG_ADDR */
1025 return 0x01ffffff;
1026 case 0x08: /* DEBUG_DATA */
1027 return 0xffffffff;
1028 case 0x0c: /* DEBUG_FLAG */
1029 return 0x00000800;
1030 case 0x10: /* STATUS */
1031 return 0x00000000;
1032
1033 /* Not in OMAP310 */
1034 case 0x14: /* DSP_STATUS */
1035 case 0x18: /* DSP_BOOT_CONFIG */
1036 return 0x00000000;
1037 case 0x1c: /* DSP_MPUI_CONFIG */
1038 return 0x0000ffff;
1039 }
1040
1041 OMAP_BAD_REG(addr);
1042 return 0;
1043 }
1044
1045 static void omap_mpui_write(void *opaque, hwaddr addr,
1046 uint64_t value, unsigned size)
1047 {
1048 struct omap_mpu_state_s *s = opaque;
1049
1050 if (size != 4) {
1051 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1052 " with bad width %d\n", __func__, addr, size);
1053 return;
1054 }
1055
1056 switch (addr) {
1057 case 0x00: /* CTRL */
1058 s->mpui_ctrl = value & 0x007fffff;
1059 break;
1060
1061 case 0x04: /* DEBUG_ADDR */
1062 case 0x08: /* DEBUG_DATA */
1063 case 0x0c: /* DEBUG_FLAG */
1064 case 0x10: /* STATUS */
1065 /* Not in OMAP310 */
1066 case 0x14: /* DSP_STATUS */
1067 OMAP_RO_REG(addr);
1068 break;
1069 case 0x18: /* DSP_BOOT_CONFIG */
1070 case 0x1c: /* DSP_MPUI_CONFIG */
1071 break;
1072
1073 default:
1074 OMAP_BAD_REG(addr);
1075 }
1076 }
1077
1078 static const MemoryRegionOps omap_mpui_ops = {
1079 .read = omap_mpui_read,
1080 .write = omap_mpui_write,
1081 .endianness = DEVICE_NATIVE_ENDIAN,
1082 };
1083
1084 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1085 {
1086 s->mpui_ctrl = 0x0003ff1b;
1087 }
1088
1089 static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
1090 struct omap_mpu_state_s *mpu)
1091 {
1092 memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu,
1093 "omap-mpui", 0x100);
1094 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
1095
1096 omap_mpui_reset(mpu);
1097 }
1098
1099 /* TIPB Bridges */
1100 struct omap_tipb_bridge_s {
1101 qemu_irq abort;
1102 MemoryRegion iomem;
1103
1104 int width_intr;
1105 uint16_t control;
1106 uint16_t alloc;
1107 uint16_t buffer;
1108 uint16_t enh_control;
1109 };
1110
1111 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
1112 unsigned size)
1113 {
1114 struct omap_tipb_bridge_s *s = opaque;
1115
1116 if (size < 2) {
1117 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1118 " with bad width %d\n", __func__, addr, size);
1119 return 0;
1120 }
1121
1122 switch (addr) {
1123 case 0x00: /* TIPB_CNTL */
1124 return s->control;
1125 case 0x04: /* TIPB_BUS_ALLOC */
1126 return s->alloc;
1127 case 0x08: /* MPU_TIPB_CNTL */
1128 return s->buffer;
1129 case 0x0c: /* ENHANCED_TIPB_CNTL */
1130 return s->enh_control;
1131 case 0x10: /* ADDRESS_DBG */
1132 case 0x14: /* DATA_DEBUG_LOW */
1133 case 0x18: /* DATA_DEBUG_HIGH */
1134 return 0xffff;
1135 case 0x1c: /* DEBUG_CNTR_SIG */
1136 return 0x00f8;
1137 }
1138
1139 OMAP_BAD_REG(addr);
1140 return 0;
1141 }
1142
1143 static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
1144 uint64_t value, unsigned size)
1145 {
1146 struct omap_tipb_bridge_s *s = opaque;
1147
1148 if (size < 2) {
1149 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1150 " with bad width %d\n", __func__, addr, size);
1151 return;
1152 }
1153
1154 switch (addr) {
1155 case 0x00: /* TIPB_CNTL */
1156 s->control = value & 0xffff;
1157 break;
1158
1159 case 0x04: /* TIPB_BUS_ALLOC */
1160 s->alloc = value & 0x003f;
1161 break;
1162
1163 case 0x08: /* MPU_TIPB_CNTL */
1164 s->buffer = value & 0x0003;
1165 break;
1166
1167 case 0x0c: /* ENHANCED_TIPB_CNTL */
1168 s->width_intr = !(value & 2);
1169 s->enh_control = value & 0x000f;
1170 break;
1171
1172 case 0x10: /* ADDRESS_DBG */
1173 case 0x14: /* DATA_DEBUG_LOW */
1174 case 0x18: /* DATA_DEBUG_HIGH */
1175 case 0x1c: /* DEBUG_CNTR_SIG */
1176 OMAP_RO_REG(addr);
1177 break;
1178
1179 default:
1180 OMAP_BAD_REG(addr);
1181 }
1182 }
1183
1184 static const MemoryRegionOps omap_tipb_bridge_ops = {
1185 .read = omap_tipb_bridge_read,
1186 .write = omap_tipb_bridge_write,
1187 .endianness = DEVICE_NATIVE_ENDIAN,
1188 };
1189
1190 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1191 {
1192 s->control = 0xffff;
1193 s->alloc = 0x0009;
1194 s->buffer = 0x0000;
1195 s->enh_control = 0x000f;
1196 }
1197
1198 static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1199 MemoryRegion *memory, hwaddr base,
1200 qemu_irq abort_irq, omap_clk clk)
1201 {
1202 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1);
1203
1204 s->abort = abort_irq;
1205 omap_tipb_bridge_reset(s);
1206
1207 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s,
1208 "omap-tipb-bridge", 0x100);
1209 memory_region_add_subregion(memory, base, &s->iomem);
1210
1211 return s;
1212 }
1213
1214 /* Dummy Traffic Controller's Memory Interface */
1215 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
1216 unsigned size)
1217 {
1218 struct omap_mpu_state_s *s = opaque;
1219 uint32_t ret;
1220
1221 if (size != 4) {
1222 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1223 " with bad width %d\n", __func__, addr, size);
1224 return 0;
1225 }
1226
1227 switch (addr) {
1228 case 0x00: /* IMIF_PRIO */
1229 case 0x04: /* EMIFS_PRIO */
1230 case 0x08: /* EMIFF_PRIO */
1231 case 0x0c: /* EMIFS_CONFIG */
1232 case 0x10: /* EMIFS_CS0_CONFIG */
1233 case 0x14: /* EMIFS_CS1_CONFIG */
1234 case 0x18: /* EMIFS_CS2_CONFIG */
1235 case 0x1c: /* EMIFS_CS3_CONFIG */
1236 case 0x24: /* EMIFF_MRS */
1237 case 0x28: /* TIMEOUT1 */
1238 case 0x2c: /* TIMEOUT2 */
1239 case 0x30: /* TIMEOUT3 */
1240 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1241 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1242 return s->tcmi_regs[addr >> 2];
1243
1244 case 0x20: /* EMIFF_SDRAM_CONFIG */
1245 ret = s->tcmi_regs[addr >> 2];
1246 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1247 /* XXX: We can try using the VGA_DIRTY flag for this */
1248 return ret;
1249 }
1250
1251 OMAP_BAD_REG(addr);
1252 return 0;
1253 }
1254
1255 static void omap_tcmi_write(void *opaque, hwaddr addr,
1256 uint64_t value, unsigned size)
1257 {
1258 struct omap_mpu_state_s *s = opaque;
1259
1260 if (size != 4) {
1261 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1262 " with bad width %d\n", __func__, addr, size);
1263 return;
1264 }
1265
1266 switch (addr) {
1267 case 0x00: /* IMIF_PRIO */
1268 case 0x04: /* EMIFS_PRIO */
1269 case 0x08: /* EMIFF_PRIO */
1270 case 0x10: /* EMIFS_CS0_CONFIG */
1271 case 0x14: /* EMIFS_CS1_CONFIG */
1272 case 0x18: /* EMIFS_CS2_CONFIG */
1273 case 0x1c: /* EMIFS_CS3_CONFIG */
1274 case 0x20: /* EMIFF_SDRAM_CONFIG */
1275 case 0x24: /* EMIFF_MRS */
1276 case 0x28: /* TIMEOUT1 */
1277 case 0x2c: /* TIMEOUT2 */
1278 case 0x30: /* TIMEOUT3 */
1279 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1280 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1281 s->tcmi_regs[addr >> 2] = value;
1282 break;
1283 case 0x0c: /* EMIFS_CONFIG */
1284 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
1285 break;
1286
1287 default:
1288 OMAP_BAD_REG(addr);
1289 }
1290 }
1291
1292 static const MemoryRegionOps omap_tcmi_ops = {
1293 .read = omap_tcmi_read,
1294 .write = omap_tcmi_write,
1295 .endianness = DEVICE_NATIVE_ENDIAN,
1296 };
1297
1298 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1299 {
1300 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1301 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1302 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1303 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1304 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1305 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1306 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1307 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1308 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1309 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1310 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1311 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1312 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1313 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1314 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1315 }
1316
1317 static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
1318 struct omap_mpu_state_s *mpu)
1319 {
1320 memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu,
1321 "omap-tcmi", 0x100);
1322 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
1323 omap_tcmi_reset(mpu);
1324 }
1325
1326 /* Digital phase-locked loops control */
1327 struct dpll_ctl_s {
1328 MemoryRegion iomem;
1329 uint16_t mode;
1330 omap_clk dpll;
1331 };
1332
1333 static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
1334 unsigned size)
1335 {
1336 struct dpll_ctl_s *s = opaque;
1337
1338 if (size != 2) {
1339 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1340 " with bad width %d\n", __func__, addr, size);
1341 return 0;
1342 }
1343
1344 if (addr == 0x00) /* CTL_REG */
1345 return s->mode;
1346
1347 OMAP_BAD_REG(addr);
1348 return 0;
1349 }
1350
1351 static void omap_dpll_write(void *opaque, hwaddr addr,
1352 uint64_t value, unsigned size)
1353 {
1354 struct dpll_ctl_s *s = opaque;
1355 uint16_t diff;
1356 static const int bypass_div[4] = { 1, 2, 4, 4 };
1357 int div, mult;
1358
1359 if (size != 2) {
1360 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1361 " with bad width %d\n", __func__, addr, size);
1362 return;
1363 }
1364
1365 if (addr == 0x00) { /* CTL_REG */
1366 /* See omap_ulpd_pm_write() too */
1367 diff = s->mode & value;
1368 s->mode = value & 0x2fff;
1369 if (diff & (0x3ff << 2)) {
1370 if (value & (1 << 4)) { /* PLL_ENABLE */
1371 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1372 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1373 } else {
1374 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1375 mult = 1;
1376 }
1377 omap_clk_setrate(s->dpll, div, mult);
1378 }
1379
1380 /* Enter the desired mode. */
1381 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1382
1383 /* Act as if the lock is restored. */
1384 s->mode |= 2;
1385 } else {
1386 OMAP_BAD_REG(addr);
1387 }
1388 }
1389
1390 static const MemoryRegionOps omap_dpll_ops = {
1391 .read = omap_dpll_read,
1392 .write = omap_dpll_write,
1393 .endianness = DEVICE_NATIVE_ENDIAN,
1394 };
1395
1396 static void omap_dpll_reset(struct dpll_ctl_s *s)
1397 {
1398 s->mode = 0x2002;
1399 omap_clk_setrate(s->dpll, 1, 1);
1400 }
1401
1402 static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
1403 hwaddr base, omap_clk clk)
1404 {
1405 struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
1406 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100);
1407
1408 s->dpll = clk;
1409 omap_dpll_reset(s);
1410
1411 memory_region_add_subregion(memory, base, &s->iomem);
1412 return s;
1413 }
1414
1415 /* MPU Clock/Reset/Power Mode Control */
1416 static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
1417 unsigned size)
1418 {
1419 struct omap_mpu_state_s *s = opaque;
1420
1421 if (size != 2) {
1422 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1423 " with bad width %d\n", __func__, addr, size);
1424 return 0;
1425 }
1426
1427 switch (addr) {
1428 case 0x00: /* ARM_CKCTL */
1429 return s->clkm.arm_ckctl;
1430
1431 case 0x04: /* ARM_IDLECT1 */
1432 return s->clkm.arm_idlect1;
1433
1434 case 0x08: /* ARM_IDLECT2 */
1435 return s->clkm.arm_idlect2;
1436
1437 case 0x0c: /* ARM_EWUPCT */
1438 return s->clkm.arm_ewupct;
1439
1440 case 0x10: /* ARM_RSTCT1 */
1441 return s->clkm.arm_rstct1;
1442
1443 case 0x14: /* ARM_RSTCT2 */
1444 return s->clkm.arm_rstct2;
1445
1446 case 0x18: /* ARM_SYSST */
1447 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
1448
1449 case 0x1c: /* ARM_CKOUT1 */
1450 return s->clkm.arm_ckout1;
1451
1452 case 0x20: /* ARM_CKOUT2 */
1453 break;
1454 }
1455
1456 OMAP_BAD_REG(addr);
1457 return 0;
1458 }
1459
1460 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1461 uint16_t diff, uint16_t value)
1462 {
1463 omap_clk clk;
1464
1465 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1466 if (value & (1 << 14))
1467 /* Reserved */;
1468 else {
1469 clk = omap_findclk(s, "arminth_ck");
1470 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1471 }
1472 }
1473 if (diff & (1 << 12)) { /* ARM_TIMXO */
1474 clk = omap_findclk(s, "armtim_ck");
1475 if (value & (1 << 12))
1476 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1477 else
1478 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1479 }
1480 /* XXX: en_dspck */
1481 if (diff & (3 << 10)) { /* DSPMMUDIV */
1482 clk = omap_findclk(s, "dspmmu_ck");
1483 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1484 }
1485 if (diff & (3 << 8)) { /* TCDIV */
1486 clk = omap_findclk(s, "tc_ck");
1487 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1488 }
1489 if (diff & (3 << 6)) { /* DSPDIV */
1490 clk = omap_findclk(s, "dsp_ck");
1491 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1492 }
1493 if (diff & (3 << 4)) { /* ARMDIV */
1494 clk = omap_findclk(s, "arm_ck");
1495 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1496 }
1497 if (diff & (3 << 2)) { /* LCDDIV */
1498 clk = omap_findclk(s, "lcd_ck");
1499 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1500 }
1501 if (diff & (3 << 0)) { /* PERDIV */
1502 clk = omap_findclk(s, "armper_ck");
1503 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1504 }
1505 }
1506
1507 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1508 uint16_t diff, uint16_t value)
1509 {
1510 omap_clk clk;
1511
1512 if (value & (1 << 11)) { /* SETARM_IDLE */
1513 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
1514 }
1515 if (!(value & (1 << 10))) { /* WKUP_MODE */
1516 /* XXX: disable wakeup from IRQ */
1517 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
1518 }
1519
1520 #define SET_CANIDLE(clock, bit) \
1521 if (diff & (1 << bit)) { \
1522 clk = omap_findclk(s, clock); \
1523 omap_clk_canidle(clk, (value >> bit) & 1); \
1524 }
1525 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1526 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1527 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1528 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1529 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1530 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1531 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1532 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1533 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1534 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1535 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1536 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1537 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1538 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1539 }
1540
1541 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1542 uint16_t diff, uint16_t value)
1543 {
1544 omap_clk clk;
1545
1546 #define SET_ONOFF(clock, bit) \
1547 if (diff & (1 << bit)) { \
1548 clk = omap_findclk(s, clock); \
1549 omap_clk_onoff(clk, (value >> bit) & 1); \
1550 }
1551 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1552 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1553 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1554 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1555 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1556 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1557 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1558 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1559 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1560 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1561 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1562 }
1563
1564 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1565 uint16_t diff, uint16_t value)
1566 {
1567 omap_clk clk;
1568
1569 if (diff & (3 << 4)) { /* TCLKOUT */
1570 clk = omap_findclk(s, "tclk_out");
1571 switch ((value >> 4) & 3) {
1572 case 1:
1573 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1574 omap_clk_onoff(clk, 1);
1575 break;
1576 case 2:
1577 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1578 omap_clk_onoff(clk, 1);
1579 break;
1580 default:
1581 omap_clk_onoff(clk, 0);
1582 }
1583 }
1584 if (diff & (3 << 2)) { /* DCLKOUT */
1585 clk = omap_findclk(s, "dclk_out");
1586 switch ((value >> 2) & 3) {
1587 case 0:
1588 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1589 break;
1590 case 1:
1591 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1592 break;
1593 case 2:
1594 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1595 break;
1596 case 3:
1597 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1598 break;
1599 }
1600 }
1601 if (diff & (3 << 0)) { /* ACLKOUT */
1602 clk = omap_findclk(s, "aclk_out");
1603 switch ((value >> 0) & 3) {
1604 case 1:
1605 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1606 omap_clk_onoff(clk, 1);
1607 break;
1608 case 2:
1609 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1610 omap_clk_onoff(clk, 1);
1611 break;
1612 case 3:
1613 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1614 omap_clk_onoff(clk, 1);
1615 break;
1616 default:
1617 omap_clk_onoff(clk, 0);
1618 }
1619 }
1620 }
1621
1622 static void omap_clkm_write(void *opaque, hwaddr addr,
1623 uint64_t value, unsigned size)
1624 {
1625 struct omap_mpu_state_s *s = opaque;
1626 uint16_t diff;
1627 omap_clk clk;
1628 static const char *clkschemename[8] = {
1629 "fully synchronous", "fully asynchronous", "synchronous scalable",
1630 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1631 };
1632
1633 if (size != 2) {
1634 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1635 " with bad width %d\n", __func__, addr, size);
1636 return;
1637 }
1638
1639 switch (addr) {
1640 case 0x00: /* ARM_CKCTL */
1641 diff = s->clkm.arm_ckctl ^ value;
1642 s->clkm.arm_ckctl = value & 0x7fff;
1643 omap_clkm_ckctl_update(s, diff, value);
1644 return;
1645
1646 case 0x04: /* ARM_IDLECT1 */
1647 diff = s->clkm.arm_idlect1 ^ value;
1648 s->clkm.arm_idlect1 = value & 0x0fff;
1649 omap_clkm_idlect1_update(s, diff, value);
1650 return;
1651
1652 case 0x08: /* ARM_IDLECT2 */
1653 diff = s->clkm.arm_idlect2 ^ value;
1654 s->clkm.arm_idlect2 = value & 0x07ff;
1655 omap_clkm_idlect2_update(s, diff, value);
1656 return;
1657
1658 case 0x0c: /* ARM_EWUPCT */
1659 s->clkm.arm_ewupct = value & 0x003f;
1660 return;
1661
1662 case 0x10: /* ARM_RSTCT1 */
1663 diff = s->clkm.arm_rstct1 ^ value;
1664 s->clkm.arm_rstct1 = value & 0x0007;
1665 if (value & 9) {
1666 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1667 s->clkm.cold_start = 0xa;
1668 }
1669 if (diff & ~value & 4) { /* DSP_RST */
1670 omap_mpui_reset(s);
1671 omap_tipb_bridge_reset(s->private_tipb);
1672 omap_tipb_bridge_reset(s->public_tipb);
1673 }
1674 if (diff & 2) { /* DSP_EN */
1675 clk = omap_findclk(s, "dsp_ck");
1676 omap_clk_canidle(clk, (~value >> 1) & 1);
1677 }
1678 return;
1679
1680 case 0x14: /* ARM_RSTCT2 */
1681 s->clkm.arm_rstct2 = value & 0x0001;
1682 return;
1683
1684 case 0x18: /* ARM_SYSST */
1685 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1686 s->clkm.clocking_scheme = (value >> 11) & 7;
1687 trace_omap1_pwl_clocking_scheme(
1688 clkschemename[s->clkm.clocking_scheme]);
1689 }
1690 s->clkm.cold_start &= value & 0x3f;
1691 return;
1692
1693 case 0x1c: /* ARM_CKOUT1 */
1694 diff = s->clkm.arm_ckout1 ^ value;
1695 s->clkm.arm_ckout1 = value & 0x003f;
1696 omap_clkm_ckout1_update(s, diff, value);
1697 return;
1698
1699 case 0x20: /* ARM_CKOUT2 */
1700 default:
1701 OMAP_BAD_REG(addr);
1702 }
1703 }
1704
1705 static const MemoryRegionOps omap_clkm_ops = {
1706 .read = omap_clkm_read,
1707 .write = omap_clkm_write,
1708 .endianness = DEVICE_NATIVE_ENDIAN,
1709 };
1710
1711 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
1712 unsigned size)
1713 {
1714 struct omap_mpu_state_s *s = opaque;
1715 CPUState *cpu = CPU(s->cpu);
1716
1717 if (size != 2) {
1718 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1719 " with bad width %d\n", __func__, addr, size);
1720 return 0;
1721 }
1722
1723 switch (addr) {
1724 case 0x04: /* DSP_IDLECT1 */
1725 return s->clkm.dsp_idlect1;
1726
1727 case 0x08: /* DSP_IDLECT2 */
1728 return s->clkm.dsp_idlect2;
1729
1730 case 0x14: /* DSP_RSTCT2 */
1731 return s->clkm.dsp_rstct2;
1732
1733 case 0x18: /* DSP_SYSST */
1734 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
1735 (cpu->halted << 6); /* Quite useless... */
1736 }
1737
1738 OMAP_BAD_REG(addr);
1739 return 0;
1740 }
1741
1742 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1743 uint16_t diff, uint16_t value)
1744 {
1745 omap_clk clk;
1746
1747 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1748 }
1749
1750 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1751 uint16_t diff, uint16_t value)
1752 {
1753 omap_clk clk;
1754
1755 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1756 }
1757
1758 static void omap_clkdsp_write(void *opaque, hwaddr addr,
1759 uint64_t value, unsigned size)
1760 {
1761 struct omap_mpu_state_s *s = opaque;
1762 uint16_t diff;
1763
1764 if (size != 2) {
1765 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1766 " with bad width %d\n", __func__, addr, size);
1767 return;
1768 }
1769
1770 switch (addr) {
1771 case 0x04: /* DSP_IDLECT1 */
1772 diff = s->clkm.dsp_idlect1 ^ value;
1773 s->clkm.dsp_idlect1 = value & 0x01f7;
1774 omap_clkdsp_idlect1_update(s, diff, value);
1775 break;
1776
1777 case 0x08: /* DSP_IDLECT2 */
1778 s->clkm.dsp_idlect2 = value & 0x0037;
1779 diff = s->clkm.dsp_idlect1 ^ value;
1780 omap_clkdsp_idlect2_update(s, diff, value);
1781 break;
1782
1783 case 0x14: /* DSP_RSTCT2 */
1784 s->clkm.dsp_rstct2 = value & 0x0001;
1785 break;
1786
1787 case 0x18: /* DSP_SYSST */
1788 s->clkm.cold_start &= value & 0x3f;
1789 break;
1790
1791 default:
1792 OMAP_BAD_REG(addr);
1793 }
1794 }
1795
1796 static const MemoryRegionOps omap_clkdsp_ops = {
1797 .read = omap_clkdsp_read,
1798 .write = omap_clkdsp_write,
1799 .endianness = DEVICE_NATIVE_ENDIAN,
1800 };
1801
1802 static void omap_clkm_reset(struct omap_mpu_state_s *s)
1803 {
1804 if (s->wdt && s->wdt->reset)
1805 s->clkm.cold_start = 0x6;
1806 s->clkm.clocking_scheme = 0;
1807 omap_clkm_ckctl_update(s, ~0, 0x3000);
1808 s->clkm.arm_ckctl = 0x3000;
1809 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
1810 s->clkm.arm_idlect1 = 0x0400;
1811 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
1812 s->clkm.arm_idlect2 = 0x0100;
1813 s->clkm.arm_ewupct = 0x003f;
1814 s->clkm.arm_rstct1 = 0x0000;
1815 s->clkm.arm_rstct2 = 0x0000;
1816 s->clkm.arm_ckout1 = 0x0015;
1817 s->clkm.dpll1_mode = 0x2002;
1818 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1819 s->clkm.dsp_idlect1 = 0x0040;
1820 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1821 s->clkm.dsp_idlect2 = 0x0000;
1822 s->clkm.dsp_rstct2 = 0x0000;
1823 }
1824
1825 static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
1826 hwaddr dsp_base, struct omap_mpu_state_s *s)
1827 {
1828 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s,
1829 "omap-clkm", 0x100);
1830 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s,
1831 "omap-clkdsp", 0x1000);
1832
1833 s->clkm.arm_idlect1 = 0x03ff;
1834 s->clkm.arm_idlect2 = 0x0100;
1835 s->clkm.dsp_idlect1 = 0x0002;
1836 omap_clkm_reset(s);
1837 s->clkm.cold_start = 0x3a;
1838
1839 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
1840 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
1841 }
1842
1843 /* MPU I/O */
1844 struct omap_mpuio_s {
1845 qemu_irq irq;
1846 qemu_irq kbd_irq;
1847 qemu_irq *in;
1848 qemu_irq handler[16];
1849 MemoryRegion iomem;
1850
1851 uint16_t inputs;
1852 uint16_t outputs;
1853 uint16_t dir;
1854 uint16_t edge;
1855 uint16_t mask;
1856 uint16_t ints;
1857
1858 uint16_t debounce;
1859 uint16_t latch;
1860 uint8_t event;
1861
1862 uint8_t buttons[5];
1863 uint8_t row_latch;
1864 uint8_t cols;
1865 int kbd_mask;
1866 int clk;
1867 };
1868
1869 static void omap_mpuio_set(void *opaque, int line, int level)
1870 {
1871 struct omap_mpuio_s *s = opaque;
1872 uint16_t prev = s->inputs;
1873
1874 if (level)
1875 s->inputs |= 1 << line;
1876 else
1877 s->inputs &= ~(1 << line);
1878
1879 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1880 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1881 s->ints |= 1 << line;
1882 qemu_irq_raise(s->irq);
1883 /* TODO: wakeup */
1884 }
1885 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1886 (s->event >> 1) == line) /* PIN_SELECT */
1887 s->latch = s->inputs;
1888 }
1889 }
1890
1891 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1892 {
1893 int i;
1894 uint8_t *row, rows = 0, cols = ~s->cols;
1895
1896 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
1897 if (*row & cols)
1898 rows |= i;
1899
1900 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1901 s->row_latch = ~rows;
1902 }
1903
1904 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
1905 unsigned size)
1906 {
1907 struct omap_mpuio_s *s = opaque;
1908 int offset = addr & OMAP_MPUI_REG_MASK;
1909 uint16_t ret;
1910
1911 if (size != 2) {
1912 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
1913 " with bad width %d\n", __func__, addr, size);
1914 return 0;
1915 }
1916
1917 switch (offset) {
1918 case 0x00: /* INPUT_LATCH */
1919 return s->inputs;
1920
1921 case 0x04: /* OUTPUT_REG */
1922 return s->outputs;
1923
1924 case 0x08: /* IO_CNTL */
1925 return s->dir;
1926
1927 case 0x10: /* KBR_LATCH */
1928 return s->row_latch;
1929
1930 case 0x14: /* KBC_REG */
1931 return s->cols;
1932
1933 case 0x18: /* GPIO_EVENT_MODE_REG */
1934 return s->event;
1935
1936 case 0x1c: /* GPIO_INT_EDGE_REG */
1937 return s->edge;
1938
1939 case 0x20: /* KBD_INT */
1940 return (~s->row_latch & 0x1f) && !s->kbd_mask;
1941
1942 case 0x24: /* GPIO_INT */
1943 ret = s->ints;
1944 s->ints &= s->mask;
1945 if (ret)
1946 qemu_irq_lower(s->irq);
1947 return ret;
1948
1949 case 0x28: /* KBD_MASKIT */
1950 return s->kbd_mask;
1951
1952 case 0x2c: /* GPIO_MASKIT */
1953 return s->mask;
1954
1955 case 0x30: /* GPIO_DEBOUNCING_REG */
1956 return s->debounce;
1957
1958 case 0x34: /* GPIO_LATCH_REG */
1959 return s->latch;
1960 }
1961
1962 OMAP_BAD_REG(addr);
1963 return 0;
1964 }
1965
1966 static void omap_mpuio_write(void *opaque, hwaddr addr,
1967 uint64_t value, unsigned size)
1968 {
1969 struct omap_mpuio_s *s = opaque;
1970 int offset = addr & OMAP_MPUI_REG_MASK;
1971 uint16_t diff;
1972 int ln;
1973
1974 if (size != 2) {
1975 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
1976 " with bad width %d\n", __func__, addr, size);
1977 return;
1978 }
1979
1980 switch (offset) {
1981 case 0x04: /* OUTPUT_REG */
1982 diff = (s->outputs ^ value) & ~s->dir;
1983 s->outputs = value;
1984 while ((ln = ctz32(diff)) != 32) {
1985 if (s->handler[ln])
1986 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1987 diff &= ~(1 << ln);
1988 }
1989 break;
1990
1991 case 0x08: /* IO_CNTL */
1992 diff = s->outputs & (s->dir ^ value);
1993 s->dir = value;
1994
1995 value = s->outputs & ~s->dir;
1996 while ((ln = ctz32(diff)) != 32) {
1997 if (s->handler[ln])
1998 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1999 diff &= ~(1 << ln);
2000 }
2001 break;
2002
2003 case 0x14: /* KBC_REG */
2004 s->cols = value;
2005 omap_mpuio_kbd_update(s);
2006 break;
2007
2008 case 0x18: /* GPIO_EVENT_MODE_REG */
2009 s->event = value & 0x1f;
2010 break;
2011
2012 case 0x1c: /* GPIO_INT_EDGE_REG */
2013 s->edge = value;
2014 break;
2015
2016 case 0x28: /* KBD_MASKIT */
2017 s->kbd_mask = value & 1;
2018 omap_mpuio_kbd_update(s);
2019 break;
2020
2021 case 0x2c: /* GPIO_MASKIT */
2022 s->mask = value;
2023 break;
2024
2025 case 0x30: /* GPIO_DEBOUNCING_REG */
2026 s->debounce = value & 0x1ff;
2027 break;
2028
2029 case 0x00: /* INPUT_LATCH */
2030 case 0x10: /* KBR_LATCH */
2031 case 0x20: /* KBD_INT */
2032 case 0x24: /* GPIO_INT */
2033 case 0x34: /* GPIO_LATCH_REG */
2034 OMAP_RO_REG(addr);
2035 return;
2036
2037 default:
2038 OMAP_BAD_REG(addr);
2039 return;
2040 }
2041 }
2042
2043 static const MemoryRegionOps omap_mpuio_ops = {
2044 .read = omap_mpuio_read,
2045 .write = omap_mpuio_write,
2046 .endianness = DEVICE_NATIVE_ENDIAN,
2047 };
2048
2049 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2050 {
2051 s->inputs = 0;
2052 s->outputs = 0;
2053 s->dir = ~0;
2054 s->event = 0;
2055 s->edge = 0;
2056 s->kbd_mask = 0;
2057 s->mask = 0;
2058 s->debounce = 0;
2059 s->latch = 0;
2060 s->ints = 0;
2061 s->row_latch = 0x1f;
2062 s->clk = 1;
2063 }
2064
2065 static void omap_mpuio_onoff(void *opaque, int line, int on)
2066 {
2067 struct omap_mpuio_s *s = opaque;
2068
2069 s->clk = on;
2070 if (on)
2071 omap_mpuio_kbd_update(s);
2072 }
2073
2074 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
2075 hwaddr base,
2076 qemu_irq kbd_int, qemu_irq gpio_int,
2077 omap_clk clk)
2078 {
2079 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1);
2080
2081 s->irq = gpio_int;
2082 s->kbd_irq = kbd_int;
2083 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2084 omap_mpuio_reset(s);
2085
2086 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s,
2087 "omap-mpuio", 0x800);
2088 memory_region_add_subregion(memory, base, &s->iomem);
2089
2090 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0));
2091
2092 return s;
2093 }
2094
2095 /* MicroWire Interface */
2096 struct omap_uwire_s {
2097 MemoryRegion iomem;
2098 qemu_irq txirq;
2099 qemu_irq rxirq;
2100 qemu_irq txdrq;
2101
2102 uint16_t txbuf;
2103 uint16_t rxbuf;
2104 uint16_t control;
2105 uint16_t setup[5];
2106 };
2107
2108 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2109 {
2110 int chipselect = (s->control >> 10) & 3; /* INDEX */
2111
2112 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2113 if (s->control & (1 << 12)) { /* CS_CMD */
2114 qemu_log_mask(LOG_UNIMP, "uWireSlave TX CS:%d data:0x%04x\n",
2115 chipselect,
2116 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2117 }
2118 s->control &= ~(1 << 14); /* CSRB */
2119 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2120 * a DRQ. When is the level IRQ supposed to be reset? */
2121 }
2122
2123 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2124 if (s->control & (1 << 12)) { /* CS_CMD */
2125 qemu_log_mask(LOG_UNIMP, "uWireSlave RX CS:%d\n", chipselect);
2126 }
2127 s->control |= 1 << 15; /* RDRB */
2128 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2129 * a DRQ. When is the level IRQ supposed to be reset? */
2130 }
2131 }
2132
2133 static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
2134 {
2135 struct omap_uwire_s *s = opaque;
2136 int offset = addr & OMAP_MPUI_REG_MASK;
2137
2138 if (size != 2) {
2139 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
2140 " with bad width %d\n", __func__, addr, size);
2141 return 0;
2142 }
2143
2144 switch (offset) {
2145 case 0x00: /* RDR */
2146 s->control &= ~(1 << 15); /* RDRB */
2147 return s->rxbuf;
2148
2149 case 0x04: /* CSR */
2150 return s->control;
2151
2152 case 0x08: /* SR1 */
2153 return s->setup[0];
2154 case 0x0c: /* SR2 */
2155 return s->setup[1];
2156 case 0x10: /* SR3 */
2157 return s->setup[2];
2158 case 0x14: /* SR4 */
2159 return s->setup[3];
2160 case 0x18: /* SR5 */
2161 return s->setup[4];
2162 }
2163
2164 OMAP_BAD_REG(addr);
2165 return 0;
2166 }
2167
2168 static void omap_uwire_write(void *opaque, hwaddr addr,
2169 uint64_t value, unsigned size)
2170 {
2171 struct omap_uwire_s *s = opaque;
2172 int offset = addr & OMAP_MPUI_REG_MASK;
2173
2174 if (size != 2) {
2175 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
2176 " with bad width %d\n", __func__, addr, size);
2177 return;
2178 }
2179
2180 switch (offset) {
2181 case 0x00: /* TDR */
2182 s->txbuf = value; /* TD */
2183 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2184 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2185 (s->control & (1 << 12)))) { /* CS_CMD */
2186 s->control |= 1 << 14; /* CSRB */
2187 omap_uwire_transfer_start(s);
2188 }
2189 break;
2190
2191 case 0x04: /* CSR */
2192 s->control = value & 0x1fff;
2193 if (value & (1 << 13)) /* START */
2194 omap_uwire_transfer_start(s);
2195 break;
2196
2197 case 0x08: /* SR1 */
2198 s->setup[0] = value & 0x003f;
2199 break;
2200
2201 case 0x0c: /* SR2 */
2202 s->setup[1] = value & 0x0fc0;
2203 break;
2204
2205 case 0x10: /* SR3 */
2206 s->setup[2] = value & 0x0003;
2207 break;
2208
2209 case 0x14: /* SR4 */
2210 s->setup[3] = value & 0x0001;
2211 break;
2212
2213 case 0x18: /* SR5 */
2214 s->setup[4] = value & 0x000f;
2215 break;
2216
2217 default:
2218 OMAP_BAD_REG(addr);
2219 return;
2220 }
2221 }
2222
2223 static const MemoryRegionOps omap_uwire_ops = {
2224 .read = omap_uwire_read,
2225 .write = omap_uwire_write,
2226 .endianness = DEVICE_NATIVE_ENDIAN,
2227 };
2228
2229 static void omap_uwire_reset(struct omap_uwire_s *s)
2230 {
2231 s->control = 0;
2232 s->setup[0] = 0;
2233 s->setup[1] = 0;
2234 s->setup[2] = 0;
2235 s->setup[3] = 0;
2236 s->setup[4] = 0;
2237 }
2238
2239 static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
2240 hwaddr base,
2241 qemu_irq txirq, qemu_irq rxirq,
2242 qemu_irq dma,
2243 omap_clk clk)
2244 {
2245 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1);
2246
2247 s->txirq = txirq;
2248 s->rxirq = rxirq;
2249 s->txdrq = dma;
2250 omap_uwire_reset(s);
2251
2252 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800);
2253 memory_region_add_subregion(system_memory, base, &s->iomem);
2254
2255 return s;
2256 }
2257
2258 /* Pseudonoise Pulse-Width Light Modulator */
2259 struct omap_pwl_s {
2260 MemoryRegion iomem;
2261 uint8_t output;
2262 uint8_t level;
2263 uint8_t enable;
2264 int clk;
2265 };
2266
2267 static void omap_pwl_update(struct omap_pwl_s *s)
2268 {
2269 int output = (s->clk && s->enable) ? s->level : 0;
2270
2271 if (output != s->output) {
2272 s->output = output;
2273 trace_omap1_pwl_backlight(output);
2274 }
2275 }
2276
2277 static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
2278 {
2279 struct omap_pwl_s *s = opaque;
2280 int offset = addr & OMAP_MPUI_REG_MASK;
2281
2282 if (size != 1) {
2283 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
2284 " with bad width %d\n", __func__, addr, size);
2285 return 0;
2286 }
2287
2288 switch (offset) {
2289 case 0x00: /* PWL_LEVEL */
2290 return s->level;
2291 case 0x04: /* PWL_CTRL */
2292 return s->enable;
2293 }
2294 OMAP_BAD_REG(addr);
2295 return 0;
2296 }
2297
2298 static void omap_pwl_write(void *opaque, hwaddr addr,
2299 uint64_t value, unsigned size)
2300 {
2301 struct omap_pwl_s *s = opaque;
2302 int offset = addr & OMAP_MPUI_REG_MASK;
2303
2304 if (size != 1) {
2305 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
2306 " with bad width %d\n", __func__, addr, size);
2307 return;
2308 }
2309
2310 switch (offset) {
2311 case 0x00: /* PWL_LEVEL */
2312 s->level = value;
2313 omap_pwl_update(s);
2314 break;
2315 case 0x04: /* PWL_CTRL */
2316 s->enable = value & 1;
2317 omap_pwl_update(s);
2318 break;
2319 default:
2320 OMAP_BAD_REG(addr);
2321 return;
2322 }
2323 }
2324
2325 static const MemoryRegionOps omap_pwl_ops = {
2326 .read = omap_pwl_read,
2327 .write = omap_pwl_write,
2328 .endianness = DEVICE_NATIVE_ENDIAN,
2329 };
2330
2331 static void omap_pwl_reset(struct omap_pwl_s *s)
2332 {
2333 s->output = 0;
2334 s->level = 0;
2335 s->enable = 0;
2336 s->clk = 1;
2337 omap_pwl_update(s);
2338 }
2339
2340 static void omap_pwl_clk_update(void *opaque, int line, int on)
2341 {
2342 struct omap_pwl_s *s = opaque;
2343
2344 s->clk = on;
2345 omap_pwl_update(s);
2346 }
2347
2348 static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
2349 hwaddr base,
2350 omap_clk clk)
2351 {
2352 struct omap_pwl_s *s = g_malloc0(sizeof(*s));
2353
2354 omap_pwl_reset(s);
2355
2356 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s,
2357 "omap-pwl", 0x800);
2358 memory_region_add_subregion(system_memory, base, &s->iomem);
2359
2360 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0));
2361 return s;
2362 }
2363
2364 /* Pulse-Width Tone module */
2365 struct omap_pwt_s {
2366 MemoryRegion iomem;
2367 uint8_t frc;
2368 uint8_t vrc;
2369 uint8_t gcr;
2370 omap_clk clk;
2371 };
2372
2373 static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
2374 {
2375 struct omap_pwt_s *s = opaque;
2376 int offset = addr & OMAP_MPUI_REG_MASK;
2377
2378 if (size != 1) {
2379 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
2380 " with bad width %d\n", __func__, addr, size);
2381 return 0;
2382 }
2383
2384 switch (offset) {
2385 case 0x00: /* FRC */
2386 return s->frc;
2387 case 0x04: /* VCR */
2388 return s->vrc;
2389 case 0x08: /* GCR */
2390 return s->gcr;
2391 }
2392 OMAP_BAD_REG(addr);
2393 return 0;
2394 }
2395
2396 static void omap_pwt_write(void *opaque, hwaddr addr,
2397 uint64_t value, unsigned size)
2398 {
2399 struct omap_pwt_s *s = opaque;
2400 int offset = addr & OMAP_MPUI_REG_MASK;
2401
2402 if (size != 1) {
2403 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
2404 " with bad width %d\n", __func__, addr, size);
2405 return;
2406 }
2407
2408 switch (offset) {
2409 case 0x00: /* FRC */
2410 s->frc = value & 0x3f;
2411 break;
2412 case 0x04: /* VRC */
2413 if ((value ^ s->vrc) & 1) {
2414 if (value & 1) {
2415 trace_omap1_pwt_buzz(
2416 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2417 ((omap_clk_getrate(s->clk) >> 3) /
2418 /* Pre-multiplexer divider */
2419 ((s->gcr & 2) ? 1 : 154) /
2420 /* Octave multiplexer */
2421 (2 << (value & 3)) *
2422 /* 101/107 divider */
2423 ((value & (1 << 2)) ? 101 : 107) *
2424 /* 49/55 divider */
2425 ((value & (1 << 3)) ? 49 : 55) *
2426 /* 50/63 divider */
2427 ((value & (1 << 4)) ? 50 : 63) *
2428 /* 80/127 divider */
2429 ((value & (1 << 5)) ? 80 : 127) /
2430 (107 * 55 * 63 * 127)));
2431 } else {
2432 trace_omap1_pwt_silence();
2433 }
2434 }
2435 s->vrc = value & 0x7f;
2436 break;
2437 case 0x08: /* GCR */
2438 s->gcr = value & 3;
2439 break;
2440 default:
2441 OMAP_BAD_REG(addr);
2442 return;
2443 }
2444 }
2445
2446 static const MemoryRegionOps omap_pwt_ops = {
2447 .read =omap_pwt_read,
2448 .write = omap_pwt_write,
2449 .endianness = DEVICE_NATIVE_ENDIAN,
2450 };
2451
2452 static void omap_pwt_reset(struct omap_pwt_s *s)
2453 {
2454 s->frc = 0;
2455 s->vrc = 0;
2456 s->gcr = 0;
2457 }
2458
2459 static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
2460 hwaddr base,
2461 omap_clk clk)
2462 {
2463 struct omap_pwt_s *s = g_malloc0(sizeof(*s));
2464 s->clk = clk;
2465 omap_pwt_reset(s);
2466
2467 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s,
2468 "omap-pwt", 0x800);
2469 memory_region_add_subregion(system_memory, base, &s->iomem);
2470 return s;
2471 }
2472
2473 /* Real-time Clock module */
2474 struct omap_rtc_s {
2475 MemoryRegion iomem;
2476 qemu_irq irq;
2477 qemu_irq alarm;
2478 QEMUTimer *clk;
2479
2480 uint8_t interrupts;
2481 uint8_t status;
2482 int16_t comp_reg;
2483 int running;
2484 int pm_am;
2485 int auto_comp;
2486 int round;
2487 struct tm alarm_tm;
2488 time_t alarm_ti;
2489
2490 struct tm current_tm;
2491 time_t ti;
2492 uint64_t tick;
2493 };
2494
2495 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2496 {
2497 /* s->alarm is level-triggered */
2498 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2499 }
2500
2501 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2502 {
2503 s->alarm_ti = mktimegm(&s->alarm_tm);
2504 if (s->alarm_ti == -1) {
2505 qemu_log_mask(LOG_GUEST_ERROR, "%s: conversion failed\n", __func__);
2506 }
2507 }
2508
2509 static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
2510 {
2511 struct omap_rtc_s *s = opaque;
2512 int offset = addr & OMAP_MPUI_REG_MASK;
2513 uint8_t i;
2514
2515 if (size != 1) {
2516 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
2517 " with bad width %d\n", __func__, addr, size);
2518 return 0;
2519 }
2520
2521 switch (offset) {
2522 case 0x00: /* SECONDS_REG */
2523 return to_bcd(s->current_tm.tm_sec);
2524
2525 case 0x04: /* MINUTES_REG */
2526 return to_bcd(s->current_tm.tm_min);
2527
2528 case 0x08: /* HOURS_REG */
2529 if (s->pm_am)
2530 return ((s->current_tm.tm_hour > 11) << 7) |
2531 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
2532 else
2533 return to_bcd(s->current_tm.tm_hour);
2534
2535 case 0x0c: /* DAYS_REG */
2536 return to_bcd(s->current_tm.tm_mday);
2537
2538 case 0x10: /* MONTHS_REG */
2539 return to_bcd(s->current_tm.tm_mon + 1);
2540
2541 case 0x14: /* YEARS_REG */
2542 return to_bcd(s->current_tm.tm_year % 100);
2543
2544 case 0x18: /* WEEK_REG */
2545 return s->current_tm.tm_wday;
2546
2547 case 0x20: /* ALARM_SECONDS_REG */
2548 return to_bcd(s->alarm_tm.tm_sec);
2549
2550 case 0x24: /* ALARM_MINUTES_REG */
2551 return to_bcd(s->alarm_tm.tm_min);
2552
2553 case 0x28: /* ALARM_HOURS_REG */
2554 if (s->pm_am)
2555 return ((s->alarm_tm.tm_hour > 11) << 7) |
2556 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
2557 else
2558 return to_bcd(s->alarm_tm.tm_hour);
2559
2560 case 0x2c: /* ALARM_DAYS_REG */
2561 return to_bcd(s->alarm_tm.tm_mday);
2562
2563 case 0x30: /* ALARM_MONTHS_REG */
2564 return to_bcd(s->alarm_tm.tm_mon + 1);
2565
2566 case 0x34: /* ALARM_YEARS_REG */
2567 return to_bcd(s->alarm_tm.tm_year % 100);
2568
2569 case 0x40: /* RTC_CTRL_REG */
2570 return (s->pm_am << 3) | (s->auto_comp << 2) |
2571 (s->round << 1) | s->running;
2572
2573 case 0x44: /* RTC_STATUS_REG */
2574 i = s->status;
2575 s->status &= ~0x3d;
2576 return i;
2577
2578 case 0x48: /* RTC_INTERRUPTS_REG */
2579 return s->interrupts;
2580
2581 case 0x4c: /* RTC_COMP_LSB_REG */
2582 return ((uint16_t) s->comp_reg) & 0xff;
2583
2584 case 0x50: /* RTC_COMP_MSB_REG */
2585 return ((uint16_t) s->comp_reg) >> 8;
2586 }
2587
2588 OMAP_BAD_REG(addr);
2589 return 0;
2590 }
2591
2592 static void omap_rtc_write(void *opaque, hwaddr addr,
2593 uint64_t value, unsigned size)
2594 {
2595 struct omap_rtc_s *s = opaque;
2596 int offset = addr & OMAP_MPUI_REG_MASK;
2597 struct tm new_tm;
2598 time_t ti[2];
2599
2600 if (size != 1) {
2601 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
2602 " with bad width %d\n", __func__, addr, size);
2603 return;
2604 }
2605
2606 switch (offset) {
2607 case 0x00: /* SECONDS_REG */
2608 s->ti -= s->current_tm.tm_sec;
2609 s->ti += from_bcd(value);
2610 return;
2611
2612 case 0x04: /* MINUTES_REG */
2613 s->ti -= s->current_tm.tm_min * 60;
2614 s->ti += from_bcd(value) * 60;
2615 return;
2616
2617 case 0x08: /* HOURS_REG */
2618 s->ti -= s->current_tm.tm_hour * 3600;
2619 if (s->pm_am) {
2620 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
2621 s->ti += ((value >> 7) & 1) * 43200;
2622 } else
2623 s->ti += from_bcd(value & 0x3f) * 3600;
2624 return;
2625
2626 case 0x0c: /* DAYS_REG */
2627 s->ti -= s->current_tm.tm_mday * 86400;
2628 s->ti += from_bcd(value) * 86400;
2629 return;
2630
2631 case 0x10: /* MONTHS_REG */
2632 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2633 new_tm.tm_mon = from_bcd(value);
2634 ti[0] = mktimegm(&s->current_tm);
2635 ti[1] = mktimegm(&new_tm);
2636
2637 if (ti[0] != -1 && ti[1] != -1) {
2638 s->ti -= ti[0];
2639 s->ti += ti[1];
2640 } else {
2641 /* A less accurate version */
2642 s->ti -= s->current_tm.tm_mon * 2592000;
2643 s->ti += from_bcd(value) * 2592000;
2644 }
2645 return;
2646
2647 case 0x14: /* YEARS_REG */
2648 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2649 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
2650 ti[0] = mktimegm(&s->current_tm);
2651 ti[1] = mktimegm(&new_tm);
2652
2653 if (ti[0] != -1 && ti[1] != -1) {
2654 s->ti -= ti[0];
2655 s->ti += ti[1];
2656 } else {
2657 /* A less accurate version */
2658 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000;
2659 s->ti += (time_t)from_bcd(value) * 31536000;
2660 }
2661 return;
2662
2663 case 0x18: /* WEEK_REG */
2664 return; /* Ignored */
2665
2666 case 0x20: /* ALARM_SECONDS_REG */
2667 s->alarm_tm.tm_sec = from_bcd(value);
2668 omap_rtc_alarm_update(s);
2669 return;
2670
2671 case 0x24: /* ALARM_MINUTES_REG */
2672 s->alarm_tm.tm_min = from_bcd(value);
2673 omap_rtc_alarm_update(s);
2674 return;
2675
2676 case 0x28: /* ALARM_HOURS_REG */
2677 if (s->pm_am)
2678 s->alarm_tm.tm_hour =
2679 ((from_bcd(value & 0x3f)) % 12) +
2680 ((value >> 7) & 1) * 12;
2681 else
2682 s->alarm_tm.tm_hour = from_bcd(value);
2683 omap_rtc_alarm_update(s);
2684 return;
2685
2686 case 0x2c: /* ALARM_DAYS_REG */
2687 s->alarm_tm.tm_mday = from_bcd(value);
2688 omap_rtc_alarm_update(s);
2689 return;
2690
2691 case 0x30: /* ALARM_MONTHS_REG */
2692 s->alarm_tm.tm_mon = from_bcd(value);
2693 omap_rtc_alarm_update(s);
2694 return;
2695
2696 case 0x34: /* ALARM_YEARS_REG */
2697 s->alarm_tm.tm_year = from_bcd(value);
2698 omap_rtc_alarm_update(s);
2699 return;
2700
2701 case 0x40: /* RTC_CTRL_REG */
2702 s->pm_am = (value >> 3) & 1;
2703 s->auto_comp = (value >> 2) & 1;
2704 s->round = (value >> 1) & 1;
2705 s->running = value & 1;
2706 s->status &= 0xfd;
2707 s->status |= s->running << 1;
2708 return;
2709
2710 case 0x44: /* RTC_STATUS_REG */
2711 s->status &= ~((value & 0xc0) ^ 0x80);
2712 omap_rtc_interrupts_update(s);
2713 return;
2714
2715 case 0x48: /* RTC_INTERRUPTS_REG */
2716 s->interrupts = value;
2717 return;
2718
2719 case 0x4c: /* RTC_COMP_LSB_REG */
2720 s->comp_reg &= 0xff00;
2721 s->comp_reg |= 0x00ff & value;
2722 return;
2723
2724 case 0x50: /* RTC_COMP_MSB_REG */
2725 s->comp_reg &= 0x00ff;
2726 s->comp_reg |= 0xff00 & (value << 8);
2727 return;
2728
2729 default:
2730 OMAP_BAD_REG(addr);
2731 return;
2732 }
2733 }
2734
2735 static const MemoryRegionOps omap_rtc_ops = {
2736 .read = omap_rtc_read,
2737 .write = omap_rtc_write,
2738 .endianness = DEVICE_NATIVE_ENDIAN,
2739 };
2740
2741 static void omap_rtc_tick(void *opaque)
2742 {
2743 struct omap_rtc_s *s = opaque;
2744
2745 if (s->round) {
2746 /* Round to nearest full minute. */
2747 if (s->current_tm.tm_sec < 30)
2748 s->ti -= s->current_tm.tm_sec;
2749 else
2750 s->ti += 60 - s->current_tm.tm_sec;
2751
2752 s->round = 0;
2753 }
2754
2755 localtime_r(&s->ti, &s->current_tm);
2756
2757 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2758 s->status |= 0x40;
2759 omap_rtc_interrupts_update(s);
2760 }
2761
2762 if (s->interrupts & 0x04)
2763 switch (s->interrupts & 3) {
2764 case 0:
2765 s->status |= 0x04;
2766 qemu_irq_pulse(s->irq);
2767 break;
2768 case 1:
2769 if (s->current_tm.tm_sec)
2770 break;
2771 s->status |= 0x08;
2772 qemu_irq_pulse(s->irq);
2773 break;
2774 case 2:
2775 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2776 break;
2777 s->status |= 0x10;
2778 qemu_irq_pulse(s->irq);
2779 break;
2780 case 3:
2781 if (s->current_tm.tm_sec ||
2782 s->current_tm.tm_min || s->current_tm.tm_hour)
2783 break;
2784 s->status |= 0x20;
2785 qemu_irq_pulse(s->irq);
2786 break;
2787 }
2788
2789 /* Move on */
2790 if (s->running)
2791 s->ti ++;
2792 s->tick += 1000;
2793
2794 /*
2795 * Every full hour add a rough approximation of the compensation
2796 * register to the 32kHz Timer (which drives the RTC) value.
2797 */
2798 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2799 s->tick += s->comp_reg * 1000 / 32768;
2800
2801 timer_mod(s->clk, s->tick);
2802 }
2803
2804 static void omap_rtc_reset(struct omap_rtc_s *s)
2805 {
2806 struct tm tm;
2807
2808 s->interrupts = 0;
2809 s->comp_reg = 0;
2810 s->running = 0;
2811 s->pm_am = 0;
2812 s->auto_comp = 0;
2813 s->round = 0;
2814 s->tick = qemu_clock_get_ms(rtc_clock);
2815 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2816 s->alarm_tm.tm_mday = 0x01;
2817 s->status = 1 << 7;
2818 qemu_get_timedate(&tm, 0);
2819 s->ti = mktimegm(&tm);
2820
2821 omap_rtc_alarm_update(s);
2822 omap_rtc_tick(s);
2823 }
2824
2825 static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
2826 hwaddr base,
2827 qemu_irq timerirq, qemu_irq alarmirq,
2828 omap_clk clk)
2829 {
2830 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1);
2831
2832 s->irq = timerirq;
2833 s->alarm = alarmirq;
2834 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s);
2835
2836 omap_rtc_reset(s);
2837
2838 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s,
2839 "omap-rtc", 0x800);
2840 memory_region_add_subregion(system_memory, base, &s->iomem);
2841
2842 return s;
2843 }
2844
2845 /* Multi-channel Buffered Serial Port interfaces */
2846 struct omap_mcbsp_s {
2847 MemoryRegion iomem;
2848 qemu_irq txirq;
2849 qemu_irq rxirq;
2850 qemu_irq txdrq;
2851 qemu_irq rxdrq;
2852
2853 uint16_t spcr[2];
2854 uint16_t rcr[2];
2855 uint16_t xcr[2];
2856 uint16_t srgr[2];
2857 uint16_t mcr[2];
2858 uint16_t pcr;
2859 uint16_t rcer[8];
2860 uint16_t xcer[8];
2861 int tx_rate;
2862 int rx_rate;
2863 int tx_req;
2864 int rx_req;
2865
2866 I2SCodec *codec;
2867 QEMUTimer *source_timer;
2868 QEMUTimer *sink_timer;
2869 };
2870
2871 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2872 {
2873 int irq;
2874
2875 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2876 case 0:
2877 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2878 break;
2879 case 3:
2880 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2881 break;
2882 default:
2883 irq = 0;
2884 break;
2885 }
2886
2887 if (irq)
2888 qemu_irq_pulse(s->rxirq);
2889
2890 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
2891 case 0:
2892 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
2893 break;
2894 case 3:
2895 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
2896 break;
2897 default:
2898 irq = 0;
2899 break;
2900 }
2901
2902 if (irq)
2903 qemu_irq_pulse(s->txirq);
2904 }
2905
2906 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
2907 {
2908 if ((s->spcr[0] >> 1) & 1) /* RRDY */
2909 s->spcr[0] |= 1 << 2; /* RFULL */
2910 s->spcr[0] |= 1 << 1; /* RRDY */
2911 qemu_irq_raise(s->rxdrq);
2912 omap_mcbsp_intr_update(s);
2913 }
2914
2915 static void omap_mcbsp_source_tick(void *opaque)
2916 {
2917 struct omap_mcbsp_s *s = opaque;
2918 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2919
2920 if (!s->rx_rate)
2921 return;
2922 if (s->rx_req) {
2923 qemu_log_mask(LOG_GUEST_ERROR, "%s: Rx FIFO overrun\n", __func__);
2924 }
2925
2926 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
2927
2928 omap_mcbsp_rx_newdata(s);
2929 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2930 NANOSECONDS_PER_SECOND);
2931 }
2932
2933 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
2934 {
2935 if (!s->codec || !s->codec->rts)
2936 omap_mcbsp_source_tick(s);
2937 else if (s->codec->in.len) {
2938 s->rx_req = s->codec->in.len;
2939 omap_mcbsp_rx_newdata(s);
2940 }
2941 }
2942
2943 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
2944 {
2945 timer_del(s->source_timer);
2946 }
2947
2948 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
2949 {
2950 s->spcr[0] &= ~(1 << 1); /* RRDY */
2951 qemu_irq_lower(s->rxdrq);
2952 omap_mcbsp_intr_update(s);
2953 }
2954
2955 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
2956 {
2957 s->spcr[1] |= 1 << 1; /* XRDY */
2958 qemu_irq_raise(s->txdrq);
2959 omap_mcbsp_intr_update(s);
2960 }
2961
2962 static void omap_mcbsp_sink_tick(void *opaque)
2963 {
2964 struct omap_mcbsp_s *s = opaque;
2965 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2966
2967 if (!s->tx_rate)
2968 return;
2969 if (s->tx_req) {
2970 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO underrun\n", __func__);
2971 }
2972
2973 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
2974
2975 omap_mcbsp_tx_newdata(s);
2976 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2977 NANOSECONDS_PER_SECOND);
2978 }
2979
2980 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
2981 {
2982 if (!s->codec || !s->codec->cts)
2983 omap_mcbsp_sink_tick(s);
2984 else if (s->codec->out.size) {
2985 s->tx_req = s->codec->out.size;
2986 omap_mcbsp_tx_newdata(s);
2987 }
2988 }
2989
2990 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
2991 {
2992 s->spcr[1] &= ~(1 << 1); /* XRDY */
2993 qemu_irq_lower(s->txdrq);
2994 omap_mcbsp_intr_update(s);
2995 if (s->codec && s->codec->cts)
2996 s->codec->tx_swallow(s->codec->opaque);
2997 }
2998
2999 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3000 {
3001 s->tx_req = 0;
3002 omap_mcbsp_tx_done(s);
3003 timer_del(s->sink_timer);
3004 }
3005
3006 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3007 {
3008 int prev_rx_rate, prev_tx_rate;
3009 int rx_rate = 0, tx_rate = 0;
3010 int cpu_rate = 1500000; /* XXX */
3011
3012 /* TODO: check CLKSTP bit */
3013 if (s->spcr[1] & (1 << 6)) { /* GRST */
3014 if (s->spcr[0] & (1 << 0)) { /* RRST */
3015 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3016 (s->pcr & (1 << 8))) { /* CLKRM */
3017 if (~s->pcr & (1 << 7)) /* SCLKME */
3018 rx_rate = cpu_rate /
3019 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3020 } else
3021 if (s->codec)
3022 rx_rate = s->codec->rx_rate;
3023 }
3024
3025 if (s->spcr[1] & (1 << 0)) { /* XRST */
3026 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3027 (s->pcr & (1 << 9))) { /* CLKXM */
3028 if (~s->pcr & (1 << 7)) /* SCLKME */
3029 tx_rate = cpu_rate /
3030 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3031 } else
3032 if (s->codec)
3033 tx_rate = s->codec->tx_rate;
3034 }
3035 }
3036 prev_tx_rate = s->tx_rate;
3037 prev_rx_rate = s->rx_rate;
3038 s->tx_rate = tx_rate;
3039 s->rx_rate = rx_rate;
3040
3041 if (s->codec)
3042 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3043
3044 if (!prev_tx_rate && tx_rate)
3045 omap_mcbsp_tx_start(s);
3046 else if (s->tx_rate && !tx_rate)
3047 omap_mcbsp_tx_stop(s);
3048
3049 if (!prev_rx_rate && rx_rate)
3050 omap_mcbsp_rx_start(s);
3051 else if (prev_tx_rate && !tx_rate)
3052 omap_mcbsp_rx_stop(s);
3053 }
3054
3055 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
3056 unsigned size)
3057 {
3058 struct omap_mcbsp_s *s = opaque;
3059 int offset = addr & OMAP_MPUI_REG_MASK;
3060 uint16_t ret;
3061
3062 if (size != 2) {
3063 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
3064 " with bad width %d\n", __func__, addr, size);
3065 return 0;
3066 }
3067
3068 switch (offset) {
3069 case 0x00: /* DRR2 */
3070 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3071 return 0x0000;
3072 /* Fall through. */
3073 case 0x02: /* DRR1 */
3074 if (s->rx_req < 2) {
3075 qemu_log_mask(LOG_GUEST_ERROR, "%s: Rx FIFO underrun\n", __func__);
3076 omap_mcbsp_rx_done(s);
3077 } else {
3078 s->tx_req -= 2;
3079 if (s->codec && s->codec->in.len >= 2) {
3080 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3081 ret |= s->codec->in.fifo[s->codec->in.start ++];
3082 s->codec->in.len -= 2;
3083 } else
3084 ret = 0x0000;
3085 if (!s->tx_req)
3086 omap_mcbsp_rx_done(s);
3087 return ret;
3088 }
3089 return 0x0000;
3090
3091 case 0x04: /* DXR2 */
3092 case 0x06: /* DXR1 */
3093 return 0x0000;
3094
3095 case 0x08: /* SPCR2 */
3096 return s->spcr[1];
3097 case 0x0a: /* SPCR1 */
3098 return s->spcr[0];
3099 case 0x0c: /* RCR2 */
3100 return s->rcr[1];
3101 case 0x0e: /* RCR1 */
3102 return s->rcr[0];
3103 case 0x10: /* XCR2 */
3104 return s->xcr[1];
3105 case 0x12: /* XCR1 */
3106 return s->xcr[0];
3107 case 0x14: /* SRGR2 */
3108 return s->srgr[1];
3109 case 0x16: /* SRGR1 */
3110 return s->srgr[0];
3111 case 0x18: /* MCR2 */
3112 return s->mcr[1];
3113 case 0x1a: /* MCR1 */
3114 return s->mcr[0];
3115 case 0x1c: /* RCERA */
3116 return s->rcer[0];
3117 case 0x1e: /* RCERB */
3118 return s->rcer[1];
3119 case 0x20: /* XCERA */
3120 return s->xcer[0];
3121 case 0x22: /* XCERB */
3122 return s->xcer[1];
3123 case 0x24: /* PCR0 */
3124 return s->pcr;
3125 case 0x26: /* RCERC */
3126 return s->rcer[2];
3127 case 0x28: /* RCERD */
3128 return s->rcer[3];
3129 case 0x2a: /* XCERC */
3130 return s->xcer[2];
3131 case 0x2c: /* XCERD */
3132 return s->xcer[3];
3133 case 0x2e: /* RCERE */
3134 return s->rcer[4];
3135 case 0x30: /* RCERF */
3136 return s->rcer[5];
3137 case 0x32: /* XCERE */
3138 return s->xcer[4];
3139 case 0x34: /* XCERF */
3140 return s->xcer[5];
3141 case 0x36: /* RCERG */
3142 return s->rcer[6];
3143 case 0x38: /* RCERH */
3144 return s->rcer[7];
3145 case 0x3a: /* XCERG */
3146 return s->xcer[6];
3147 case 0x3c: /* XCERH */
3148 return s->xcer[7];
3149 }
3150
3151 OMAP_BAD_REG(addr);
3152 return 0;
3153 }
3154
3155 static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
3156 uint32_t value)
3157 {
3158 struct omap_mcbsp_s *s = opaque;
3159 int offset = addr & OMAP_MPUI_REG_MASK;
3160
3161 switch (offset) {
3162 case 0x00: /* DRR2 */
3163 case 0x02: /* DRR1 */
3164 OMAP_RO_REG(addr);
3165 return;
3166
3167 case 0x04: /* DXR2 */
3168 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3169 return;
3170 /* Fall through. */
3171 case 0x06: /* DXR1 */
3172 if (s->tx_req > 1) {
3173 s->tx_req -= 2;
3174 if (s->codec && s->codec->cts) {
3175 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3176 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
3177 }
3178 if (s->tx_req < 2)
3179 omap_mcbsp_tx_done(s);
3180 } else {
3181 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO overrun\n", __func__);
3182 }
3183 return;
3184
3185 case 0x08: /* SPCR2 */
3186 s->spcr[1] &= 0x0002;
3187 s->spcr[1] |= 0x03f9 & value;
3188 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
3189 if (~value & 1) /* XRST */
3190 s->spcr[1] &= ~6;
3191 omap_mcbsp_req_update(s);
3192 return;
3193 case 0x0a: /* SPCR1 */
3194 s->spcr[0] &= 0x0006;
3195 s->spcr[0] |= 0xf8f9 & value;
3196 if (value & (1 << 15)) { /* DLB */
3197 qemu_log_mask(LOG_UNIMP,
3198 "%s: Digital Loopback mode enable attempt\n",
3199 __func__);
3200 }
3201 if (~value & 1) { /* RRST */
3202 s->spcr[0] &= ~6;
3203 s->rx_req = 0;
3204 omap_mcbsp_rx_done(s);
3205 }
3206 omap_mcbsp_req_update(s);
3207 return;
3208
3209 case 0x0c: /* RCR2 */
3210 s->rcr[1] = value & 0xffff;
3211 return;
3212 case 0x0e: /* RCR1 */
3213 s->rcr[0] = value & 0x7fe0;
3214 return;
3215 case 0x10: /* XCR2 */
3216 s->xcr[1] = value & 0xffff;
3217 return;
3218 case 0x12: /* XCR1 */
3219 s->xcr[0] = value & 0x7fe0;
3220 return;
3221 case 0x14: /* SRGR2 */
3222 s->srgr[1] = value & 0xffff;
3223 omap_mcbsp_req_update(s);
3224 return;
3225 case 0x16: /* SRGR1 */
3226 s->srgr[0] = value & 0xffff;
3227 omap_mcbsp_req_update(s);
3228 return;
3229 case 0x18: /* MCR2 */
3230 s->mcr[1] = value & 0x03e3;
3231 if (value & 3) { /* XMCM */
3232 qemu_log_mask(LOG_UNIMP,
3233 "%s: Tx channel selection mode enable attempt\n",
3234 __func__);
3235 }
3236 return;
3237 case 0x1a: /* MCR1 */
3238 s->mcr[0] = value & 0x03e1;
3239 if (value & 1) { /* RMCM */
3240 qemu_log_mask(LOG_UNIMP,
3241 "%s: Rx channel selection mode enable attempt\n",
3242 __func__);
3243 }
3244 return;
3245 case 0x1c: /* RCERA */
3246 s->rcer[0] = value & 0xffff;
3247 return;
3248 case 0x1e: /* RCERB */
3249 s->rcer[1] = value & 0xffff;
3250 return;
3251 case 0x20: /* XCERA */
3252 s->xcer[0] = value & 0xffff;
3253 return;
3254 case 0x22: /* XCERB */
3255 s->xcer[1] = value & 0xffff;
3256 return;
3257 case 0x24: /* PCR0 */
3258 s->pcr = value & 0x7faf;
3259 return;
3260 case 0x26: /* RCERC */
3261 s->rcer[2] = value & 0xffff;
3262 return;
3263 case 0x28: /* RCERD */
3264 s->rcer[3] = value & 0xffff;
3265 return;
3266 case 0x2a: /* XCERC */
3267 s->xcer[2] = value & 0xffff;
3268 return;
3269 case 0x2c: /* XCERD */
3270 s->xcer[3] = value & 0xffff;
3271 return;
3272 case 0x2e: /* RCERE */
3273 s->rcer[4] = value & 0xffff;
3274 return;
3275 case 0x30: /* RCERF */
3276 s->rcer[5] = value & 0xffff;
3277 return;
3278 case 0x32: /* XCERE */
3279 s->xcer[4] = value & 0xffff;
3280 return;
3281 case 0x34: /* XCERF */
3282 s->xcer[5] = value & 0xffff;
3283 return;
3284 case 0x36: /* RCERG */
3285 s->rcer[6] = value & 0xffff;
3286 return;
3287 case 0x38: /* RCERH */
3288 s->rcer[7] = value & 0xffff;
3289 return;
3290 case 0x3a: /* XCERG */
3291 s->xcer[6] = value & 0xffff;
3292 return;
3293 case 0x3c: /* XCERH */
3294 s->xcer[7] = value & 0xffff;
3295 return;
3296 }
3297
3298 OMAP_BAD_REG(addr);
3299 }
3300
3301 static void omap_mcbsp_writew(void *opaque, hwaddr addr,
3302 uint32_t value)
3303 {
3304 struct omap_mcbsp_s *s = opaque;
3305 int offset = addr & OMAP_MPUI_REG_MASK;
3306
3307 if (offset == 0x04) { /* DXR */
3308 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3309 return;
3310 if (s->tx_req > 3) {
3311 s->tx_req -= 4;
3312 if (s->codec && s->codec->cts) {
3313 s->codec->out.fifo[s->codec->out.len ++] =
3314 (value >> 24) & 0xff;
3315 s->codec->out.fifo[s->codec->out.len ++] =
3316 (value >> 16) & 0xff;
3317 s->codec->out.fifo[s->codec->out.len ++] =
3318 (value >> 8) & 0xff;
3319 s->codec->out.fifo[s->codec->out.len ++] =
3320 (value >> 0) & 0xff;
3321 }
3322 if (s->tx_req < 4)
3323 omap_mcbsp_tx_done(s);
3324 } else {
3325 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO overrun\n", __func__);
3326 }
3327 return;
3328 }
3329
3330 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
3331 " with bad width %d\n", __func__, addr, 4);
3332 }
3333
3334 static void omap_mcbsp_write(void *opaque, hwaddr addr,
3335 uint64_t value, unsigned size)
3336 {
3337 switch (size) {
3338 case 2:
3339 omap_mcbsp_writeh(opaque, addr, value);
3340 break;
3341 case 4:
3342 omap_mcbsp_writew(opaque, addr, value);
3343 break;
3344 default:
3345 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
3346 " with bad width %d\n", __func__, addr, size);
3347 }
3348 }
3349
3350 static const MemoryRegionOps omap_mcbsp_ops = {
3351 .read = omap_mcbsp_read,
3352 .write = omap_mcbsp_write,
3353 .endianness = DEVICE_NATIVE_ENDIAN,
3354 };
3355
3356 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3357 {
3358 memset(&s->spcr, 0, sizeof(s->spcr));
3359 memset(&s->rcr, 0, sizeof(s->rcr));
3360 memset(&s->xcr, 0, sizeof(s->xcr));
3361 s->srgr[0] = 0x0001;
3362 s->srgr[1] = 0x2000;
3363 memset(&s->mcr, 0, sizeof(s->mcr));
3364 memset(&s->pcr, 0, sizeof(s->pcr));
3365 memset(&s->rcer, 0, sizeof(s->rcer));
3366 memset(&s->xcer, 0, sizeof(s->xcer));
3367 s->tx_req = 0;
3368 s->rx_req = 0;
3369 s->tx_rate = 0;
3370 s->rx_rate = 0;
3371 timer_del(s->source_timer);
3372 timer_del(s->sink_timer);
3373 }
3374
3375 static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
3376 hwaddr base,
3377 qemu_irq txirq, qemu_irq rxirq,
3378 qemu_irq *dma, omap_clk clk)
3379 {
3380 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1);
3381
3382 s->txirq = txirq;
3383 s->rxirq = rxirq;
3384 s->txdrq = dma[0];
3385 s->rxdrq = dma[1];
3386 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s);
3387 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s);
3388 omap_mcbsp_reset(s);
3389
3390 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
3391 memory_region_add_subregion(system_memory, base, &s->iomem);
3392
3393 return s;
3394 }
3395
3396 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
3397 {
3398 struct omap_mcbsp_s *s = opaque;
3399
3400 if (s->rx_rate) {
3401 s->rx_req = s->codec->in.len;
3402 omap_mcbsp_rx_newdata(s);
3403 }
3404 }
3405
3406 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
3407 {
3408 struct omap_mcbsp_s *s = opaque;
3409
3410 if (s->tx_rate) {
3411 s->tx_req = s->codec->out.size;
3412 omap_mcbsp_tx_newdata(s);
3413 }
3414 }
3415
3416 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
3417 {
3418 s->codec = slave;
3419 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0);
3420 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0);
3421 }
3422
3423 /* LED Pulse Generators */
3424 struct omap_lpg_s {
3425 MemoryRegion iomem;
3426 QEMUTimer *tm;
3427
3428 uint8_t control;
3429 uint8_t power;
3430 int64_t on;
3431 int64_t period;
3432 int clk;
3433 int cycle;
3434 };
3435
3436 static void omap_lpg_tick(void *opaque)
3437 {
3438 struct omap_lpg_s *s = opaque;
3439
3440 if (s->cycle)
3441 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on);
3442 else
3443 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on);
3444
3445 s->cycle = !s->cycle;
3446 trace_omap1_lpg_led(s->cycle ? "on" : "off");
3447 }
3448
3449 static void omap_lpg_update(struct omap_lpg_s *s)
3450 {
3451 int64_t on, period = 1, ticks = 1000;
3452 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3453
3454 if (~s->control & (1 << 6)) /* LPGRES */
3455 on = 0;
3456 else if (s->control & (1 << 7)) /* PERM_ON */
3457 on = period;
3458 else {
3459 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3460 256 / 32);
3461 on = (s->clk && s->power) ? muldiv64(ticks,
3462 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3463 }
3464
3465 timer_del(s->tm);
3466 if (on == period && s->on < s->period) {
3467 trace_omap1_lpg_led("on");
3468 } else if (on == 0 && s->on) {
3469 trace_omap1_lpg_led("off");
3470 } else if (on && (on != s->on || period != s->period)) {
3471 s->cycle = 0;
3472 s->on = on;
3473 s->period = period;
3474 omap_lpg_tick(s);
3475 return;
3476 }
3477
3478 s->on = on;
3479 s->period = period;
3480 }
3481
3482 static void omap_lpg_reset(struct omap_lpg_s *s)
3483 {
3484 s->control = 0x00;
3485 s->power = 0x00;
3486 s->clk = 1;
3487 omap_lpg_update(s);
3488 }
3489
3490 static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
3491 {
3492 struct omap_lpg_s *s = opaque;
3493 int offset = addr & OMAP_MPUI_REG_MASK;
3494
3495 if (size != 1) {
3496 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
3497 " with bad width %d\n", __func__, addr, size);
3498 return 0;
3499 }
3500
3501 switch (offset) {
3502 case 0x00: /* LCR */
3503 return s->control;
3504
3505 case 0x04: /* PMR */
3506 return s->power;
3507 }
3508
3509 OMAP_BAD_REG(addr);
3510 return 0;
3511 }
3512
3513 static void omap_lpg_write(void *opaque, hwaddr addr,
3514 uint64_t value, unsigned size)
3515 {
3516 struct omap_lpg_s *s = opaque;
3517 int offset = addr & OMAP_MPUI_REG_MASK;
3518
3519 if (size != 1) {
3520 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
3521 " with bad width %d\n", __func__, addr, size);
3522 return;
3523 }
3524
3525 switch (offset) {
3526 case 0x00: /* LCR */
3527 if (~value & (1 << 6)) /* LPGRES */
3528 omap_lpg_reset(s);
3529 s->control = value & 0xff;
3530 omap_lpg_update(s);
3531 return;
3532
3533 case 0x04: /* PMR */
3534 s->power = value & 0x01;
3535 omap_lpg_update(s);
3536 return;
3537
3538 default:
3539 OMAP_BAD_REG(addr);
3540 return;
3541 }
3542 }
3543
3544 static const MemoryRegionOps omap_lpg_ops = {
3545 .read = omap_lpg_read,
3546 .write = omap_lpg_write,
3547 .endianness = DEVICE_NATIVE_ENDIAN,
3548 };
3549
3550 static void omap_lpg_clk_update(void *opaque, int line, int on)
3551 {
3552 struct omap_lpg_s *s = opaque;
3553
3554 s->clk = on;
3555 omap_lpg_update(s);
3556 }
3557
3558 static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
3559 hwaddr base, omap_clk clk)
3560 {
3561 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1);
3562
3563 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s);
3564
3565 omap_lpg_reset(s);
3566
3567 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800);
3568 memory_region_add_subregion(system_memory, base, &s->iomem);
3569
3570 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0));
3571
3572 return s;
3573 }
3574
3575 /* MPUI Peripheral Bridge configuration */
3576 static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
3577 unsigned size)
3578 {
3579 if (size != 2) {
3580 qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx
3581 " with bad width %d\n", __func__, addr, size);
3582 return 0;
3583 }
3584
3585 if (addr == OMAP_MPUI_BASE) /* CMR */
3586 return 0xfe4d;
3587
3588 OMAP_BAD_REG(addr);
3589 return 0;
3590 }
3591
3592 static void omap_mpui_io_write(void *opaque, hwaddr addr,
3593 uint64_t value, unsigned size)
3594 {
3595 qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx
3596 " with bad width %d\n", __func__, addr, size);
3597 }
3598
3599 static const MemoryRegionOps omap_mpui_io_ops = {
3600 .read = omap_mpui_io_read,
3601 .write = omap_mpui_io_write,
3602 .endianness = DEVICE_NATIVE_ENDIAN,
3603 };
3604
3605 static void omap_setup_mpui_io(MemoryRegion *system_memory,
3606 struct omap_mpu_state_s *mpu)
3607 {
3608 memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu,
3609 "omap-mpui-io", 0x7fff);
3610 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
3611 &mpu->mpui_io_iomem);
3612 }
3613
3614 /* General chip reset */
3615 static void omap1_mpu_reset(void *opaque)
3616 {
3617 struct omap_mpu_state_s *mpu = opaque;
3618
3619 omap_dma_reset(mpu->dma);
3620 omap_mpu_timer_reset(mpu->timer[0]);
3621 omap_mpu_timer_reset(mpu->timer[1]);
3622 omap_mpu_timer_reset(mpu->timer[2]);
3623 omap_wd_timer_reset(mpu->wdt);
3624 omap_os_timer_reset(mpu->os_timer);
3625 omap_lcdc_reset(mpu->lcd);
3626 omap_ulpd_pm_reset(mpu);
3627 omap_pin_cfg_reset(mpu);
3628 omap_mpui_reset(mpu);
3629 omap_tipb_bridge_reset(mpu->private_tipb);
3630 omap_tipb_bridge_reset(mpu->public_tipb);
3631 omap_dpll_reset(mpu->dpll[0]);
3632 omap_dpll_reset(mpu->dpll[1]);
3633 omap_dpll_reset(mpu->dpll[2]);
3634 omap_uart_reset(mpu->uart[0]);
3635 omap_uart_reset(mpu->uart[1]);
3636 omap_uart_reset(mpu->uart[2]);
3637 omap_mpuio_reset(mpu->mpuio);
3638 omap_uwire_reset(mpu->microwire);
3639 omap_pwl_reset(mpu->pwl);
3640 omap_pwt_reset(mpu->pwt);
3641 omap_rtc_reset(mpu->rtc);
3642 omap_mcbsp_reset(mpu->mcbsp1);
3643 omap_mcbsp_reset(mpu->mcbsp2);
3644 omap_mcbsp_reset(mpu->mcbsp3);
3645 omap_lpg_reset(mpu->led[0]);
3646 omap_lpg_reset(mpu->led[1]);
3647 omap_clkm_reset(mpu);
3648 cpu_reset(CPU(mpu->cpu));
3649 }
3650
3651 static const struct omap_map_s {
3652 hwaddr phys_dsp;
3653 hwaddr phys_mpu;
3654 uint32_t size;
3655 const char *name;
3656 } omap15xx_dsp_mm[] = {
3657 /* Strobe 0 */
3658 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3659 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3660 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3661 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3662 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3663 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3664 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3665 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3666 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3667 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3668 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3669 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3670 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3671 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3672 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3673 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3674 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3675 /* Strobe 1 */
3676 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3677
3678 { 0 }
3679 };
3680
3681 static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
3682 const struct omap_map_s *map)
3683 {
3684 MemoryRegion *io;
3685
3686 for (; map->phys_dsp; map ++) {
3687 io = g_new(MemoryRegion, 1);
3688 memory_region_init_alias(io, NULL, map->name,
3689 system_memory, map->phys_mpu, map->size);
3690 memory_region_add_subregion(system_memory, map->phys_dsp, io);
3691 }
3692 }
3693
3694 static const struct dma_irq_map omap1_dma_irq_map[] = {
3695 { 0, OMAP_INT_DMA_CH0_6 },
3696 { 0, OMAP_INT_DMA_CH1_7 },
3697 { 0, OMAP_INT_DMA_CH2_8 },
3698 { 0, OMAP_INT_DMA_CH3 },
3699 { 0, OMAP_INT_DMA_CH4 },
3700 { 0, OMAP_INT_DMA_CH5 },
3701 };
3702
3703 /* DMA ports for OMAP1 */
3704 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
3705 hwaddr addr)
3706 {
3707 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
3708 }
3709
3710 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
3711 hwaddr addr)
3712 {
3713 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3714 addr);
3715 }
3716
3717 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
3718 hwaddr addr)
3719 {
3720 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
3721 }
3722
3723 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
3724 hwaddr addr)
3725 {
3726 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
3727 }
3728
3729 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
3730 hwaddr addr)
3731 {
3732 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
3733 }
3734
3735 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
3736 hwaddr addr)
3737 {
3738 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
3739 }
3740
3741 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
3742 const char *cpu_type)
3743 {
3744 int i;
3745 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
3746 qemu_irq dma_irqs[6];
3747 DriveInfo *dinfo;
3748 SysBusDevice *busdev;
3749 MemoryRegion *system_memory = get_system_memory();
3750
3751 /* Core */
3752 s->cpu = ARM_CPU(cpu_create(cpu_type));
3753 s->sdram_size = memory_region_size(dram);
3754 s->sram_size = OMAP15XX_SRAM_SIZE;
3755
3756 /* Clocks */
3757 omap_clk_init(s);
3758
3759 /* Memory-mapped stuff */
3760 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
3761 &error_fatal);
3762 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
3763
3764 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
3765
3766 s->ih[0] = qdev_new("omap-intc");
3767 qdev_prop_set_uint32(s->ih[0], "size", 0x100);
3768 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
3769 busdev = SYS_BUS_DEVICE(s->ih[0]);
3770 sysbus_realize_and_unref(busdev, &error_fatal);
3771 sysbus_connect_irq(busdev, 0,
3772 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
3773 sysbus_connect_irq(busdev, 1,
3774 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
3775 sysbus_mmio_map(busdev, 0, 0xfffecb00);
3776 s->ih[1] = qdev_new("omap-intc");
3777 qdev_prop_set_uint32(s->ih[1], "size", 0x800);
3778 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
3779 busdev = SYS_BUS_DEVICE(s->ih[1]);
3780 sysbus_realize_and_unref(busdev, &error_fatal);
3781 sysbus_connect_irq(busdev, 0,
3782 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
3783 /* The second interrupt controller's FIQ output is not wired up */
3784 sysbus_mmio_map(busdev, 0, 0xfffe0000);
3785
3786 for (i = 0; i < 6; i++) {
3787 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
3788 omap1_dma_irq_map[i].intr);
3789 }
3790 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
3791 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
3792 s, omap_findclk(s, "dma_ck"));
3793
3794 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3795 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3796 s->port[imif ].addr_valid = omap_validate_imif_addr;
3797 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3798 s->port[local ].addr_valid = omap_validate_local_addr;
3799 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3800
3801 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3802 soc_dma_port_add_mem(s->dma, OMAP_EMIFF_BASE, s->sdram_size);
3803 soc_dma_port_add_mem(s->dma, OMAP_IMIF_BASE, s->sram_size);
3804
3805 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
3806 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
3807 omap_findclk(s, "mputim_ck"));
3808 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
3809 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
3810 omap_findclk(s, "mputim_ck"));
3811 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
3812 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
3813 omap_findclk(s, "mputim_ck"));
3814
3815 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
3816 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
3817 omap_findclk(s, "armwdt_ck"));
3818
3819 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
3820 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
3821 omap_findclk(s, "clk32-kHz"));
3822
3823 s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
3824 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
3825 omap_dma_get_lcdch(s->dma),
3826 omap_findclk(s, "lcd_ck"));
3827
3828 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3829 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3830 omap_id_init(system_memory, s);
3831
3832 omap_mpui_init(system_memory, 0xfffec900, s);
3833
3834 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
3835 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
3836 omap_findclk(s, "tipb_ck"));
3837 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
3838 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
3839 omap_findclk(s, "tipb_ck"));
3840
3841 omap_tcmi_init(system_memory, 0xfffecc00, s);
3842
3843 s->uart[0] = omap_uart_init(0xfffb0000,
3844 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
3845 omap_findclk(s, "uart1_ck"),
3846 omap_findclk(s, "uart1_ck"),
3847 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
3848 "uart1",
3849 serial_hd(0));
3850 s->uart[1] = omap_uart_init(0xfffb0800,
3851 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
3852 omap_findclk(s, "uart2_ck"),
3853 omap_findclk(s, "uart2_ck"),
3854 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
3855 "uart2",
3856 serial_hd(0) ? serial_hd(1) : NULL);
3857 s->uart[2] = omap_uart_init(0xfffb9800,
3858 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
3859 omap_findclk(s, "uart3_ck"),
3860 omap_findclk(s, "uart3_ck"),
3861 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
3862 "uart3",
3863 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
3864
3865 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
3866 omap_findclk(s, "dpll1"));
3867 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
3868 omap_findclk(s, "dpll2"));
3869 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
3870 omap_findclk(s, "dpll3"));
3871
3872 dinfo = drive_get(IF_SD, 0, 0);
3873 if (!dinfo && !qtest_enabled()) {
3874 warn_report("missing SecureDigital device");
3875 }
3876
3877 s->mmc = qdev_new(TYPE_OMAP_MMC);
3878 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->mmc), &error_fatal);
3879 omap_mmc_set_clk(s->mmc, omap_findclk(s, "mmc_ck"));
3880
3881 memory_region_add_subregion(system_memory, 0xfffb7800,
3882 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->mmc), 0));
3883 qdev_connect_gpio_out_named(s->mmc, "dma-tx", 0, s->drq[OMAP_DMA_MMC_TX]);
3884 qdev_connect_gpio_out_named(s->mmc, "dma-rx", 0, s->drq[OMAP_DMA_MMC_RX]);
3885 sysbus_connect_irq(SYS_BUS_DEVICE(s->mmc), 0,
3886 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN));
3887
3888 if (dinfo) {
3889 DeviceState *card = qdev_new(TYPE_SD_CARD);
3890 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
3891 &error_fatal);
3892 qdev_realize_and_unref(card, qdev_get_child_bus(s->mmc, "sd-bus"),
3893 &error_fatal);
3894 }
3895
3896 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
3897 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
3898 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
3899 omap_findclk(s, "clk32-kHz"));
3900
3901 s->gpio = qdev_new("omap-gpio");
3902 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
3903 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal);
3904 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
3905 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
3906 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000);
3907
3908 s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
3909 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
3910 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
3911 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
3912
3913 s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
3914 omap_findclk(s, "armxor_ck"));
3915 s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
3916 omap_findclk(s, "armxor_ck"));
3917
3918 s->i2c[0] = qdev_new("omap_i2c");
3919 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
3920 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
3921 busdev = SYS_BUS_DEVICE(s->i2c[0]);
3922 sysbus_realize_and_unref(busdev, &error_fatal);
3923 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
3924 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
3925 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
3926 sysbus_mmio_map(busdev, 0, 0xfffb3800);
3927
3928 s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
3929 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
3930 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
3931 omap_findclk(s, "clk32-kHz"));
3932
3933 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
3934 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
3935 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
3936 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
3937 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
3938 qdev_get_gpio_in(s->ih[0],
3939 OMAP_INT_310_McBSP2_TX),
3940 qdev_get_gpio_in(s->ih[0],
3941 OMAP_INT_310_McBSP2_RX),
3942 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
3943 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
3944 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
3945 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
3946 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
3947
3948 s->led[0] = omap_lpg_init(system_memory,
3949 0xfffbd000, omap_findclk(s, "clk32-kHz"));
3950 s->led[1] = omap_lpg_init(system_memory,
3951 0xfffbd800, omap_findclk(s, "clk32-kHz"));
3952
3953 /* Register mappings not currently implemented:
3954 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
3955 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
3956 * USB W2FC fffb4000 - fffb47ff
3957 * Camera Interface fffb6800 - fffb6fff
3958 * USB Host fffba000 - fffba7ff
3959 * FAC fffba800 - fffbafff
3960 * HDQ/1-Wire fffbc000 - fffbc7ff
3961 * TIPB switches fffbc800 - fffbcfff
3962 * Mailbox fffcf000 - fffcf7ff
3963 * Local bus IF fffec100 - fffec1ff
3964 * Local bus MMU fffec200 - fffec2ff
3965 * DSP MMU fffed200 - fffed2ff
3966 */
3967
3968 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
3969 omap_setup_mpui_io(system_memory, s);
3970
3971 qemu_register_reset(omap1_mpu_reset, s);
3972
3973 return s;
3974 }