| 1 | /* |
| 2 | * ARM RealView Baseboard System emulation. |
| 3 | * |
| 4 | * Copyright (c) 2006-2007 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This code is licensed under the GPL. |
| 8 | */ |
| 9 | |
| 10 | #include "qemu/osdep.h" |
| 11 | #include "qapi/error.h" |
| 12 | #include "target/arm/cpu.h" |
| 13 | #include "hw/core/sysbus.h" |
| 14 | #include "hw/arm/boot.h" |
| 15 | #include "hw/arm/machines-qom.h" |
| 16 | #include "hw/core/split-irq.h" |
| 17 | #include "hw/misc/arm_sysctl.h" |
| 18 | #include "hw/net/lan9118.h" |
| 19 | #include "hw/net/smc91c111.h" |
| 20 | #include "hw/pci/pci.h" |
| 21 | #include "hw/core/qdev.h" |
| 22 | #include "net/net.h" |
| 23 | #include "system/system.h" |
| 24 | #include "hw/core/boards.h" |
| 25 | #include "hw/i2c/i2c.h" |
| 26 | #include "qemu/error-report.h" |
| 27 | #include "hw/char/pl011.h" |
| 28 | #include "hw/cpu/a9mpcore.h" |
| 29 | #include "hw/intc/realview_gic.h" |
| 30 | #include "hw/core/irq.h" |
| 31 | #include "hw/i2c/arm_sbcon_i2c.h" |
| 32 | #include "hw/sd/sd.h" |
| 33 | #include "target/arm/cpu-qom.h" |
| 34 | |
| 35 | #define SMP_BOOT_ADDR 0xe0000000 |
| 36 | #define SMP_BOOTREG_ADDR 0x10000030 |
| 37 | |
| 38 | #define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */ |
| 39 | |
| 40 | /* Board init. */ |
| 41 | |
| 42 | typedef struct RealViewMachineState { |
| 43 | MachineState parent; |
| 44 | |
| 45 | struct arm_boot_info bootinfo; |
| 46 | } RealViewMachineState; |
| 47 | |
| 48 | /* The following two lists must be consistent. */ |
| 49 | enum realview_board_type { |
| 50 | BOARD_EB, |
| 51 | BOARD_EB_MPCORE, |
| 52 | BOARD_PB_A8, |
| 53 | BOARD_PBX_A9, |
| 54 | }; |
| 55 | |
| 56 | static const int realview_board_id[] = { |
| 57 | 0x33b, |
| 58 | 0x33b, |
| 59 | 0x769, |
| 60 | 0x76d |
| 61 | }; |
| 62 | |
| 63 | static void split_irq_from_named(DeviceState *src, const char* outname, |
| 64 | qemu_irq out1, qemu_irq out2) { |
| 65 | DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); |
| 66 | |
| 67 | qdev_prop_set_uint32(splitter, "num-lines", 2); |
| 68 | |
| 69 | qdev_realize_and_unref(splitter, NULL, &error_fatal); |
| 70 | |
| 71 | qdev_connect_gpio_out(splitter, 0, out1); |
| 72 | qdev_connect_gpio_out(splitter, 1, out2); |
| 73 | qdev_connect_gpio_out_named(src, outname, 0, |
| 74 | qdev_get_gpio_in(splitter, 0)); |
| 75 | } |
| 76 | |
| 77 | static void realview_init(MachineState *machine, |
| 78 | enum realview_board_type board_type) |
| 79 | { |
| 80 | /* All realview-* machines embed the same state as their first member */ |
| 81 | RealViewMachineState *rvms = (RealViewMachineState *)machine; |
| 82 | ARMCPU *cpu = NULL; |
| 83 | CPUARMState *env; |
| 84 | MemoryRegion *sysmem = get_system_memory(); |
| 85 | MemoryRegion *ram_lo; |
| 86 | MemoryRegion *ram_hi = g_new(MemoryRegion, 1); |
| 87 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); |
| 88 | MemoryRegion *ram_hack = g_new(MemoryRegion, 1); |
| 89 | DeviceState *dev, *sysctl, *gpio2, *pl041; |
| 90 | SysBusDevice *busdev; |
| 91 | qemu_irq pic[64]; |
| 92 | PCIBus *pci_bus = NULL; |
| 93 | DriveInfo *dinfo; |
| 94 | I2CBus *i2c; |
| 95 | int n; |
| 96 | unsigned int smp_cpus = machine->smp.cpus; |
| 97 | qemu_irq cpu_irq[4]; |
| 98 | int is_mpcore = 0; |
| 99 | int is_pb = 0; |
| 100 | uint32_t proc_id = 0; |
| 101 | uint32_t sys_id; |
| 102 | ram_addr_t low_ram_size; |
| 103 | ram_addr_t ram_size = machine->ram_size; |
| 104 | hwaddr periphbase = 0; |
| 105 | |
| 106 | switch (board_type) { |
| 107 | case BOARD_EB: |
| 108 | break; |
| 109 | case BOARD_EB_MPCORE: |
| 110 | is_mpcore = 1; |
| 111 | periphbase = 0x10100000; |
| 112 | break; |
| 113 | case BOARD_PB_A8: |
| 114 | is_pb = 1; |
| 115 | break; |
| 116 | case BOARD_PBX_A9: |
| 117 | is_mpcore = 1; |
| 118 | is_pb = 1; |
| 119 | periphbase = 0x1f000000; |
| 120 | break; |
| 121 | } |
| 122 | |
| 123 | for (n = 0; n < smp_cpus; n++) { |
| 124 | Object *cpuobj = object_new(machine->cpu_type); |
| 125 | |
| 126 | /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board |
| 127 | * does not currently support EL3 so the CPU EL3 property is disabled |
| 128 | * before realization. |
| 129 | */ |
| 130 | if (object_property_find(cpuobj, "has_el3")) { |
| 131 | object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); |
| 132 | } |
| 133 | |
| 134 | if (is_pb && is_mpcore) { |
| 135 | object_property_set_int(cpuobj, "reset-cbar", periphbase, |
| 136 | &error_fatal); |
| 137 | } |
| 138 | |
| 139 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 140 | |
| 141 | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); |
| 142 | } |
| 143 | cpu = ARM_CPU(first_cpu); |
| 144 | env = &cpu->env; |
| 145 | if (arm_feature(env, ARM_FEATURE_V7)) { |
| 146 | if (is_mpcore) { |
| 147 | proc_id = 0x0c000000; |
| 148 | } else { |
| 149 | proc_id = 0x0e000000; |
| 150 | } |
| 151 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { |
| 152 | proc_id = 0x06000000; |
| 153 | } else if (arm_feature(env, ARM_FEATURE_V6)) { |
| 154 | proc_id = 0x04000000; |
| 155 | } else { |
| 156 | proc_id = 0x02000000; |
| 157 | } |
| 158 | |
| 159 | if (is_pb && ram_size > 0x20000000) { |
| 160 | /* Core tile RAM. */ |
| 161 | ram_lo = g_new(MemoryRegion, 1); |
| 162 | low_ram_size = ram_size - 0x20000000; |
| 163 | ram_size = 0x20000000; |
| 164 | memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, |
| 165 | &error_fatal); |
| 166 | memory_region_add_subregion(sysmem, 0x20000000, ram_lo); |
| 167 | } |
| 168 | |
| 169 | memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, |
| 170 | &error_fatal); |
| 171 | low_ram_size = ram_size; |
| 172 | if (low_ram_size > 0x10000000) |
| 173 | low_ram_size = 0x10000000; |
| 174 | /* SDRAM at address zero. */ |
| 175 | memory_region_init_alias(ram_alias, NULL, "realview.alias", |
| 176 | ram_hi, 0, low_ram_size); |
| 177 | memory_region_add_subregion(sysmem, 0, ram_alias); |
| 178 | if (is_pb) { |
| 179 | /* And again at a high address. */ |
| 180 | memory_region_add_subregion(sysmem, 0x70000000, ram_hi); |
| 181 | } else { |
| 182 | ram_size = low_ram_size; |
| 183 | } |
| 184 | |
| 185 | sys_id = is_pb ? 0x01780500 : 0xc1400400; |
| 186 | sysctl = qdev_new("realview_sysctl"); |
| 187 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); |
| 188 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); |
| 189 | sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); |
| 190 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); |
| 191 | |
| 192 | if (is_mpcore) { |
| 193 | if (is_pb) { |
| 194 | dev = qdev_new(TYPE_A9MPCORE_PRIV); |
| 195 | qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); |
| 196 | } else { |
| 197 | dev = qdev_new("realview_mpcore"); |
| 198 | } |
| 199 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
| 200 | busdev = SYS_BUS_DEVICE(dev); |
| 201 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 202 | sysbus_mmio_map(busdev, 0, periphbase); |
| 203 | for (n = 0; n < smp_cpus; n++) { |
| 204 | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
| 205 | } |
| 206 | sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); |
| 207 | /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ |
| 208 | rvms->bootinfo.gic_cpu_if_addr = periphbase + 0x100; |
| 209 | } else { |
| 210 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; |
| 211 | /* For now just create the nIRQ GIC, and ignore the others. */ |
| 212 | dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); |
| 213 | } |
| 214 | for (n = 0; n < GIC_EXT_IRQS; n++) { |
| 215 | pic[n] = qdev_get_gpio_in(dev, n); |
| 216 | } |
| 217 | |
| 218 | pl041 = qdev_new("pl041"); |
| 219 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
| 220 | if (machine->audiodev) { |
| 221 | qdev_prop_set_string(pl041, "audiodev", machine->audiodev); |
| 222 | } |
| 223 | sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); |
| 224 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); |
| 225 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); |
| 226 | |
| 227 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); |
| 228 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); |
| 229 | |
| 230 | pl011_create(0x10009000, pic[12], serial_hd(0)); |
| 231 | pl011_create(0x1000a000, pic[13], serial_hd(1)); |
| 232 | pl011_create(0x1000b000, pic[14], serial_hd(2)); |
| 233 | pl011_create(0x1000c000, pic[15], serial_hd(3)); |
| 234 | |
| 235 | /* DMA controller is optional, apparently. */ |
| 236 | dev = qdev_new("pl081"); |
| 237 | object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), |
| 238 | &error_fatal); |
| 239 | busdev = SYS_BUS_DEVICE(dev); |
| 240 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 241 | sysbus_mmio_map(busdev, 0, 0x10030000); |
| 242 | sysbus_connect_irq(busdev, 0, pic[24]); |
| 243 | |
| 244 | sysbus_create_simple("sp804", 0x10011000, pic[4]); |
| 245 | sysbus_create_simple("sp804", 0x10012000, pic[5]); |
| 246 | |
| 247 | sysbus_create_simple("pl061", 0x10013000, pic[6]); |
| 248 | sysbus_create_simple("pl061", 0x10014000, pic[7]); |
| 249 | gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); |
| 250 | |
| 251 | dev = qdev_new("pl111"); |
| 252 | object_property_set_link(OBJECT(dev), "framebuffer-memory", |
| 253 | OBJECT(sysmem), &error_fatal); |
| 254 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 255 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x10020000); |
| 256 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[23]); |
| 257 | |
| 258 | dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); |
| 259 | /* Wire up MMC card detect and read-only signals. These have |
| 260 | * to go to both the PL061 GPIO and the sysctl register. |
| 261 | * Note that the PL181 orders these lines (readonly,inserted) |
| 262 | * and the PL061 has them the other way about. Also the card |
| 263 | * detect line is inverted. |
| 264 | */ |
| 265 | split_irq_from_named(dev, "card-read-only", |
| 266 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), |
| 267 | qdev_get_gpio_in(gpio2, 1)); |
| 268 | |
| 269 | split_irq_from_named(dev, "card-inserted", |
| 270 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), |
| 271 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); |
| 272 | |
| 273 | dinfo = drive_get(IF_SD, 0, 0); |
| 274 | if (dinfo) { |
| 275 | DeviceState *card; |
| 276 | |
| 277 | card = qdev_new(TYPE_SD_CARD); |
| 278 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), |
| 279 | &error_fatal); |
| 280 | qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), |
| 281 | &error_fatal); |
| 282 | } |
| 283 | |
| 284 | sysbus_create_simple("pl031", 0x10017000, pic[10]); |
| 285 | |
| 286 | if (!is_pb) { |
| 287 | dev = qdev_new("realview_pci"); |
| 288 | busdev = SYS_BUS_DEVICE(dev); |
| 289 | sysbus_realize_and_unref(busdev, &error_fatal); |
| 290 | sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ |
| 291 | sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ |
| 292 | sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ |
| 293 | sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ |
| 294 | sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ |
| 295 | sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ |
| 296 | sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ |
| 297 | sysbus_connect_irq(busdev, 0, pic[48]); |
| 298 | sysbus_connect_irq(busdev, 1, pic[49]); |
| 299 | sysbus_connect_irq(busdev, 2, pic[50]); |
| 300 | sysbus_connect_irq(busdev, 3, pic[51]); |
| 301 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
| 302 | if (machine_usb(machine)) { |
| 303 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
| 304 | } |
| 305 | n = drive_get_max_bus(IF_SCSI); |
| 306 | while (n >= 0) { |
| 307 | dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); |
| 308 | lsi53c8xx_handle_legacy_cmdline(dev); |
| 309 | n--; |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | if (qemu_find_nic_info(is_pb ? "lan9118" : "smc91c111", true, NULL)) { |
| 314 | if (is_pb) { |
| 315 | lan9118_init(0x4e000000, pic[28]); |
| 316 | } else { |
| 317 | smc91c111_init(0x4e000000, pic[28]); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | if (pci_bus) { |
| 322 | pci_init_nic_devices(pci_bus, "rtl8139"); |
| 323 | } |
| 324 | |
| 325 | dev = sysbus_create_simple(TYPE_ARM_SBCON_I2C, 0x10002000, NULL); |
| 326 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
| 327 | i2c_slave_create_simple(i2c, "ds1338", 0x68); |
| 328 | |
| 329 | /* Memory map for RealView Emulation Baseboard: */ |
| 330 | /* 0x10000000 System registers. */ |
| 331 | /* 0x10001000 System controller. */ |
| 332 | /* 0x10002000 Two-Wire Serial Bus. */ |
| 333 | /* 0x10003000 Reserved. */ |
| 334 | /* 0x10004000 AACI. */ |
| 335 | /* 0x10005000 MCI. */ |
| 336 | /* 0x10006000 KMI0. */ |
| 337 | /* 0x10007000 KMI1. */ |
| 338 | /* 0x10008000 Character LCD. (EB) */ |
| 339 | /* 0x10009000 UART0. */ |
| 340 | /* 0x1000a000 UART1. */ |
| 341 | /* 0x1000b000 UART2. */ |
| 342 | /* 0x1000c000 UART3. */ |
| 343 | /* 0x1000d000 SSPI. */ |
| 344 | /* 0x1000e000 SCI. */ |
| 345 | /* 0x1000f000 Reserved. */ |
| 346 | /* 0x10010000 Watchdog. */ |
| 347 | /* 0x10011000 Timer 0+1. */ |
| 348 | /* 0x10012000 Timer 2+3. */ |
| 349 | /* 0x10013000 GPIO 0. */ |
| 350 | /* 0x10014000 GPIO 1. */ |
| 351 | /* 0x10015000 GPIO 2. */ |
| 352 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ |
| 353 | /* 0x10017000 RTC. */ |
| 354 | /* 0x10018000 DMC. */ |
| 355 | /* 0x10019000 PCI controller config. */ |
| 356 | /* 0x10020000 CLCD. */ |
| 357 | /* 0x10030000 DMA Controller. */ |
| 358 | /* 0x10040000 GIC1. (EB) */ |
| 359 | /* 0x10050000 GIC2. (EB) */ |
| 360 | /* 0x10060000 GIC3. (EB) */ |
| 361 | /* 0x10070000 GIC4. (EB) */ |
| 362 | /* 0x10080000 SMC. */ |
| 363 | /* 0x1e000000 GIC1. (PB) */ |
| 364 | /* 0x1e001000 GIC2. (PB) */ |
| 365 | /* 0x1e002000 GIC3. (PB) */ |
| 366 | /* 0x1e003000 GIC4. (PB) */ |
| 367 | /* 0x40000000 NOR flash. */ |
| 368 | /* 0x44000000 DoC flash. */ |
| 369 | /* 0x48000000 SRAM. */ |
| 370 | /* 0x4c000000 Configuration flash. */ |
| 371 | /* 0x4e000000 Ethernet. */ |
| 372 | /* 0x4f000000 USB. */ |
| 373 | /* 0x50000000 PISMO. */ |
| 374 | /* 0x54000000 PISMO. */ |
| 375 | /* 0x58000000 PISMO. */ |
| 376 | /* 0x5c000000 PISMO. */ |
| 377 | /* 0x60000000 PCI. */ |
| 378 | /* 0x60000000 PCI Self Config. */ |
| 379 | /* 0x61000000 PCI Config. */ |
| 380 | /* 0x62000000 PCI IO. */ |
| 381 | /* 0x63000000 PCI mem 0. */ |
| 382 | /* 0x64000000 PCI mem 1. */ |
| 383 | /* 0x68000000 PCI mem 2. */ |
| 384 | |
| 385 | /* ??? Hack to map an additional page of ram for the secondary CPU |
| 386 | startup code. I guess this works on real hardware because the |
| 387 | BootROM happens to be in ROM/flash or in memory that isn't clobbered |
| 388 | until after Linux boots the secondary CPUs. */ |
| 389 | memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, |
| 390 | &error_fatal); |
| 391 | memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); |
| 392 | |
| 393 | rvms->bootinfo.smp_loader_start = SMP_BOOT_ADDR; |
| 394 | rvms->bootinfo.smp_bootreg_addr = SMP_BOOTREG_ADDR; |
| 395 | rvms->bootinfo.ram_size = ram_size; |
| 396 | rvms->bootinfo.board_id = realview_board_id[board_type]; |
| 397 | rvms->bootinfo.loader_start = board_type == BOARD_PB_A8 ? 0x70000000 : 0; |
| 398 | arm_load_kernel(cpu, machine, &rvms->bootinfo); |
| 399 | } |
| 400 | |
| 401 | static void realview_eb_init(MachineState *machine) |
| 402 | { |
| 403 | realview_init(machine, BOARD_EB); |
| 404 | } |
| 405 | |
| 406 | static void realview_eb_mpcore_init(MachineState *machine) |
| 407 | { |
| 408 | realview_init(machine, BOARD_EB_MPCORE); |
| 409 | } |
| 410 | |
| 411 | static void realview_pb_a8_init(MachineState *machine) |
| 412 | { |
| 413 | realview_init(machine, BOARD_PB_A8); |
| 414 | } |
| 415 | |
| 416 | static void realview_pbx_a9_init(MachineState *machine) |
| 417 | { |
| 418 | realview_init(machine, BOARD_PBX_A9); |
| 419 | } |
| 420 | |
| 421 | static void realview_eb_class_init(ObjectClass *oc, const void *data) |
| 422 | { |
| 423 | MachineClass *mc = MACHINE_CLASS(oc); |
| 424 | |
| 425 | mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)"; |
| 426 | mc->init = realview_eb_init; |
| 427 | mc->block_default_type = IF_SCSI; |
| 428 | mc->ignore_memory_transaction_failures = true; |
| 429 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
| 430 | mc->auto_create_sdcard = true; |
| 431 | |
| 432 | machine_add_audiodev_property(mc); |
| 433 | } |
| 434 | |
| 435 | static const TypeInfo realview_eb_type = { |
| 436 | .name = MACHINE_TYPE_NAME("realview-eb"), |
| 437 | .parent = TYPE_MACHINE, |
| 438 | .class_init = realview_eb_class_init, |
| 439 | .instance_size = sizeof(RealViewMachineState), |
| 440 | .interfaces = arm_machine_interfaces, |
| 441 | }; |
| 442 | |
| 443 | static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data) |
| 444 | { |
| 445 | MachineClass *mc = MACHINE_CLASS(oc); |
| 446 | |
| 447 | mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)"; |
| 448 | mc->init = realview_eb_mpcore_init; |
| 449 | mc->block_default_type = IF_SCSI; |
| 450 | mc->max_cpus = 4; |
| 451 | mc->ignore_memory_transaction_failures = true; |
| 452 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore"); |
| 453 | mc->auto_create_sdcard = true; |
| 454 | |
| 455 | machine_add_audiodev_property(mc); |
| 456 | } |
| 457 | |
| 458 | static const TypeInfo realview_eb_mpcore_type = { |
| 459 | .name = MACHINE_TYPE_NAME("realview-eb-mpcore"), |
| 460 | .parent = TYPE_MACHINE, |
| 461 | .class_init = realview_eb_mpcore_class_init, |
| 462 | .instance_size = sizeof(RealViewMachineState), |
| 463 | .interfaces = arm_machine_interfaces, |
| 464 | }; |
| 465 | |
| 466 | static void realview_pb_a8_class_init(ObjectClass *oc, const void *data) |
| 467 | { |
| 468 | MachineClass *mc = MACHINE_CLASS(oc); |
| 469 | |
| 470 | mc->desc = "ARM RealView Platform Baseboard for Cortex-A8"; |
| 471 | mc->init = realview_pb_a8_init; |
| 472 | mc->ignore_memory_transaction_failures = true; |
| 473 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8"); |
| 474 | mc->auto_create_sdcard = true; |
| 475 | |
| 476 | machine_add_audiodev_property(mc); |
| 477 | } |
| 478 | |
| 479 | static const TypeInfo realview_pb_a8_type = { |
| 480 | .name = MACHINE_TYPE_NAME("realview-pb-a8"), |
| 481 | .parent = TYPE_MACHINE, |
| 482 | .class_init = realview_pb_a8_class_init, |
| 483 | .instance_size = sizeof(RealViewMachineState), |
| 484 | .interfaces = arm_machine_interfaces, |
| 485 | }; |
| 486 | |
| 487 | static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data) |
| 488 | { |
| 489 | MachineClass *mc = MACHINE_CLASS(oc); |
| 490 | |
| 491 | mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9"; |
| 492 | mc->init = realview_pbx_a9_init; |
| 493 | mc->max_cpus = 4; |
| 494 | mc->ignore_memory_transaction_failures = true; |
| 495 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
| 496 | mc->auto_create_sdcard = true; |
| 497 | |
| 498 | machine_add_audiodev_property(mc); |
| 499 | } |
| 500 | |
| 501 | static const TypeInfo realview_pbx_a9_type = { |
| 502 | .name = MACHINE_TYPE_NAME("realview-pbx-a9"), |
| 503 | .parent = TYPE_MACHINE, |
| 504 | .class_init = realview_pbx_a9_class_init, |
| 505 | .instance_size = sizeof(RealViewMachineState), |
| 506 | .interfaces = arm_machine_interfaces, |
| 507 | }; |
| 508 | |
| 509 | static void realview_machine_init(void) |
| 510 | { |
| 511 | type_register_static(&realview_eb_type); |
| 512 | type_register_static(&realview_eb_mpcore_type); |
| 513 | type_register_static(&realview_pb_a8_type); |
| 514 | type_register_static(&realview_pbx_a9_type); |
| 515 | } |
| 516 | |
| 517 | type_init(realview_machine_init) |