@samitouri / QOSamiQemu
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1 /*
2 * SABRELITE Board System emulation.
3 *
4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5 *
6 * This code is licensed under the GPL, version 2 or later.
7 * See the file `COPYING' in the top level directory.
8 *
9 * It (partially) emulates a sabrelite board, with a Freescale
10 * i.MX6 SoC
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/arm/fsl-imx6.h"
16 #include "hw/arm/boot.h"
17 #include "hw/arm/machines-qom.h"
18 #include "hw/core/boards.h"
19 #include "hw/core/qdev-properties.h"
20 #include "qemu/error-report.h"
21 #include "system/qtest.h"
22
23 struct SabreliteMachineState {
24 MachineState parent_obj;
25
26 FslIMX6State soc;
27 CanBusState *canbus[FSL_IMX6_NUM_CANS];
28 struct arm_boot_info bootinfo;
29 };
30
31 #define TYPE_SABRELITE_MACHINE MACHINE_TYPE_NAME("sabrelite")
32 OBJECT_DECLARE_SIMPLE_TYPE(SabreliteMachineState, SABRELITE_MACHINE)
33
34 /* No need to do any particular setup for secondary boot */
35 static void sabrelite_write_secondary(ARMCPU *cpu,
36 const struct arm_boot_info *info)
37 {
38 }
39
40 /* Secondary cores are reset through SRC device */
41 static void sabrelite_reset_secondary(ARMCPU *cpu,
42 const struct arm_boot_info *info)
43 {
44 }
45
46 static void sabrelite_init(MachineState *machine)
47 {
48 SabreliteMachineState *s = SABRELITE_MACHINE(machine);
49
50 /* Check the amount of memory is compatible with the SOC */
51 if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
52 error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
53 machine->ram_size, FSL_IMX6_MMDC_SIZE);
54 exit(1);
55 }
56
57 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX6);
58
59 /* Ethernet PHY address is 6 */
60 object_property_set_int(OBJECT(&s->soc), "fec-phy-num", 6, &error_fatal);
61
62 for (int i = 0; i < FSL_IMX6_NUM_CANS; i++) {
63 g_autofree char *bus_name = g_strdup_printf("canbus%d", i);
64
65 object_property_set_link(OBJECT(&s->soc), bus_name,
66 OBJECT(s->canbus[i]), &error_fatal);
67 }
68
69 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
70
71 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
72 machine->ram);
73
74 {
75 /*
76 * TODO: Ideally we would expose the chip select and spi bus on the
77 * SoC object using alias properties; then we would not need to
78 * directly access the underlying spi device object.
79 */
80 /* Add the sst25vf016b NOR FLASH memory to first SPI */
81 Object *spi_dev;
82
83 spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
84 if (spi_dev) {
85 SSIBus *spi_bus;
86
87 spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
88 if (spi_bus) {
89 DeviceState *flash_dev;
90 qemu_irq cs_line;
91 DriveInfo *dinfo = drive_get(IF_MTD, 0, 0);
92
93 flash_dev = qdev_new("sst25vf016b");
94 if (dinfo) {
95 qdev_prop_set_drive_err(flash_dev, "drive",
96 blk_by_legacy_dinfo(dinfo),
97 &error_fatal);
98 }
99 qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
100
101 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
102 qdev_connect_gpio_out(DEVICE(&s->soc.gpio[2]), 19, cs_line);
103 }
104 }
105 }
106
107 /* DDR memory start */
108 s->bootinfo.loader_start = FSL_IMX6_MMDC_ADDR;
109 /* No board ID, we boot from DT tree */
110 s->bootinfo.board_id = -1;
111 s->bootinfo.ram_size = machine->ram_size;
112 s->bootinfo.secure_boot = true;
113 s->bootinfo.write_secondary_boot = sabrelite_write_secondary;
114 s->bootinfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
115
116 if (!qtest_enabled()) {
117 arm_load_kernel(&s->soc.cpu[0], machine, &s->bootinfo);
118 }
119 }
120
121 static void sabrelite_machine_instance_init(Object *obj)
122 {
123 SabreliteMachineState *s = SABRELITE_MACHINE(obj);
124
125 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
126 (Object **)&s->canbus[0],
127 object_property_allow_set_link,
128 0);
129
130 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
131 (Object **)&s->canbus[1],
132 object_property_allow_set_link,
133 0);
134 }
135
136 static void sabrelite_machine_class_init(ObjectClass *oc, const void *data)
137 {
138 MachineClass *mc = MACHINE_CLASS(oc);
139
140 mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex-A9)";
141 mc->init = sabrelite_init;
142 mc->max_cpus = FSL_IMX6_NUM_CPUS;
143 mc->ignore_memory_transaction_failures = true;
144 mc->default_ram_id = "sabrelite.ram";
145 mc->auto_create_sdcard = true;
146 }
147
148 static const TypeInfo sabrelite_machine_init_typeinfo = {
149 .name = TYPE_SABRELITE_MACHINE,
150 .parent = TYPE_MACHINE,
151 .class_init = sabrelite_machine_class_init,
152 .instance_init = sabrelite_machine_instance_init,
153 .instance_size = sizeof(SabreliteMachineState),
154 .abstract = false,
155 .interfaces = arm_machine_interfaces,
156 };
157
158 static void sabrelite_machine_init_register_types(void)
159 {
160 type_register_static(&sabrelite_machine_init_typeinfo);
161 }
162
163 type_init(sabrelite_machine_init_register_types)