| 1 | /* |
| 2 | * ARM SBSA Reference Platform emulation |
| 3 | * |
| 4 | * Copyright (c) 2018 Linaro Limited |
| 5 | * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. |
| 6 | * Written by Hongbo Zhang <hongbo.zhang@linaro.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2 or later, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/cutils.h" |
| 23 | #include "qemu/datadir.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "qemu/error-report.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "system/device_tree.h" |
| 28 | #include "system/kvm.h" |
| 29 | #include "system/numa.h" |
| 30 | #include "system/runstate.h" |
| 31 | #include "system/system.h" |
| 32 | #include "exec/hwaddr.h" |
| 33 | #include "kvm_arm.h" |
| 34 | #include "hw/arm/boot.h" |
| 35 | #include "hw/arm/bsa.h" |
| 36 | #include "hw/arm/fdt.h" |
| 37 | #include "hw/arm/smmuv3.h" |
| 38 | #include "hw/arm/machines-qom.h" |
| 39 | #include "hw/block/flash.h" |
| 40 | #include "hw/core/boards.h" |
| 41 | #include "hw/ide/ide-bus.h" |
| 42 | #include "hw/ide/ahci-sysbus.h" |
| 43 | #include "hw/intc/arm_gicv3_common.h" |
| 44 | #include "hw/intc/arm_gicv3_its_common.h" |
| 45 | #include "hw/core/loader.h" |
| 46 | #include "hw/pci-host/gpex.h" |
| 47 | #include "hw/core/qdev-properties.h" |
| 48 | #include "hw/usb/usb.h" |
| 49 | #include "hw/usb/xhci.h" |
| 50 | #include "hw/char/pl011.h" |
| 51 | #include "hw/watchdog/sbsa_gwdt.h" |
| 52 | #include "net/net.h" |
| 53 | #include "qobject/qlist.h" |
| 54 | #include "qom/object.h" |
| 55 | #include "target/arm/cpu.h" |
| 56 | #include "target/arm/cpu-qom.h" |
| 57 | #include "target/arm/gtimer.h" |
| 58 | |
| 59 | #define RAMLIMIT_BYTES (8 * TiB) |
| 60 | |
| 61 | #define NUM_IRQS 256 |
| 62 | #define NUM_SMMU_IRQS 4 |
| 63 | #define NUM_SATA_PORTS 6 |
| 64 | |
| 65 | /* |
| 66 | * Generic timer frequency in Hz (which drives both the CPU generic timers |
| 67 | * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware |
| 68 | * assumed 62.5MHz here. |
| 69 | * |
| 70 | * Starting with Armv8.6 CPU 1GHz timer frequency is mandated. |
| 71 | */ |
| 72 | #define SBSA_GTIMER_HZ 1000000000 |
| 73 | |
| 74 | enum { |
| 75 | SBSA_FLASH, |
| 76 | SBSA_MEM, |
| 77 | SBSA_CPUPERIPHS, |
| 78 | SBSA_GIC_DIST, |
| 79 | SBSA_GIC_REDIST, |
| 80 | SBSA_GIC_ITS, |
| 81 | SBSA_SECURE_EC, |
| 82 | SBSA_GWDT_WS0, |
| 83 | SBSA_GWDT_REFRESH, |
| 84 | SBSA_GWDT_CONTROL, |
| 85 | SBSA_SMMU, |
| 86 | SBSA_UART, |
| 87 | SBSA_RTC, |
| 88 | SBSA_PCIE, |
| 89 | SBSA_PCIE_MMIO, |
| 90 | SBSA_PCIE_MMIO_HIGH, |
| 91 | SBSA_PCIE_PIO, |
| 92 | SBSA_PCIE_ECAM, |
| 93 | SBSA_GPIO, |
| 94 | SBSA_SECURE_UART, |
| 95 | SBSA_SECURE_UART_MM, |
| 96 | SBSA_SECURE_MEM, |
| 97 | SBSA_AHCI, |
| 98 | SBSA_XHCI, |
| 99 | }; |
| 100 | |
| 101 | struct SBSAMachineState { |
| 102 | MachineState parent; |
| 103 | struct arm_boot_info bootinfo; |
| 104 | int smp_cpus; |
| 105 | void *fdt; |
| 106 | int fdt_size; |
| 107 | int psci_conduit; |
| 108 | DeviceState *gic; |
| 109 | PFlashCFI01 *flash[2]; |
| 110 | }; |
| 111 | |
| 112 | #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") |
| 113 | OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) |
| 114 | |
| 115 | static const MemMapEntry sbsa_ref_memmap[] = { |
| 116 | /* 512M boot ROM */ |
| 117 | [SBSA_FLASH] = { 0, 0x20000000 }, |
| 118 | /* 512M secure memory */ |
| 119 | [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, |
| 120 | /* Space reserved for CPU peripheral devices */ |
| 121 | [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, |
| 122 | [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, |
| 123 | [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, |
| 124 | [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 }, |
| 125 | [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, |
| 126 | [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, |
| 127 | [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, |
| 128 | [SBSA_UART] = { 0x60000000, 0x00001000 }, |
| 129 | [SBSA_RTC] = { 0x60010000, 0x00001000 }, |
| 130 | [SBSA_GPIO] = { 0x60020000, 0x00001000 }, |
| 131 | [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, |
| 132 | [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, |
| 133 | [SBSA_SMMU] = { 0x60050000, 0x00020000 }, |
| 134 | /* Space here reserved for more SMMUs */ |
| 135 | [SBSA_AHCI] = { 0x60100000, 0x00010000 }, |
| 136 | [SBSA_XHCI] = { 0x60110000, 0x00010000 }, |
| 137 | /* Space here reserved for other devices */ |
| 138 | [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, |
| 139 | /* 32-bit address PCIE MMIO space */ |
| 140 | [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, |
| 141 | /* 256M PCIE ECAM space */ |
| 142 | [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, |
| 143 | /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ |
| 144 | [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, |
| 145 | [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, |
| 146 | }; |
| 147 | |
| 148 | static const int sbsa_ref_irqmap[] = { |
| 149 | [SBSA_UART] = 1, |
| 150 | [SBSA_RTC] = 2, |
| 151 | [SBSA_PCIE] = 3, /* ... to 6 */ |
| 152 | [SBSA_GPIO] = 7, |
| 153 | [SBSA_SECURE_UART] = 8, |
| 154 | [SBSA_SECURE_UART_MM] = 9, |
| 155 | [SBSA_AHCI] = 10, |
| 156 | [SBSA_XHCI] = 11, |
| 157 | [SBSA_SMMU] = 12, /* ... to 15 */ |
| 158 | [SBSA_GWDT_WS0] = 16, |
| 159 | }; |
| 160 | |
| 161 | static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) |
| 162 | { |
| 163 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; |
| 164 | return arm_build_mp_affinity(idx, clustersz); |
| 165 | } |
| 166 | |
| 167 | static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) |
| 168 | { |
| 169 | const char *intc_nodename = "/intc"; |
| 170 | const char *its_nodename = "/intc/its"; |
| 171 | |
| 172 | qemu_fdt_add_subnode(sms->fdt, intc_nodename); |
| 173 | qemu_fdt_setprop_sized_cells(sms->fdt, intc_nodename, "reg", |
| 174 | 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, |
| 175 | 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, |
| 176 | 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, |
| 177 | 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); |
| 178 | |
| 179 | qemu_fdt_add_subnode(sms->fdt, its_nodename); |
| 180 | qemu_fdt_setprop_sized_cells(sms->fdt, its_nodename, "reg", |
| 181 | 2, sbsa_ref_memmap[SBSA_GIC_ITS].base, |
| 182 | 2, sbsa_ref_memmap[SBSA_GIC_ITS].size); |
| 183 | } |
| 184 | |
| 185 | /* |
| 186 | * Firmware on this machine only uses ACPI table to load OS, these limited |
| 187 | * device tree nodes are just to let firmware know the info which varies from |
| 188 | * command line parameters, so it is not necessary to be fully compatible |
| 189 | * with the kernel CPU and NUMA binding rules. |
| 190 | */ |
| 191 | static void create_fdt(SBSAMachineState *sms) |
| 192 | { |
| 193 | void *fdt = create_device_tree(&sms->fdt_size); |
| 194 | const MachineState *ms = MACHINE(sms); |
| 195 | int nb_numa_nodes = ms->numa_state->num_nodes; |
| 196 | int cpu; |
| 197 | |
| 198 | if (!fdt) { |
| 199 | error_report("create_device_tree() failed"); |
| 200 | exit(1); |
| 201 | } |
| 202 | |
| 203 | sms->fdt = fdt; |
| 204 | |
| 205 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); |
| 206 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); |
| 207 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
| 208 | |
| 209 | /* |
| 210 | * This versioning scheme is for informing platform fw only. It is neither: |
| 211 | * - A QEMU versioned machine type; a given version of QEMU will emulate |
| 212 | * a given version of the platform. |
| 213 | * - A reflection of level of SBSA (now SystemReady SR) support provided. |
| 214 | * |
| 215 | * machine-version-major: updated when changes breaking fw compatibility |
| 216 | * are introduced. |
| 217 | * machine-version-minor: updated when features are added that don't break |
| 218 | * fw compatibility. |
| 219 | */ |
| 220 | qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); |
| 221 | qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4); |
| 222 | |
| 223 | if (ms->numa_state->have_numa_distance) { |
| 224 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); |
| 225 | uint32_t *matrix = g_malloc0(size); |
| 226 | int idx, i, j; |
| 227 | |
| 228 | for (i = 0; i < nb_numa_nodes; i++) { |
| 229 | for (j = 0; j < nb_numa_nodes; j++) { |
| 230 | idx = (i * nb_numa_nodes + j) * 3; |
| 231 | matrix[idx + 0] = cpu_to_be32(i); |
| 232 | matrix[idx + 1] = cpu_to_be32(j); |
| 233 | matrix[idx + 2] = |
| 234 | cpu_to_be32(ms->numa_state->nodes[i].distance[j]); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | qemu_fdt_add_subnode(fdt, "/distance-map"); |
| 239 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", |
| 240 | matrix, size); |
| 241 | g_free(matrix); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * From Documentation/devicetree/bindings/arm/cpus.yaml |
| 246 | * On ARM v8 64-bit systems this property is required |
| 247 | * and matches the MPIDR_EL1 register affinity bits. |
| 248 | * |
| 249 | * * If cpus node's #address-cells property is set to 2 |
| 250 | * |
| 251 | * The first reg cell bits [7:0] must be set to |
| 252 | * bits [39:32] of MPIDR_EL1. |
| 253 | * |
| 254 | * The second reg cell bits [23:0] must be set to |
| 255 | * bits [23:0] of MPIDR_EL1. |
| 256 | */ |
| 257 | qemu_fdt_add_subnode(sms->fdt, "/cpus"); |
| 258 | qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); |
| 259 | qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); |
| 260 | |
| 261 | for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { |
| 262 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
| 263 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); |
| 264 | CPUState *cs = CPU(armcpu); |
| 265 | uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); |
| 266 | |
| 267 | qemu_fdt_add_subnode(sms->fdt, nodename); |
| 268 | qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); |
| 269 | |
| 270 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { |
| 271 | qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", |
| 272 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); |
| 273 | } |
| 274 | |
| 275 | g_free(nodename); |
| 276 | } |
| 277 | |
| 278 | /* Add CPU topology description through fdt node topology. */ |
| 279 | qemu_fdt_add_subnode(sms->fdt, "/cpus/topology"); |
| 280 | |
| 281 | qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets); |
| 282 | qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters); |
| 283 | qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores); |
| 284 | qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads); |
| 285 | |
| 286 | sbsa_fdt_add_gic_node(sms); |
| 287 | } |
| 288 | |
| 289 | #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) |
| 290 | |
| 291 | static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, |
| 292 | const char *name, |
| 293 | const char *alias_prop_name) |
| 294 | { |
| 295 | /* |
| 296 | * Create a single flash device. We use the same parameters as |
| 297 | * the flash devices on the Versatile Express board. |
| 298 | */ |
| 299 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 300 | |
| 301 | qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); |
| 302 | qdev_prop_set_uint8(dev, "width", 4); |
| 303 | qdev_prop_set_uint8(dev, "device-width", 2); |
| 304 | qdev_prop_set_bit(dev, "big-endian", false); |
| 305 | qdev_prop_set_uint16(dev, "id0", 0x89); |
| 306 | qdev_prop_set_uint16(dev, "id1", 0x18); |
| 307 | qdev_prop_set_uint16(dev, "id2", 0x00); |
| 308 | qdev_prop_set_uint16(dev, "id3", 0x00); |
| 309 | qdev_prop_set_string(dev, "name", name); |
| 310 | object_property_add_child(OBJECT(sms), name, OBJECT(dev)); |
| 311 | object_property_add_alias(OBJECT(sms), alias_prop_name, |
| 312 | OBJECT(dev), "drive"); |
| 313 | return PFLASH_CFI01(dev); |
| 314 | } |
| 315 | |
| 316 | static void sbsa_flash_create(SBSAMachineState *sms) |
| 317 | { |
| 318 | sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); |
| 319 | sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); |
| 320 | } |
| 321 | |
| 322 | static void sbsa_flash_map1(PFlashCFI01 *flash, |
| 323 | hwaddr base, hwaddr size, |
| 324 | MemoryRegion *sysmem) |
| 325 | { |
| 326 | DeviceState *dev = DEVICE(flash); |
| 327 | |
| 328 | assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); |
| 329 | assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); |
| 330 | qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); |
| 331 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 332 | |
| 333 | memory_region_add_subregion(sysmem, base, |
| 334 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), |
| 335 | 0)); |
| 336 | } |
| 337 | |
| 338 | static void sbsa_flash_map(SBSAMachineState *sms, |
| 339 | MemoryRegion *sysmem, |
| 340 | MemoryRegion *secure_sysmem) |
| 341 | { |
| 342 | /* |
| 343 | * Map two flash devices to fill the SBSA_FLASH space in the memmap. |
| 344 | * sysmem is the system memory space. secure_sysmem is the secure view |
| 345 | * of the system, and the first flash device should be made visible only |
| 346 | * there. The second flash device is visible to both secure and nonsecure. |
| 347 | */ |
| 348 | hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; |
| 349 | hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; |
| 350 | |
| 351 | sbsa_flash_map1(sms->flash[0], flashbase, flashsize, |
| 352 | secure_sysmem); |
| 353 | sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, |
| 354 | sysmem); |
| 355 | } |
| 356 | |
| 357 | static bool sbsa_firmware_init(SBSAMachineState *sms, |
| 358 | MemoryRegion *sysmem, |
| 359 | MemoryRegion *secure_sysmem) |
| 360 | { |
| 361 | const char *bios_name; |
| 362 | int i; |
| 363 | BlockBackend *pflash_blk0; |
| 364 | |
| 365 | /* Map legacy -drive if=pflash to machine properties */ |
| 366 | for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { |
| 367 | pflash_cfi01_legacy_drive(sms->flash[i], |
| 368 | drive_get(IF_PFLASH, 0, i)); |
| 369 | } |
| 370 | |
| 371 | sbsa_flash_map(sms, sysmem, secure_sysmem); |
| 372 | |
| 373 | pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); |
| 374 | |
| 375 | bios_name = MACHINE(sms)->firmware; |
| 376 | if (bios_name) { |
| 377 | char *fname; |
| 378 | MemoryRegion *mr; |
| 379 | int image_size; |
| 380 | |
| 381 | if (pflash_blk0) { |
| 382 | error_report("The contents of the first flash device may be " |
| 383 | "specified with -bios or with -drive if=pflash... " |
| 384 | "but you cannot use both options at once"); |
| 385 | exit(1); |
| 386 | } |
| 387 | |
| 388 | /* Fall back to -bios */ |
| 389 | |
| 390 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 391 | if (!fname) { |
| 392 | error_report("Could not find ROM image '%s'", bios_name); |
| 393 | exit(1); |
| 394 | } |
| 395 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); |
| 396 | image_size = load_image_mr(fname, mr); |
| 397 | g_free(fname); |
| 398 | if (image_size < 0) { |
| 399 | error_report("Could not load ROM image '%s'", bios_name); |
| 400 | exit(1); |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | return pflash_blk0 || bios_name; |
| 405 | } |
| 406 | |
| 407 | static void create_secure_ram(SBSAMachineState *sms, |
| 408 | MemoryRegion *secure_sysmem) |
| 409 | { |
| 410 | MemoryRegion *secram = g_new(MemoryRegion, 1); |
| 411 | hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; |
| 412 | hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; |
| 413 | |
| 414 | memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, |
| 415 | &error_fatal); |
| 416 | memory_region_add_subregion(secure_sysmem, base, secram); |
| 417 | } |
| 418 | |
| 419 | static void create_its(SBSAMachineState *sms) |
| 420 | { |
| 421 | const char *itsclass = its_class_name(); |
| 422 | DeviceState *dev; |
| 423 | |
| 424 | dev = qdev_new(itsclass); |
| 425 | |
| 426 | object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), |
| 427 | &error_abort); |
| 428 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 429 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base); |
| 430 | } |
| 431 | |
| 432 | static void create_gic(SBSAMachineState *sms, MemoryRegion *mem) |
| 433 | { |
| 434 | unsigned int smp_cpus = MACHINE(sms)->smp.cpus; |
| 435 | SysBusDevice *gicbusdev; |
| 436 | const char *gictype; |
| 437 | uint32_t redist0_capacity, redist0_count; |
| 438 | QList *redist_region_count; |
| 439 | int i; |
| 440 | |
| 441 | gictype = gicv3_class_name(); |
| 442 | |
| 443 | sms->gic = qdev_new(gictype); |
| 444 | qdev_prop_set_uint32(sms->gic, "revision", 3); |
| 445 | qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); |
| 446 | /* |
| 447 | * Note that the num-irq property counts both internal and external |
| 448 | * interrupts; there are always 32 of the former (mandated by GIC spec). |
| 449 | */ |
| 450 | qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); |
| 451 | qdev_prop_set_bit(sms->gic, "has-security-extensions", true); |
| 452 | |
| 453 | redist0_capacity = |
| 454 | sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; |
| 455 | redist0_count = MIN(smp_cpus, redist0_capacity); |
| 456 | |
| 457 | redist_region_count = qlist_new(); |
| 458 | qlist_append_int(redist_region_count, redist0_count); |
| 459 | qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); |
| 460 | |
| 461 | object_property_set_link(OBJECT(sms->gic), "sysmem", |
| 462 | OBJECT(mem), &error_fatal); |
| 463 | qdev_prop_set_bit(sms->gic, "has-lpi", true); |
| 464 | |
| 465 | gicbusdev = SYS_BUS_DEVICE(sms->gic); |
| 466 | sysbus_realize_and_unref(gicbusdev, &error_fatal); |
| 467 | sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); |
| 468 | sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); |
| 469 | |
| 470 | /* |
| 471 | * Wire the outputs from each CPU's generic timer and the GICv3 |
| 472 | * maintenance interrupt signal to the appropriate GIC PPI inputs, |
| 473 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. |
| 474 | */ |
| 475 | for (i = 0; i < smp_cpus; i++) { |
| 476 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); |
| 477 | int intidbase = NUM_IRQS + i * GIC_INTERNAL; |
| 478 | int irq; |
| 479 | /* |
| 480 | * Mapping from the output timer irq lines from the CPU to the |
| 481 | * GIC PPI inputs used for this board. |
| 482 | */ |
| 483 | const int timer_irq[] = { |
| 484 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, |
| 485 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, |
| 486 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, |
| 487 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, |
| 488 | [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, |
| 489 | [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ, |
| 490 | [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ, |
| 491 | }; |
| 492 | |
| 493 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { |
| 494 | qdev_connect_gpio_out(cpudev, irq, |
| 495 | qdev_get_gpio_in(sms->gic, |
| 496 | intidbase + timer_irq[irq])); |
| 497 | } |
| 498 | |
| 499 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, |
| 500 | qdev_get_gpio_in(sms->gic, |
| 501 | intidbase |
| 502 | + ARCH_GIC_MAINT_IRQ)); |
| 503 | |
| 504 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, |
| 505 | qdev_get_gpio_in(sms->gic, |
| 506 | intidbase |
| 507 | + VIRTUAL_PMU_IRQ)); |
| 508 | |
| 509 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
| 510 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
| 511 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); |
| 512 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, |
| 513 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); |
| 514 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, |
| 515 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); |
| 516 | } |
| 517 | create_its(sms); |
| 518 | } |
| 519 | |
| 520 | static void create_uart(const SBSAMachineState *sms, int uart, |
| 521 | MemoryRegion *mem, Chardev *chr) |
| 522 | { |
| 523 | hwaddr base = sbsa_ref_memmap[uart].base; |
| 524 | int irq = sbsa_ref_irqmap[uart]; |
| 525 | DeviceState *dev = qdev_new(TYPE_PL011); |
| 526 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
| 527 | |
| 528 | qdev_prop_set_chr(dev, "chardev", chr); |
| 529 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 530 | memory_region_add_subregion(mem, base, |
| 531 | sysbus_mmio_get_region(s, 0)); |
| 532 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); |
| 533 | } |
| 534 | |
| 535 | static void create_rtc(const SBSAMachineState *sms) |
| 536 | { |
| 537 | hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; |
| 538 | int irq = sbsa_ref_irqmap[SBSA_RTC]; |
| 539 | |
| 540 | sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); |
| 541 | } |
| 542 | |
| 543 | static void create_wdt(const SBSAMachineState *sms) |
| 544 | { |
| 545 | hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; |
| 546 | hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; |
| 547 | DeviceState *dev = qdev_new(TYPE_WDT_SBSA); |
| 548 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
| 549 | int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; |
| 550 | |
| 551 | qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); |
| 552 | sysbus_realize_and_unref(s, &error_fatal); |
| 553 | sysbus_mmio_map(s, 0, rbase); |
| 554 | sysbus_mmio_map(s, 1, cbase); |
| 555 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); |
| 556 | } |
| 557 | |
| 558 | static DeviceState *gpio_key_dev; |
| 559 | static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) |
| 560 | { |
| 561 | /* use gpio Pin 3 for power button event */ |
| 562 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
| 563 | } |
| 564 | |
| 565 | static Notifier sbsa_ref_powerdown_notifier = { |
| 566 | .notify = sbsa_ref_powerdown_req |
| 567 | }; |
| 568 | |
| 569 | static void create_gpio(const SBSAMachineState *sms) |
| 570 | { |
| 571 | DeviceState *pl061_dev; |
| 572 | hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; |
| 573 | int irq = sbsa_ref_irqmap[SBSA_GPIO]; |
| 574 | |
| 575 | pl061_dev = sysbus_create_simple("pl061", base, |
| 576 | qdev_get_gpio_in(sms->gic, irq)); |
| 577 | |
| 578 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
| 579 | qdev_get_gpio_in(pl061_dev, 3)); |
| 580 | |
| 581 | /* connect powerdown request */ |
| 582 | qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); |
| 583 | } |
| 584 | |
| 585 | static void create_ahci(const SBSAMachineState *sms) |
| 586 | { |
| 587 | hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; |
| 588 | int irq = sbsa_ref_irqmap[SBSA_AHCI]; |
| 589 | DeviceState *dev; |
| 590 | DriveInfo *hd[NUM_SATA_PORTS]; |
| 591 | SysbusAHCIState *sysahci; |
| 592 | |
| 593 | dev = qdev_new("sysbus-ahci"); |
| 594 | qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); |
| 595 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 596 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 597 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); |
| 598 | |
| 599 | sysahci = SYSBUS_AHCI(dev); |
| 600 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
| 601 | ahci_ide_create_devs(&sysahci->ahci, hd); |
| 602 | } |
| 603 | |
| 604 | static void create_xhci(const SBSAMachineState *sms) |
| 605 | { |
| 606 | hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; |
| 607 | int irq = sbsa_ref_irqmap[SBSA_XHCI]; |
| 608 | DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); |
| 609 | qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); |
| 610 | |
| 611 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 612 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 613 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); |
| 614 | } |
| 615 | |
| 616 | static void create_smmu(const SBSAMachineState *sms, PCIBus *bus, |
| 617 | MemoryRegion *sysmem, |
| 618 | MemoryRegion *secure_sysmem) |
| 619 | { |
| 620 | hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; |
| 621 | int irq = sbsa_ref_irqmap[SBSA_SMMU]; |
| 622 | DeviceState *dev; |
| 623 | int i; |
| 624 | |
| 625 | dev = qdev_new(TYPE_ARM_SMMUV3); |
| 626 | |
| 627 | object_property_set_str(OBJECT(dev), "stage", "nested", &error_abort); |
| 628 | object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), |
| 629 | &error_abort); |
| 630 | object_property_set_link(OBJECT(dev), "memory", OBJECT(sysmem), |
| 631 | &error_abort); |
| 632 | object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(secure_sysmem), |
| 633 | &error_abort); |
| 634 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 635 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 636 | for (i = 0; i < NUM_SMMU_IRQS; i++) { |
| 637 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
| 638 | qdev_get_gpio_in(sms->gic, irq + i)); |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | static void create_pcie(SBSAMachineState *sms, |
| 643 | MemoryRegion *sysmem, |
| 644 | MemoryRegion *secure_sysmem) |
| 645 | { |
| 646 | hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; |
| 647 | hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; |
| 648 | hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; |
| 649 | hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; |
| 650 | hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; |
| 651 | hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; |
| 652 | hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; |
| 653 | int irq = sbsa_ref_irqmap[SBSA_PCIE]; |
| 654 | MachineClass *mc = MACHINE_GET_CLASS(sms); |
| 655 | MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; |
| 656 | MemoryRegion *ecam_alias, *ecam_reg; |
| 657 | DeviceState *dev; |
| 658 | PCIHostState *pci; |
| 659 | int i; |
| 660 | |
| 661 | dev = qdev_new(TYPE_GPEX_HOST); |
| 662 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 663 | |
| 664 | /* Map ECAM space */ |
| 665 | ecam_alias = g_new0(MemoryRegion, 1); |
| 666 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
| 667 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", |
| 668 | ecam_reg, 0, size_ecam); |
| 669 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); |
| 670 | |
| 671 | /* Map the MMIO space */ |
| 672 | mmio_alias = g_new0(MemoryRegion, 1); |
| 673 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); |
| 674 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", |
| 675 | mmio_reg, base_mmio, size_mmio); |
| 676 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); |
| 677 | |
| 678 | /* Map the MMIO_HIGH space */ |
| 679 | mmio_alias_high = g_new0(MemoryRegion, 1); |
| 680 | memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", |
| 681 | mmio_reg, base_mmio_high, size_mmio_high); |
| 682 | memory_region_add_subregion(get_system_memory(), base_mmio_high, |
| 683 | mmio_alias_high); |
| 684 | |
| 685 | /* Map IO port space */ |
| 686 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
| 687 | |
| 688 | for (i = 0; i < PCI_NUM_PINS; i++) { |
| 689 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
| 690 | qdev_get_gpio_in(sms->gic, irq + i)); |
| 691 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
| 692 | } |
| 693 | |
| 694 | pci = PCI_HOST_BRIDGE(dev); |
| 695 | |
| 696 | pci_init_nic_devices(pci->bus, mc->default_nic); |
| 697 | |
| 698 | pci_create_simple(pci->bus, -1, "bochs-display"); |
| 699 | |
| 700 | create_smmu(sms, pci->bus, sysmem, secure_sysmem); |
| 701 | } |
| 702 | |
| 703 | static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
| 704 | { |
| 705 | const SBSAMachineState *board = container_of(binfo, SBSAMachineState, |
| 706 | bootinfo); |
| 707 | |
| 708 | *fdt_size = board->fdt_size; |
| 709 | return board->fdt; |
| 710 | } |
| 711 | |
| 712 | static void create_secure_ec(MemoryRegion *mem) |
| 713 | { |
| 714 | hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; |
| 715 | DeviceState *dev = qdev_new("sbsa-ec"); |
| 716 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
| 717 | |
| 718 | memory_region_add_subregion(mem, base, |
| 719 | sysbus_mmio_get_region(s, 0)); |
| 720 | } |
| 721 | |
| 722 | static void sbsa_ref_init(MachineState *machine) |
| 723 | { |
| 724 | unsigned int smp_cpus = machine->smp.cpus; |
| 725 | unsigned int max_cpus = machine->smp.max_cpus; |
| 726 | SBSAMachineState *sms = SBSA_MACHINE(machine); |
| 727 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 728 | MemoryRegion *sysmem = get_system_memory(); |
| 729 | MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); |
| 730 | bool firmware_loaded; |
| 731 | const CPUArchIdList *possible_cpus; |
| 732 | int n, sbsa_max_cpus; |
| 733 | |
| 734 | if (kvm_enabled()) { |
| 735 | error_report("sbsa-ref: KVM is not supported for this machine"); |
| 736 | exit(1); |
| 737 | } |
| 738 | |
| 739 | /* |
| 740 | * The Secure view of the world is the same as the NonSecure, |
| 741 | * but with a few extra devices. Create it as a container region |
| 742 | * containing the system memory at low priority; any secure-only |
| 743 | * devices go in at higher priority and take precedence. |
| 744 | */ |
| 745 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", |
| 746 | UINT64_MAX); |
| 747 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); |
| 748 | |
| 749 | firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); |
| 750 | |
| 751 | /* |
| 752 | * This machine has EL3 enabled, external firmware should supply PSCI |
| 753 | * implementation, so the QEMU's internal PSCI is disabled. |
| 754 | */ |
| 755 | sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; |
| 756 | |
| 757 | sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; |
| 758 | |
| 759 | if (max_cpus > sbsa_max_cpus) { |
| 760 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
| 761 | "supported by machine 'sbsa-ref' (%d)", |
| 762 | max_cpus, sbsa_max_cpus); |
| 763 | exit(1); |
| 764 | } |
| 765 | |
| 766 | sms->smp_cpus = smp_cpus; |
| 767 | |
| 768 | if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { |
| 769 | char *size_str = size_to_str(RAMLIMIT_BYTES); |
| 770 | |
| 771 | error_report("sbsa-ref: cannot model more than %s of RAM", size_str); |
| 772 | exit(1); |
| 773 | } |
| 774 | |
| 775 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
| 776 | for (n = 0; n < possible_cpus->len; n++) { |
| 777 | Object *cpuobj; |
| 778 | CPUState *cs; |
| 779 | |
| 780 | if (n >= smp_cpus) { |
| 781 | break; |
| 782 | } |
| 783 | |
| 784 | cpuobj = object_new(possible_cpus->cpus[n].type); |
| 785 | object_property_set_int(cpuobj, "mp-affinity", |
| 786 | possible_cpus->cpus[n].arch_id, NULL); |
| 787 | |
| 788 | cs = CPU(cpuobj); |
| 789 | cs->cpu_index = n; |
| 790 | |
| 791 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), |
| 792 | &error_fatal); |
| 793 | |
| 794 | if (object_property_find(cpuobj, "reset-cbar")) { |
| 795 | object_property_set_int(cpuobj, "reset-cbar", |
| 796 | sbsa_ref_memmap[SBSA_CPUPERIPHS].base, |
| 797 | &error_abort); |
| 798 | } |
| 799 | |
| 800 | object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort); |
| 801 | |
| 802 | object_property_set_link(cpuobj, "memory", OBJECT(sysmem), |
| 803 | &error_abort); |
| 804 | |
| 805 | object_property_set_link(cpuobj, "secure-memory", |
| 806 | OBJECT(secure_sysmem), &error_abort); |
| 807 | |
| 808 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
| 809 | object_unref(cpuobj); |
| 810 | } |
| 811 | |
| 812 | memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, |
| 813 | machine->ram); |
| 814 | |
| 815 | create_fdt(sms); |
| 816 | |
| 817 | create_secure_ram(sms, secure_sysmem); |
| 818 | |
| 819 | create_gic(sms, sysmem); |
| 820 | |
| 821 | create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); |
| 822 | create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); |
| 823 | /* Second secure UART for RAS and MM from EL0 */ |
| 824 | create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); |
| 825 | |
| 826 | create_rtc(sms); |
| 827 | |
| 828 | create_wdt(sms); |
| 829 | |
| 830 | create_gpio(sms); |
| 831 | |
| 832 | create_ahci(sms); |
| 833 | |
| 834 | create_xhci(sms); |
| 835 | |
| 836 | create_pcie(sms, sysmem, secure_sysmem); |
| 837 | |
| 838 | create_secure_ec(secure_sysmem); |
| 839 | |
| 840 | sms->bootinfo.ram_size = machine->ram_size; |
| 841 | sms->bootinfo.board_id = -1; |
| 842 | sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; |
| 843 | sms->bootinfo.get_dtb = sbsa_ref_dtb; |
| 844 | sms->bootinfo.firmware_loaded = firmware_loaded; |
| 845 | arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); |
| 846 | } |
| 847 | |
| 848 | static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) |
| 849 | { |
| 850 | unsigned int max_cpus = ms->smp.max_cpus; |
| 851 | SBSAMachineState *sms = SBSA_MACHINE(ms); |
| 852 | int n; |
| 853 | |
| 854 | if (ms->possible_cpus) { |
| 855 | assert(ms->possible_cpus->len == max_cpus); |
| 856 | return ms->possible_cpus; |
| 857 | } |
| 858 | |
| 859 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
| 860 | sizeof(CPUArchId) * max_cpus); |
| 861 | ms->possible_cpus->len = max_cpus; |
| 862 | for (n = 0; n < ms->possible_cpus->len; n++) { |
| 863 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
| 864 | ms->possible_cpus->cpus[n].arch_id = |
| 865 | sbsa_ref_cpu_mp_affinity(sms, n); |
| 866 | ms->possible_cpus->cpus[n].props.has_thread_id = true; |
| 867 | ms->possible_cpus->cpus[n].props.thread_id = n; |
| 868 | } |
| 869 | return ms->possible_cpus; |
| 870 | } |
| 871 | |
| 872 | static CpuInstanceProperties |
| 873 | sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) |
| 874 | { |
| 875 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
| 876 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); |
| 877 | |
| 878 | assert(cpu_index < possible_cpus->len); |
| 879 | return possible_cpus->cpus[cpu_index].props; |
| 880 | } |
| 881 | |
| 882 | static int64_t |
| 883 | sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) |
| 884 | { |
| 885 | return idx % ms->numa_state->num_nodes; |
| 886 | } |
| 887 | |
| 888 | static void sbsa_ref_instance_init(Object *obj) |
| 889 | { |
| 890 | SBSAMachineState *sms = SBSA_MACHINE(obj); |
| 891 | |
| 892 | sbsa_flash_create(sms); |
| 893 | } |
| 894 | |
| 895 | static void sbsa_ref_instance_finalize(Object *obj) |
| 896 | { |
| 897 | SBSAMachineState *sms = SBSA_MACHINE(obj); |
| 898 | |
| 899 | for (int i = 0; i < ARRAY_SIZE(sms->flash); i++) { |
| 900 | if (sms->flash[i] && !qdev_is_realized(DEVICE(sms->flash[i]))) { |
| 901 | object_unref(OBJECT(sms->flash[i])); |
| 902 | } |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | static void sbsa_ref_class_init(ObjectClass *oc, const void *data) |
| 907 | { |
| 908 | MachineClass *mc = MACHINE_CLASS(oc); |
| 909 | static const char * const valid_cpu_types[] = { |
| 910 | ARM_CPU_TYPE_NAME("cortex-a57"), |
| 911 | ARM_CPU_TYPE_NAME("cortex-a72"), |
| 912 | ARM_CPU_TYPE_NAME("neoverse-n1"), |
| 913 | ARM_CPU_TYPE_NAME("neoverse-v1"), |
| 914 | ARM_CPU_TYPE_NAME("neoverse-n2"), |
| 915 | ARM_CPU_TYPE_NAME("max"), |
| 916 | ARM_CPU_TYPE_NAME("max-v8"), |
| 917 | ARM_CPU_TYPE_NAME("max-v9"), |
| 918 | NULL, |
| 919 | }; |
| 920 | |
| 921 | mc->init = sbsa_ref_init; |
| 922 | mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; |
| 923 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2"); |
| 924 | mc->valid_cpu_types = valid_cpu_types; |
| 925 | mc->max_cpus = 512; |
| 926 | mc->pci_allow_0_address = true; |
| 927 | mc->minimum_page_bits = 12; |
| 928 | mc->block_default_type = IF_IDE; |
| 929 | mc->no_cdrom = 1; |
| 930 | mc->default_nic = "e1000e"; |
| 931 | mc->default_ram_size = 1 * GiB; |
| 932 | mc->default_ram_id = "sbsa-ref.ram"; |
| 933 | mc->default_cpus = 4; |
| 934 | mc->smp_props.clusters_supported = true; |
| 935 | mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; |
| 936 | mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; |
| 937 | mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; |
| 938 | /* platform instead of architectural choice */ |
| 939 | mc->cpu_cluster_has_numa_boundary = true; |
| 940 | } |
| 941 | |
| 942 | static const TypeInfo sbsa_ref_info = { |
| 943 | .name = TYPE_SBSA_MACHINE, |
| 944 | .parent = TYPE_MACHINE, |
| 945 | .instance_init = sbsa_ref_instance_init, |
| 946 | .instance_finalize = sbsa_ref_instance_finalize, |
| 947 | .class_init = sbsa_ref_class_init, |
| 948 | .instance_size = sizeof(SBSAMachineState), |
| 949 | .interfaces = aarch64_machine_interfaces, |
| 950 | }; |
| 951 | |
| 952 | static void sbsa_ref_machine_init(void) |
| 953 | { |
| 954 | type_register_static(&sbsa_ref_info); |
| 955 | } |
| 956 | |
| 957 | type_init(sbsa_ref_machine_init); |