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1 /*
2 * ARM SMMUv3 support - Internal API
3 *
4 * Copyright (C) 2014-2016 Broadcom Corporation
5 * Copyright (c) 2017 Red Hat, Inc.
6 * Written by Prem Mallappa, Eric Auger
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef HW_ARM_SMMUV3_INTERNAL_H
22 #define HW_ARM_SMMUV3_INTERNAL_H
23
24 #include "hw/core/registerfields.h"
25 #include "hw/arm/smmu-common.h"
26 #include "hw/arm/smmuv3-common.h"
27
28 typedef enum SMMUTranslationStatus {
29 SMMU_TRANS_DISABLE,
30 SMMU_TRANS_ABORT,
31 SMMU_TRANS_BYPASS,
32 SMMU_TRANS_ERROR,
33 SMMU_TRANS_SUCCESS,
34 } SMMUTranslationStatus;
35
36 typedef enum SMMUTranslationClass {
37 SMMU_CLASS_CD,
38 SMMU_CLASS_TT,
39 SMMU_CLASS_IN,
40 } SMMUTranslationClass;
41
42 static inline int smmu_enabled(SMMUv3State *s)
43 {
44 return FIELD_EX32(s->cr[0], CR0, SMMUEN);
45 }
46
47 /* Command Queue Entry */
48 typedef struct Cmd {
49 uint32_t word[4];
50 } Cmd;
51
52 /* Event Queue Entry */
53 typedef struct Evt {
54 uint32_t word[8];
55 } Evt;
56
57 static inline uint32_t smmuv3_idreg(int regoffset)
58 {
59 /*
60 * Return the value of the Primecell/Corelink ID registers at the
61 * specified offset from the first ID register.
62 * These value indicate an ARM implementation of MMU600 p1
63 */
64 static const uint8_t smmuv3_ids[] = {
65 0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
66 };
67 return smmuv3_ids[regoffset / 4];
68 }
69
70 static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
71 {
72 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
73 }
74
75 static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
76 {
77 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
78 }
79
80 /* Queue Handling */
81
82 #define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
83 #define WRAP_MASK(q) (1 << (q)->log2size)
84 #define INDEX_MASK(q) (((1 << (q)->log2size)) - 1)
85 #define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
86
87 #define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
88 #define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
89
90 #define Q_CONS_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
91 #define Q_PROD_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_PROD(q))
92
93 #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
94 #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)
95
96 static inline bool smmuv3_q_full(SMMUQueue *q)
97 {
98 return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
99 }
100
101 static inline bool smmuv3_q_empty(SMMUQueue *q)
102 {
103 return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
104 }
105
106 static inline void queue_prod_incr(SMMUQueue *q)
107 {
108 q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
109 }
110
111 static inline void queue_cons_incr(SMMUQueue *q)
112 {
113 /*
114 * We have to use deposit for the CONS registers to preserve
115 * the ERR field in the high bits.
116 */
117 q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
118 }
119
120 static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
121 {
122 return FIELD_EX32(s->cr[0], CR0, CMDQEN);
123 }
124
125 static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
126 {
127 return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
128 }
129
130 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
131 {
132 s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
133 }
134
135 static const char *cmd_stringify[] = {
136 [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
137 [SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR",
138 [SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE",
139 [SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE",
140 [SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD",
141 [SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL",
142 [SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL",
143 [SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL",
144 [SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID",
145 [SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA",
146 [SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA",
147 [SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL",
148 [SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA",
149 [SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL",
150 [SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID",
151 [SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA",
152 [SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA",
153 [SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL",
154 [SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA",
155 [SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL",
156 [SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV",
157 [SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP",
158 [SMMU_CMD_RESUME] = "SMMU_CMD_RESUME",
159 [SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM",
160 [SMMU_CMD_SYNC] = "SMMU_CMD_SYNC",
161 };
162
163 static inline const char *smmu_cmd_string(SMMUCommandType type)
164 {
165 if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
166 return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
167 } else {
168 return "INVALID";
169 }
170 }
171
172 /* CMDQ fields */
173
174 typedef enum {
175 SMMU_CERROR_NONE = 0,
176 SMMU_CERROR_ILL,
177 SMMU_CERROR_ABT,
178 SMMU_CERROR_ATC_INV_SYNC,
179 } SMMUCmdError;
180
181 enum { /* Command completion notification */
182 CMD_SYNC_SIG_NONE,
183 CMD_SYNC_SIG_IRQ,
184 CMD_SYNC_SIG_SEV,
185 };
186
187 #define CMD_TYPE(x) extract32((x)->word[0], 0 , 8)
188 #define CMD_NUM(x) extract32((x)->word[0], 12 , 5)
189 #define CMD_SCALE(x) extract32((x)->word[0], 20 , 5)
190 #define CMD_SSEC(x) extract32((x)->word[0], 10, 1)
191 #define CMD_SSV(x) extract32((x)->word[0], 11, 1)
192 #define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1)
193 #define CMD_RESUME_AB(x) extract32((x)->word[0], 13, 1)
194 #define CMD_SYNC_CS(x) extract32((x)->word[0], 12, 2)
195 #define CMD_SSID(x) extract32((x)->word[0], 12, 20)
196 #define CMD_SID(x) ((x)->word[1])
197 #define CMD_VMID(x) extract32((x)->word[1], 0 , 16)
198 #define CMD_ASID(x) extract32((x)->word[1], 16, 16)
199 #define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16)
200 #define CMD_RESP(x) extract32((x)->word[2], 11, 2)
201 #define CMD_LEAF(x) extract32((x)->word[2], 0 , 1)
202 #define CMD_TTL(x) extract32((x)->word[2], 8 , 2)
203 #define CMD_TG(x) extract32((x)->word[2], 10, 2)
204 #define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5)
205 #define CMD_ADDR(x) \
206 (((uint64_t)((x)->word[3]) << 32) | \
207 ((extract64((x)->word[2], 12, 20)) << 12))
208
209 #define SMMU_FEATURE_2LVL_STE (1 << 0)
210
211 /* Events */
212
213 typedef enum SMMUEventType {
214 SMMU_EVT_NONE = 0x00,
215 SMMU_EVT_F_UUT ,
216 SMMU_EVT_C_BAD_STREAMID ,
217 SMMU_EVT_F_STE_FETCH ,
218 SMMU_EVT_C_BAD_STE ,
219 SMMU_EVT_F_BAD_ATS_TREQ ,
220 SMMU_EVT_F_STREAM_DISABLED ,
221 SMMU_EVT_F_TRANS_FORBIDDEN ,
222 SMMU_EVT_C_BAD_SUBSTREAMID ,
223 SMMU_EVT_F_CD_FETCH ,
224 SMMU_EVT_C_BAD_CD ,
225 SMMU_EVT_F_WALK_EABT ,
226 SMMU_EVT_F_TRANSLATION = 0x10,
227 SMMU_EVT_F_ADDR_SIZE ,
228 SMMU_EVT_F_ACCESS ,
229 SMMU_EVT_F_PERMISSION ,
230 SMMU_EVT_F_TLB_CONFLICT = 0x20,
231 SMMU_EVT_F_CFG_CONFLICT ,
232 SMMU_EVT_E_PAGE_REQ = 0x24,
233 } SMMUEventType;
234
235 static const char *event_stringify[] = {
236 [SMMU_EVT_NONE] = "no recorded event",
237 [SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT",
238 [SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID",
239 [SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH",
240 [SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE",
241 [SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ",
242 [SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED",
243 [SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN",
244 [SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID",
245 [SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH",
246 [SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD",
247 [SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT",
248 [SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION",
249 [SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE",
250 [SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS",
251 [SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION",
252 [SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT",
253 [SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT",
254 [SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ",
255 };
256
257 static inline const char *smmu_event_string(SMMUEventType type)
258 {
259 if (type < ARRAY_SIZE(event_stringify)) {
260 return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
261 } else {
262 return "INVALID";
263 }
264 }
265
266 /* Encode an event record */
267 typedef struct SMMUEventInfo {
268 SMMUEventType type;
269 uint32_t sid;
270 bool recorded;
271 bool inval_ste_allowed;
272 union {
273 struct {
274 uint32_t ssid;
275 bool ssv;
276 dma_addr_t addr;
277 bool rnw;
278 bool pnu;
279 bool ind;
280 } f_uut;
281 struct SSIDInfo {
282 uint32_t ssid;
283 bool ssv;
284 } c_bad_streamid;
285 struct SSIDAddrInfo {
286 uint32_t ssid;
287 bool ssv;
288 dma_addr_t addr;
289 } f_ste_fetch;
290 struct SSIDInfo c_bad_ste;
291 struct {
292 dma_addr_t addr;
293 bool rnw;
294 } f_transl_forbidden;
295 struct {
296 uint32_t ssid;
297 } c_bad_substream;
298 struct SSIDAddrInfo f_cd_fetch;
299 struct SSIDInfo c_bad_cd;
300 struct FullInfo {
301 bool stall;
302 uint16_t stag;
303 uint32_t ssid;
304 bool ssv;
305 bool s2;
306 dma_addr_t addr;
307 bool rnw;
308 bool pnu;
309 bool ind;
310 uint8_t class;
311 dma_addr_t addr2;
312 } f_walk_eabt;
313 struct FullInfo f_translation;
314 struct FullInfo f_addr_size;
315 struct FullInfo f_access;
316 struct FullInfo f_permission;
317 struct SSIDInfo f_cfg_conflict;
318 /**
319 * not supported yet:
320 * F_BAD_ATS_TREQ
321 * F_BAD_ATS_TREQ
322 * F_TLB_CONFLICT
323 * E_PAGE_REQUEST
324 * IMPDEF_EVENTn
325 */
326 } u;
327 } SMMUEventInfo;
328
329 /* EVTQ fields */
330
331 #define EVT_Q_OVERFLOW (1 << 31)
332
333 #define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
334 #define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
335 #define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
336 #define EVT_SET_SID(x, v) ((x)->word[1] = v)
337 #define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
338 #define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
339 #define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
340 #define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
341 #define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
342 #define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
343 #define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
344 #define EVT_SET_ADDR(x, addr) \
345 do { \
346 (x)->word[5] = (uint32_t)(addr >> 32); \
347 (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
348 } while (0)
349 #define EVT_SET_ADDR2(x, addr) \
350 do { \
351 (x)->word[7] = (uint32_t)(addr >> 32); \
352 (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
353 } while (0)
354
355 #define EVT_GET_TYPE(x) extract32((x)->word[0], 0, 8)
356 #define EVT_GET_SID(x) ((x)->word[1])
357
358 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
359 void smmuv3_propagate_event(SMMUv3State *s, Evt *evt);
360 int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event);
361
362 #define STE_SIZE 6
363 #define L1STD_SIZE 3
364
365 static inline int oas2bits(int oas_field)
366 {
367 switch (oas_field) {
368 case 0:
369 return 32;
370 case 1:
371 return 36;
372 case 2:
373 return 40;
374 case 3:
375 return 42;
376 case 4:
377 return 44;
378 case 5:
379 return 48;
380 }
381
382 g_assert_not_reached();
383 }
384
385 /**
386 * tg2granule - Decodes the CD translation granule size field according
387 * to the ttbr in use
388 * @bits: TG0/1 fields
389 * @ttbr: ttbr index in use
390 */
391 static inline int tg2granule(int bits, int ttbr)
392 {
393 switch (bits) {
394 case 0:
395 return ttbr ? 0 : 12;
396 case 1:
397 return ttbr ? 14 : 16;
398 case 2:
399 return ttbr ? 12 : 14;
400 case 3:
401 return ttbr ? 16 : 0;
402 default:
403 return 0;
404 }
405 }
406
407 static inline uint64_t l1std_l2ptr(STEDesc *desc)
408 {
409 uint64_t hi, lo;
410
411 hi = desc->word[1];
412 lo = desc->word[0] & ~0x1fULL;
413 return hi << 32 | lo;
414 }
415
416 #define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
417
418 #endif