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1 /*
2 * Luminary Micro Stellaris peripherals
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/bitops.h"
12 #include "qapi/error.h"
13 #include "hw/core/split-irq.h"
14 #include "hw/core/sysbus.h"
15 #include "hw/sd/sd.h"
16 #include "hw/ssi/ssi.h"
17 #include "hw/arm/boot.h"
18 #include "hw/arm/machines-qom.h"
19 #include "qemu/timer.h"
20 #include "hw/i2c/i2c.h"
21 #include "net/net.h"
22 #include "hw/core/boards.h"
23 #include "qemu/log.h"
24 #include "system/address-spaces.h"
25 #include "system/system.h"
26 #include "hw/arm/armv7m.h"
27 #include "hw/char/pl011.h"
28 #include "hw/input/stellaris_gamepad.h"
29 #include "hw/core/irq.h"
30 #include "hw/watchdog/cmsdk-apb-watchdog.h"
31 #include "migration/vmstate.h"
32 #include "hw/misc/unimp.h"
33 #include "hw/timer/stellaris-gptm.h"
34 #include "hw/core/qdev-clock.h"
35 #include "qom/object.h"
36 #include "qobject/qlist.h"
37 #include "ui/input.h"
38
39 #define GPIO_A 0
40 #define GPIO_B 1
41 #define GPIO_C 2
42 #define GPIO_D 3
43 #define GPIO_E 4
44 #define GPIO_F 5
45 #define GPIO_G 6
46
47 #define BP_OLED_I2C 0x01
48 #define BP_OLED_SSI 0x02
49 #define BP_GAMEPAD 0x04
50
51 #define NUM_IRQ_LINES 64
52 #define NUM_PRIO_BITS 3
53
54 #define NUM_GPIO 7
55 #define NUM_UART 4
56 #define NUM_GPTM 4
57 #define NUM_I2C 2
58
59 /*
60 * See Stellaris Data Sheet chapter 5.2.5 "System Control",
61 * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4).
62 */
63 #define DC1_WDT 3
64 #define DC1_HIB 6
65 #define DC1_MPU 7
66 #define DC1_ADC 16
67 #define DC1_PWM 20
68 #define DC2_UART(n) (n)
69 #define DC2_SSI 4
70 #define DC2_QEI(n) (8 + n)
71 #define DC2_I2C(n) (12 + 2 * n)
72 #define DC2_GPTM(n) (16 + n)
73 #define DC2_COMP(n) (24 + n)
74 #define DC4_GPIO(n) (n)
75 #define DC4_EMAC 28
76
77 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)
78
79 typedef const struct {
80 const char *name;
81 uint32_t did0;
82 uint32_t did1;
83 uint32_t dc0;
84 uint32_t dc1;
85 uint32_t dc2;
86 uint32_t dc3;
87 uint32_t dc4;
88 uint32_t peripherals;
89 } stellaris_board_info;
90
91 /* System controller. */
92
93 #define TYPE_STELLARIS_SYS "stellaris-sys"
94 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
95
96 struct ssys_state {
97 SysBusDevice parent_obj;
98
99 MemoryRegion iomem;
100 uint32_t pborctl;
101 uint32_t ldopctl;
102 uint32_t int_status;
103 uint32_t int_mask;
104 uint32_t resc;
105 uint32_t rcc;
106 uint32_t rcc2;
107 uint32_t rcgc[3];
108 uint32_t scgc[3];
109 uint32_t dcgc[3];
110 uint32_t clkvclr;
111 uint32_t ldoarst;
112 qemu_irq irq;
113 Clock *sysclk;
114 /* Properties (all read-only registers) */
115 uint32_t user0;
116 uint32_t user1;
117 uint32_t did0;
118 uint32_t did1;
119 uint32_t dc0;
120 uint32_t dc1;
121 uint32_t dc2;
122 uint32_t dc3;
123 uint32_t dc4;
124 };
125
126 static void ssys_update(ssys_state *s)
127 {
128 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
129 }
130
131 static const uint32_t pllcfg_sandstorm[16] = {
132 0x31c0, /* 1 Mhz */
133 0x1ae0, /* 1.8432 Mhz */
134 0x18c0, /* 2 Mhz */
135 0xd573, /* 2.4576 Mhz */
136 0x37a6, /* 3.57954 Mhz */
137 0x1ae2, /* 3.6864 Mhz */
138 0x0c40, /* 4 Mhz */
139 0x98bc, /* 4.906 Mhz */
140 0x935b, /* 4.9152 Mhz */
141 0x09c0, /* 5 Mhz */
142 0x4dee, /* 5.12 Mhz */
143 0x0c41, /* 6 Mhz */
144 0x75db, /* 6.144 Mhz */
145 0x1ae6, /* 7.3728 Mhz */
146 0x0600, /* 8 Mhz */
147 0x585b /* 8.192 Mhz */
148 };
149
150 static const uint32_t pllcfg_fury[16] = {
151 0x3200, /* 1 Mhz */
152 0x1b20, /* 1.8432 Mhz */
153 0x1900, /* 2 Mhz */
154 0xf42b, /* 2.4576 Mhz */
155 0x37e3, /* 3.57954 Mhz */
156 0x1b21, /* 3.6864 Mhz */
157 0x0c80, /* 4 Mhz */
158 0x98ee, /* 4.906 Mhz */
159 0xd5b4, /* 4.9152 Mhz */
160 0x0a00, /* 5 Mhz */
161 0x4e27, /* 5.12 Mhz */
162 0x1902, /* 6 Mhz */
163 0xec1c, /* 6.144 Mhz */
164 0x1b23, /* 7.3728 Mhz */
165 0x0640, /* 8 Mhz */
166 0xb11c /* 8.192 Mhz */
167 };
168
169 #define DID0_VER_MASK 0x70000000
170 #define DID0_VER_0 0x00000000
171 #define DID0_VER_1 0x10000000
172
173 #define DID0_CLASS_MASK 0x00FF0000
174 #define DID0_CLASS_SANDSTORM 0x00000000
175 #define DID0_CLASS_FURY 0x00010000
176
177 static int ssys_board_class(const ssys_state *s)
178 {
179 uint32_t did0 = s->did0;
180 switch (did0 & DID0_VER_MASK) {
181 case DID0_VER_0:
182 return DID0_CLASS_SANDSTORM;
183 case DID0_VER_1:
184 switch (did0 & DID0_CLASS_MASK) {
185 case DID0_CLASS_SANDSTORM:
186 case DID0_CLASS_FURY:
187 return did0 & DID0_CLASS_MASK;
188 }
189 /* for unknown classes, fall through */
190 default:
191 /* This can only happen if the hardwired constant did0 value
192 * in this board's stellaris_board_info struct is wrong.
193 */
194 g_assert_not_reached();
195 }
196 }
197
198 static uint64_t ssys_read(void *opaque, hwaddr offset,
199 unsigned size)
200 {
201 ssys_state *s = (ssys_state *)opaque;
202
203 switch (offset) {
204 case 0x000: /* DID0 */
205 return s->did0;
206 case 0x004: /* DID1 */
207 return s->did1;
208 case 0x008: /* DC0 */
209 return s->dc0;
210 case 0x010: /* DC1 */
211 return s->dc1;
212 case 0x014: /* DC2 */
213 return s->dc2;
214 case 0x018: /* DC3 */
215 return s->dc3;
216 case 0x01c: /* DC4 */
217 return s->dc4;
218 case 0x030: /* PBORCTL */
219 return s->pborctl;
220 case 0x034: /* LDOPCTL */
221 return s->ldopctl;
222 case 0x040: /* SRCR0 */
223 return 0;
224 case 0x044: /* SRCR1 */
225 return 0;
226 case 0x048: /* SRCR2 */
227 return 0;
228 case 0x050: /* RIS */
229 return s->int_status;
230 case 0x054: /* IMC */
231 return s->int_mask;
232 case 0x058: /* MISC */
233 return s->int_status & s->int_mask;
234 case 0x05c: /* RESC */
235 return s->resc;
236 case 0x060: /* RCC */
237 return s->rcc;
238 case 0x064: /* PLLCFG */
239 {
240 int xtal;
241 xtal = (s->rcc >> 6) & 0xf;
242 switch (ssys_board_class(s)) {
243 case DID0_CLASS_FURY:
244 return pllcfg_fury[xtal];
245 case DID0_CLASS_SANDSTORM:
246 return pllcfg_sandstorm[xtal];
247 default:
248 g_assert_not_reached();
249 }
250 }
251 case 0x070: /* RCC2 */
252 return s->rcc2;
253 case 0x100: /* RCGC0 */
254 return s->rcgc[0];
255 case 0x104: /* RCGC1 */
256 return s->rcgc[1];
257 case 0x108: /* RCGC2 */
258 return s->rcgc[2];
259 case 0x110: /* SCGC0 */
260 return s->scgc[0];
261 case 0x114: /* SCGC1 */
262 return s->scgc[1];
263 case 0x118: /* SCGC2 */
264 return s->scgc[2];
265 case 0x120: /* DCGC0 */
266 return s->dcgc[0];
267 case 0x124: /* DCGC1 */
268 return s->dcgc[1];
269 case 0x128: /* DCGC2 */
270 return s->dcgc[2];
271 case 0x150: /* CLKVCLR */
272 return s->clkvclr;
273 case 0x160: /* LDOARST */
274 return s->ldoarst;
275 case 0x1e0: /* USER0 */
276 return s->user0;
277 case 0x1e4: /* USER1 */
278 return s->user1;
279 default:
280 qemu_log_mask(LOG_GUEST_ERROR,
281 "SSYS: read at bad offset 0x%x\n", (int)offset);
282 return 0;
283 }
284 }
285
286 static bool ssys_use_rcc2(ssys_state *s)
287 {
288 return (s->rcc2 >> 31) & 0x1;
289 }
290
291 /*
292 * Calculate the system clock period. We only want to propagate
293 * this change to the rest of the system if we're not being called
294 * from migration post-load.
295 */
296 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
297 {
298 int period_ns;
299 /*
300 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
301 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
302 * frequency by X is the same as multiplying the period by X.
303 */
304 if (ssys_use_rcc2(s)) {
305 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
306 } else {
307 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
308 }
309 clock_set_ns(s->sysclk, period_ns);
310 if (propagate_clock) {
311 clock_propagate(s->sysclk);
312 }
313 }
314
315 static void ssys_write(void *opaque, hwaddr offset,
316 uint64_t value, unsigned size)
317 {
318 ssys_state *s = (ssys_state *)opaque;
319
320 switch (offset) {
321 case 0x030: /* PBORCTL */
322 s->pborctl = value & 0xffff;
323 break;
324 case 0x034: /* LDOPCTL */
325 s->ldopctl = value & 0x1f;
326 break;
327 case 0x040: /* SRCR0 */
328 case 0x044: /* SRCR1 */
329 case 0x048: /* SRCR2 */
330 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
331 break;
332 case 0x054: /* IMC */
333 s->int_mask = value & 0x7f;
334 break;
335 case 0x058: /* MISC */
336 s->int_status &= ~value;
337 break;
338 case 0x05c: /* RESC */
339 s->resc = value & 0x3f;
340 break;
341 case 0x060: /* RCC */
342 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
343 /* PLL enable. */
344 s->int_status |= (1 << 6);
345 }
346 s->rcc = value;
347 ssys_calculate_system_clock(s, true);
348 break;
349 case 0x070: /* RCC2 */
350 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
351 break;
352 }
353
354 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
355 /* PLL enable. */
356 s->int_status |= (1 << 6);
357 }
358 s->rcc2 = value;
359 ssys_calculate_system_clock(s, true);
360 break;
361 case 0x100: /* RCGC0 */
362 s->rcgc[0] = value;
363 break;
364 case 0x104: /* RCGC1 */
365 s->rcgc[1] = value;
366 break;
367 case 0x108: /* RCGC2 */
368 s->rcgc[2] = value;
369 break;
370 case 0x110: /* SCGC0 */
371 s->scgc[0] = value;
372 break;
373 case 0x114: /* SCGC1 */
374 s->scgc[1] = value;
375 break;
376 case 0x118: /* SCGC2 */
377 s->scgc[2] = value;
378 break;
379 case 0x120: /* DCGC0 */
380 s->dcgc[0] = value;
381 break;
382 case 0x124: /* DCGC1 */
383 s->dcgc[1] = value;
384 break;
385 case 0x128: /* DCGC2 */
386 s->dcgc[2] = value;
387 break;
388 case 0x150: /* CLKVCLR */
389 s->clkvclr = value;
390 break;
391 case 0x160: /* LDOARST */
392 s->ldoarst = value;
393 break;
394 default:
395 qemu_log_mask(LOG_GUEST_ERROR,
396 "SSYS: write at bad offset 0x%x\n", (int)offset);
397 }
398 ssys_update(s);
399 }
400
401 static const MemoryRegionOps ssys_ops = {
402 .read = ssys_read,
403 .write = ssys_write,
404 .endianness = DEVICE_NATIVE_ENDIAN,
405 };
406
407 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
408 {
409 ssys_state *s = STELLARIS_SYS(obj);
410
411 s->pborctl = 0x7ffd;
412 s->rcc = 0x078e3ac0;
413
414 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
415 s->rcc2 = 0;
416 } else {
417 s->rcc2 = 0x07802810;
418 }
419 s->rcgc[0] = 1;
420 s->scgc[0] = 1;
421 s->dcgc[0] = 1;
422 }
423
424 static void stellaris_sys_reset_hold(Object *obj, ResetType type)
425 {
426 ssys_state *s = STELLARIS_SYS(obj);
427
428 /* OK to propagate clocks from the hold phase */
429 ssys_calculate_system_clock(s, true);
430 }
431
432 static void stellaris_sys_reset_exit(Object *obj, ResetType type)
433 {
434 }
435
436 static int stellaris_sys_post_load(void *opaque, int version_id)
437 {
438 ssys_state *s = opaque;
439
440 ssys_calculate_system_clock(s, false);
441
442 return 0;
443 }
444
445 static const VMStateDescription vmstate_stellaris_sys = {
446 .name = "stellaris_sys",
447 .version_id = 2,
448 .minimum_version_id = 1,
449 .post_load = stellaris_sys_post_load,
450 .fields = (const VMStateField[]) {
451 VMSTATE_UINT32(pborctl, ssys_state),
452 VMSTATE_UINT32(ldopctl, ssys_state),
453 VMSTATE_UINT32(int_mask, ssys_state),
454 VMSTATE_UINT32(int_status, ssys_state),
455 VMSTATE_UINT32(resc, ssys_state),
456 VMSTATE_UINT32(rcc, ssys_state),
457 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
458 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
459 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
460 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
461 VMSTATE_UINT32(clkvclr, ssys_state),
462 VMSTATE_UINT32(ldoarst, ssys_state),
463 /* No field for sysclk -- handled in post-load instead */
464 VMSTATE_END_OF_LIST()
465 }
466 };
467
468 static const Property stellaris_sys_properties[] = {
469 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
470 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
471 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
472 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
473 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
474 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
475 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
476 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
477 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
478 };
479
480 static void stellaris_sys_instance_init(Object *obj)
481 {
482 ssys_state *s = STELLARIS_SYS(obj);
483 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
484
485 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
486 sysbus_init_mmio(sbd, &s->iomem);
487 sysbus_init_irq(sbd, &s->irq);
488 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
489 }
490
491 /*
492 * I2C controller.
493 * ??? For now we only implement the master interface.
494 */
495
496 #define TYPE_STELLARIS_I2C "stellaris-i2c"
497 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
498
499 struct stellaris_i2c_state {
500 SysBusDevice parent_obj;
501
502 I2CBus *bus;
503 qemu_irq irq;
504 MemoryRegion iomem;
505 uint32_t msa;
506 uint32_t mcs;
507 uint32_t mdr;
508 uint32_t mtpr;
509 uint32_t mimr;
510 uint32_t mris;
511 uint32_t mcr;
512 };
513
514 #define STELLARIS_I2C_MCS_BUSY 0x01
515 #define STELLARIS_I2C_MCS_ERROR 0x02
516 #define STELLARIS_I2C_MCS_ADRACK 0x04
517 #define STELLARIS_I2C_MCS_DATACK 0x08
518 #define STELLARIS_I2C_MCS_ARBLST 0x10
519 #define STELLARIS_I2C_MCS_IDLE 0x20
520 #define STELLARIS_I2C_MCS_BUSBSY 0x40
521
522 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
523 unsigned size)
524 {
525 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
526
527 switch (offset) {
528 case 0x00: /* MSA */
529 return s->msa;
530 case 0x04: /* MCS */
531 /* We don't emulate timing, so the controller is never busy. */
532 return s->mcs | STELLARIS_I2C_MCS_IDLE;
533 case 0x08: /* MDR */
534 return s->mdr;
535 case 0x0c: /* MTPR */
536 return s->mtpr;
537 case 0x10: /* MIMR */
538 return s->mimr;
539 case 0x14: /* MRIS */
540 return s->mris;
541 case 0x18: /* MMIS */
542 return s->mris & s->mimr;
543 case 0x20: /* MCR */
544 return s->mcr;
545 default:
546 qemu_log_mask(LOG_GUEST_ERROR,
547 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
548 return 0;
549 }
550 }
551
552 static void stellaris_i2c_update(stellaris_i2c_state *s)
553 {
554 int level;
555
556 level = (s->mris & s->mimr) != 0;
557 qemu_set_irq(s->irq, level);
558 }
559
560 static void stellaris_i2c_write(void *opaque, hwaddr offset,
561 uint64_t value, unsigned size)
562 {
563 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
564
565 switch (offset) {
566 case 0x00: /* MSA */
567 s->msa = value & 0xff;
568 break;
569 case 0x04: /* MCS */
570 if ((s->mcr & 0x10) == 0) {
571 /* Disabled. Do nothing. */
572 break;
573 }
574 /* Grab the bus if this is starting a transfer. */
575 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
576 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
577 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
578 } else {
579 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
580 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
581 }
582 }
583 /* If we don't have the bus then indicate an error. */
584 if (!i2c_bus_busy(s->bus)
585 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
586 s->mcs |= STELLARIS_I2C_MCS_ERROR;
587 break;
588 }
589 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
590 if (value & 1) {
591 /* Transfer a byte. */
592 /* TODO: Handle errors. */
593 if (s->msa & 1) {
594 /* Recv */
595 s->mdr = i2c_recv(s->bus);
596 } else {
597 /* Send */
598 i2c_send(s->bus, s->mdr);
599 }
600 /* Raise an interrupt. */
601 s->mris |= 1;
602 }
603 if (value & 4) {
604 /* Finish transfer. */
605 i2c_end_transfer(s->bus);
606 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
607 }
608 break;
609 case 0x08: /* MDR */
610 s->mdr = value & 0xff;
611 break;
612 case 0x0c: /* MTPR */
613 s->mtpr = value & 0xff;
614 break;
615 case 0x10: /* MIMR */
616 s->mimr = 1;
617 break;
618 case 0x1c: /* MICR */
619 s->mris &= ~value;
620 break;
621 case 0x20: /* MCR */
622 if (value & 1) {
623 qemu_log_mask(LOG_UNIMP,
624 "stellaris_i2c: Loopback not implemented\n");
625 }
626 if (value & 0x20) {
627 qemu_log_mask(LOG_UNIMP,
628 "stellaris_i2c: Slave mode not implemented\n");
629 }
630 s->mcr = value & 0x31;
631 break;
632 default:
633 qemu_log_mask(LOG_GUEST_ERROR,
634 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
635 }
636 stellaris_i2c_update(s);
637 }
638
639 static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
640 {
641 stellaris_i2c_state *s = STELLARIS_I2C(obj);
642
643 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
644 i2c_end_transfer(s->bus);
645 }
646
647 static void stellaris_i2c_reset_hold(Object *obj, ResetType type)
648 {
649 stellaris_i2c_state *s = STELLARIS_I2C(obj);
650
651 s->msa = 0;
652 s->mcs = 0;
653 s->mdr = 0;
654 s->mtpr = 1;
655 s->mimr = 0;
656 s->mris = 0;
657 s->mcr = 0;
658 }
659
660 static void stellaris_i2c_reset_exit(Object *obj, ResetType type)
661 {
662 stellaris_i2c_state *s = STELLARIS_I2C(obj);
663
664 stellaris_i2c_update(s);
665 }
666
667 static const MemoryRegionOps stellaris_i2c_ops = {
668 .read = stellaris_i2c_read,
669 .write = stellaris_i2c_write,
670 .endianness = DEVICE_NATIVE_ENDIAN,
671 };
672
673 static const VMStateDescription vmstate_stellaris_i2c = {
674 .name = "stellaris_i2c",
675 .version_id = 1,
676 .minimum_version_id = 1,
677 .fields = (const VMStateField[]) {
678 VMSTATE_UINT32(msa, stellaris_i2c_state),
679 VMSTATE_UINT32(mcs, stellaris_i2c_state),
680 VMSTATE_UINT32(mdr, stellaris_i2c_state),
681 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
682 VMSTATE_UINT32(mimr, stellaris_i2c_state),
683 VMSTATE_UINT32(mris, stellaris_i2c_state),
684 VMSTATE_UINT32(mcr, stellaris_i2c_state),
685 VMSTATE_END_OF_LIST()
686 }
687 };
688
689 static void stellaris_i2c_init(Object *obj)
690 {
691 DeviceState *dev = DEVICE(obj);
692 stellaris_i2c_state *s = STELLARIS_I2C(obj);
693 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
694 I2CBus *bus;
695
696 sysbus_init_irq(sbd, &s->irq);
697 bus = i2c_init_bus(dev, "i2c");
698 s->bus = bus;
699
700 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
701 "i2c", 0x1000);
702 sysbus_init_mmio(sbd, &s->iomem);
703 }
704
705 /* Analogue to Digital Converter. This is only partially implemented,
706 enough for applications that use a combined ADC and timer tick. */
707
708 #define STELLARIS_ADC_EM_CONTROLLER 0
709 #define STELLARIS_ADC_EM_COMP 1
710 #define STELLARIS_ADC_EM_EXTERNAL 4
711 #define STELLARIS_ADC_EM_TIMER 5
712 #define STELLARIS_ADC_EM_PWM0 6
713 #define STELLARIS_ADC_EM_PWM1 7
714 #define STELLARIS_ADC_EM_PWM2 8
715
716 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
717 #define STELLARIS_ADC_FIFO_FULL 0x1000
718
719 #define TYPE_STELLARIS_ADC "stellaris-adc"
720 typedef struct StellarisADCState StellarisADCState;
721 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
722
723 struct StellarisADCState {
724 SysBusDevice parent_obj;
725
726 MemoryRegion iomem;
727 uint32_t actss;
728 uint32_t ris;
729 uint32_t im;
730 uint32_t emux;
731 uint32_t ostat;
732 uint32_t ustat;
733 uint32_t sspri;
734 uint32_t sac;
735 struct {
736 uint32_t state;
737 uint32_t data[16];
738 } fifo[4];
739 uint32_t ssmux[4];
740 uint32_t ssctl[4];
741 uint32_t noise;
742 qemu_irq irq[4];
743 };
744
745 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
746 {
747 int tail;
748
749 tail = s->fifo[n].state & 0xf;
750 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
751 s->ustat |= 1 << n;
752 } else {
753 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
754 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
755 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
756 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
757 }
758 return s->fifo[n].data[tail];
759 }
760
761 static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
762 uint32_t value)
763 {
764 int head;
765
766 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
767 FIFO fir each sequencer. */
768 head = (s->fifo[n].state >> 4) & 0xf;
769 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
770 s->ostat |= 1 << n;
771 return;
772 }
773 s->fifo[n].data[head] = value;
774 head = (head + 1) & 0xf;
775 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
776 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
777 if ((s->fifo[n].state & 0xf) == head)
778 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
779 }
780
781 static void stellaris_adc_update(StellarisADCState *s)
782 {
783 int level;
784 int n;
785
786 for (n = 0; n < 4; n++) {
787 level = (s->ris & s->im & (1 << n)) != 0;
788 qemu_set_irq(s->irq[n], level);
789 }
790 }
791
792 static void stellaris_adc_trigger(void *opaque, int irq, int level)
793 {
794 StellarisADCState *s = opaque;
795 int n;
796
797 for (n = 0; n < 4; n++) {
798 if ((s->actss & (1 << n)) == 0) {
799 continue;
800 }
801
802 if (((s->emux >> (n * 4)) & 0xff) != 5) {
803 continue;
804 }
805
806 /* Some applications use the ADC as a random number source, so introduce
807 some variation into the signal. */
808 s->noise = s->noise * 314159 + 1;
809 /* ??? actual inputs not implemented. Return an arbitrary value. */
810 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
811 s->ris |= (1 << n);
812 stellaris_adc_update(s);
813 }
814 }
815
816 static void stellaris_adc_reset_hold(Object *obj, ResetType type)
817 {
818 StellarisADCState *s = STELLARIS_ADC(obj);
819 int n;
820
821 for (n = 0; n < 4; n++) {
822 s->ssmux[n] = 0;
823 s->ssctl[n] = 0;
824 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
825 }
826 }
827
828 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
829 unsigned size)
830 {
831 StellarisADCState *s = opaque;
832
833 /* TODO: Implement this. */
834 if (offset >= 0x40 && offset < 0xc0) {
835 int n;
836 n = (offset - 0x40) >> 5;
837 switch (offset & 0x1f) {
838 case 0x00: /* SSMUX */
839 return s->ssmux[n];
840 case 0x04: /* SSCTL */
841 return s->ssctl[n];
842 case 0x08: /* SSFIFO */
843 return stellaris_adc_fifo_read(s, n);
844 case 0x0c: /* SSFSTAT */
845 return s->fifo[n].state;
846 default:
847 break;
848 }
849 }
850 switch (offset) {
851 case 0x00: /* ACTSS */
852 return s->actss;
853 case 0x04: /* RIS */
854 return s->ris;
855 case 0x08: /* IM */
856 return s->im;
857 case 0x0c: /* ISC */
858 return s->ris & s->im;
859 case 0x10: /* OSTAT */
860 return s->ostat;
861 case 0x14: /* EMUX */
862 return s->emux;
863 case 0x18: /* USTAT */
864 return s->ustat;
865 case 0x20: /* SSPRI */
866 return s->sspri;
867 case 0x30: /* SAC */
868 return s->sac;
869 default:
870 qemu_log_mask(LOG_GUEST_ERROR,
871 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
872 return 0;
873 }
874 }
875
876 static void stellaris_adc_write(void *opaque, hwaddr offset,
877 uint64_t value, unsigned size)
878 {
879 StellarisADCState *s = opaque;
880
881 /* TODO: Implement this. */
882 if (offset >= 0x40 && offset < 0xc0) {
883 int n;
884 n = (offset - 0x40) >> 5;
885 switch (offset & 0x1f) {
886 case 0x00: /* SSMUX */
887 s->ssmux[n] = value & 0x33333333;
888 return;
889 case 0x04: /* SSCTL */
890 if (value != 6) {
891 qemu_log_mask(LOG_UNIMP,
892 "ADC: Unimplemented sequence %" PRIx64 "\n",
893 value);
894 }
895 s->ssctl[n] = value;
896 return;
897 default:
898 break;
899 }
900 }
901 switch (offset) {
902 case 0x00: /* ACTSS */
903 s->actss = value & 0xf;
904 break;
905 case 0x08: /* IM */
906 s->im = value;
907 break;
908 case 0x0c: /* ISC */
909 s->ris &= ~value;
910 break;
911 case 0x10: /* OSTAT */
912 s->ostat &= ~value;
913 break;
914 case 0x14: /* EMUX */
915 s->emux = value;
916 break;
917 case 0x18: /* USTAT */
918 s->ustat &= ~value;
919 break;
920 case 0x20: /* SSPRI */
921 s->sspri = value;
922 break;
923 case 0x28: /* PSSI */
924 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
925 break;
926 case 0x30: /* SAC */
927 s->sac = value;
928 break;
929 default:
930 qemu_log_mask(LOG_GUEST_ERROR,
931 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
932 }
933 stellaris_adc_update(s);
934 }
935
936 static const MemoryRegionOps stellaris_adc_ops = {
937 .read = stellaris_adc_read,
938 .write = stellaris_adc_write,
939 .endianness = DEVICE_NATIVE_ENDIAN,
940 };
941
942 static const VMStateDescription vmstate_stellaris_adc = {
943 .name = "stellaris_adc",
944 .version_id = 1,
945 .minimum_version_id = 1,
946 .fields = (const VMStateField[]) {
947 VMSTATE_UINT32(actss, StellarisADCState),
948 VMSTATE_UINT32(ris, StellarisADCState),
949 VMSTATE_UINT32(im, StellarisADCState),
950 VMSTATE_UINT32(emux, StellarisADCState),
951 VMSTATE_UINT32(ostat, StellarisADCState),
952 VMSTATE_UINT32(ustat, StellarisADCState),
953 VMSTATE_UINT32(sspri, StellarisADCState),
954 VMSTATE_UINT32(sac, StellarisADCState),
955 VMSTATE_UINT32(fifo[0].state, StellarisADCState),
956 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
957 VMSTATE_UINT32(ssmux[0], StellarisADCState),
958 VMSTATE_UINT32(ssctl[0], StellarisADCState),
959 VMSTATE_UINT32(fifo[1].state, StellarisADCState),
960 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
961 VMSTATE_UINT32(ssmux[1], StellarisADCState),
962 VMSTATE_UINT32(ssctl[1], StellarisADCState),
963 VMSTATE_UINT32(fifo[2].state, StellarisADCState),
964 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
965 VMSTATE_UINT32(ssmux[2], StellarisADCState),
966 VMSTATE_UINT32(ssctl[2], StellarisADCState),
967 VMSTATE_UINT32(fifo[3].state, StellarisADCState),
968 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
969 VMSTATE_UINT32(ssmux[3], StellarisADCState),
970 VMSTATE_UINT32(ssctl[3], StellarisADCState),
971 VMSTATE_UINT32(noise, StellarisADCState),
972 VMSTATE_END_OF_LIST()
973 }
974 };
975
976 static void stellaris_adc_init(Object *obj)
977 {
978 DeviceState *dev = DEVICE(obj);
979 StellarisADCState *s = STELLARIS_ADC(obj);
980 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
981 int n;
982
983 for (n = 0; n < 4; n++) {
984 sysbus_init_irq(sbd, &s->irq[n]);
985 }
986
987 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
988 "adc", 0x1000);
989 sysbus_init_mmio(sbd, &s->iomem);
990 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
991 }
992
993 /* Board init. */
994 static const stellaris_board_info stellaris_boards[] = {
995 { "LM3S811EVB",
996 0,
997 0x0032000e,
998 0x001f001f, /* dc0 */
999 0x001132bf,
1000 0x01071013,
1001 0x3f0f01ff,
1002 0x0000001f,
1003 BP_OLED_I2C
1004 },
1005 { "LM3S6965EVB",
1006 0x10010002,
1007 0x1073402e,
1008 0x00ff007f, /* dc0 */
1009 0x001133ff,
1010 0x030f5317,
1011 0x0f0f87ff,
1012 0x5000007f,
1013 BP_OLED_SSI | BP_GAMEPAD
1014 }
1015 };
1016
1017 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
1018 {
1019 static const int uart_irq[NUM_UART] = {5, 6, 33, 34};
1020 static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35};
1021 static const uint32_t gpio_addr[NUM_GPIO] =
1022 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1023 0x40024000, 0x40025000, 0x40026000};
1024 static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31};
1025 static const uint32_t i2c_addr[NUM_I2C] = {0x40020000, 0x40021000};
1026 static const int i2c_irq[NUM_I2C] = {8, 37};
1027
1028 /* Memory map of SoC devices, from
1029 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1030 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1031 *
1032 * 40000000 wdtimer
1033 * 40004000 GPIO
1034 * 40005000 GPIO
1035 * 40006000 GPIO
1036 * 40007000 GPIO
1037 * 40008000 SSI
1038 * 4000c000 UART
1039 * 4000d000 UART
1040 * 4000e000 UART
1041 * 40020000 i2c
1042 * 40021000 i2c (unimplemented)
1043 * 40024000 GPIO
1044 * 40025000 GPIO
1045 * 40026000 GPIO
1046 * 40028000 PWM (unimplemented)
1047 * 4002c000 QEI (unimplemented)
1048 * 4002d000 QEI (unimplemented)
1049 * 40030000 gptimer
1050 * 40031000 gptimer
1051 * 40032000 gptimer
1052 * 40033000 gptimer
1053 * 40038000 ADC
1054 * 4003c000 analogue comparator (unimplemented)
1055 * 40048000 ethernet
1056 * 400fc000 hibernation module (unimplemented)
1057 * 400fd000 flash memory control (unimplemented)
1058 * 400fe000 system control
1059 */
1060
1061 Object *soc_container;
1062 DeviceState *gpio_dev[NUM_GPIO], *armv7m, *nvic;
1063 qemu_irq gpio_in[NUM_GPIO][8];
1064 qemu_irq gpio_out[NUM_GPIO][8];
1065 qemu_irq adc;
1066 int sram_size;
1067 int flash_size;
1068 DeviceState *i2c_dev[NUM_I2C] = { };
1069 DeviceState *dev;
1070 DeviceState *ssys_dev;
1071 int i;
1072 int j;
1073 NICInfo *nd;
1074 MACAddr mac;
1075
1076 MemoryRegion *sram = g_new(MemoryRegion, 1);
1077 MemoryRegion *flash = g_new(MemoryRegion, 1);
1078 MemoryRegion *system_memory = get_system_memory();
1079
1080 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1081 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1082
1083 soc_container = object_new(TYPE_CONTAINER);
1084 object_property_add_child(OBJECT(ms), "soc", soc_container);
1085
1086 /* Flash programming is done via the SCU, so pretend it is ROM. */
1087 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1088 &error_fatal);
1089 memory_region_add_subregion(system_memory, 0, flash);
1090
1091 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1092 &error_fatal);
1093 memory_region_add_subregion(system_memory, 0x20000000, sram);
1094
1095 /*
1096 * Create the system-registers object early, because we will
1097 * need its sysclk output.
1098 */
1099 ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
1100 object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
1101
1102 /*
1103 * Most devices come preprogrammed with a MAC address in the user data.
1104 * Generate a MAC address now, if there isn't a matching -nic for it.
1105 */
1106 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris");
1107 if (nd) {
1108 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a));
1109 } else {
1110 qemu_macaddr_default_if_unset(&mac);
1111 }
1112
1113 qdev_prop_set_uint32(ssys_dev, "user0",
1114 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16));
1115 qdev_prop_set_uint32(ssys_dev, "user1",
1116 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16));
1117 qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
1118 qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
1119 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
1120 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
1121 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
1122 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
1123 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
1124 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
1125
1126 armv7m = qdev_new(TYPE_ARMV7M);
1127 object_property_add_child(soc_container, "v7m", OBJECT(armv7m));
1128 qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);
1129 qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);
1130 qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);
1131 qdev_prop_set_bit(armv7m, "enable-bitband", true);
1132 qdev_connect_clock_in(armv7m, "cpuclk",
1133 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1134 /* This SoC does not connect the systick reference clock */
1135 object_property_set_link(OBJECT(armv7m), "memory",
1136 OBJECT(get_system_memory()), &error_abort);
1137 /* This will exit with an error if the user passed us a bad cpu_type */
1138 sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);
1139 nvic = armv7m;
1140
1141 /* Now we can wire up the IRQ and MMIO of the system registers */
1142 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
1143 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
1144
1145 if (DEV_CAP(1, ADC)) {
1146 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1147 qdev_get_gpio_in(nvic, 14),
1148 qdev_get_gpio_in(nvic, 15),
1149 qdev_get_gpio_in(nvic, 16),
1150 qdev_get_gpio_in(nvic, 17),
1151 NULL);
1152 adc = qdev_get_gpio_in(dev, 0);
1153 } else {
1154 adc = NULL;
1155 }
1156 for (i = 0; i < NUM_GPTM; i++) {
1157 if (DEV_CAP(2, GPTM(i))) {
1158 SysBusDevice *sbd;
1159
1160 dev = qdev_new(TYPE_STELLARIS_GPTM);
1161 sbd = SYS_BUS_DEVICE(dev);
1162 object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
1163 qdev_connect_clock_in(dev, "clk",
1164 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1165 sysbus_realize_and_unref(sbd, &error_fatal);
1166 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
1167 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
1168 /* TODO: This is incorrect, but we get away with it because
1169 the ADC output is only ever pulsed. */
1170 qdev_connect_gpio_out(dev, 0, adc);
1171 }
1172 }
1173
1174 if (DEV_CAP(1, WDT)) {
1175 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1176 object_property_add_child(soc_container, "wdg", OBJECT(dev));
1177 qdev_connect_clock_in(dev, "WDOGCLK",
1178 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1179
1180 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1182 0,
1183 0x40000000u);
1184 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1185 0,
1186 qdev_get_gpio_in(nvic, 18));
1187 }
1188
1189
1190 for (i = 0; i < NUM_GPIO; i++) {
1191 if (DEV_CAP(4, GPIO(i))) {
1192 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1193 qdev_get_gpio_in(nvic,
1194 gpio_irq[i]));
1195 for (j = 0; j < 8; j++) {
1196 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1197 gpio_out[i][j] = NULL;
1198 }
1199 }
1200 }
1201
1202 for (i = 0; i < NUM_I2C; i++) {
1203 if (DEV_CAP(2, I2C(i))) {
1204 i2c_dev[i] = sysbus_create_simple(TYPE_STELLARIS_I2C, i2c_addr[i],
1205 qdev_get_gpio_in(nvic,
1206 i2c_irq[i]));
1207 }
1208 }
1209 if (board->peripherals & BP_OLED_I2C) {
1210 I2CBus *bus = (I2CBus *)qdev_get_child_bus(i2c_dev[0], "i2c");
1211
1212 i2c_slave_create_simple(bus, "ssd0303", 0x3d);
1213 }
1214
1215 for (i = 0; i < NUM_UART; i++) {
1216 if (DEV_CAP(2, UART(i))) {
1217 SysBusDevice *sbd;
1218
1219 dev = qdev_new("pl011_luminary");
1220 object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
1221 sbd = SYS_BUS_DEVICE(dev);
1222 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
1223 sysbus_realize_and_unref(sbd, &error_fatal);
1224 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000);
1225 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
1226 }
1227 }
1228 if (DEV_CAP(2, SSI)) {
1229 dev = sysbus_create_simple("pl022", 0x40008000,
1230 qdev_get_gpio_in(nvic, 7));
1231 if (board->peripherals & BP_OLED_SSI) {
1232 void *bus;
1233 DeviceState *sddev;
1234 DeviceState *ssddev;
1235 DriveInfo *dinfo;
1236 DeviceState *carddev;
1237 DeviceState *gpio_d_splitter;
1238 BlockBackend *blk;
1239
1240 /*
1241 * Some boards have both an OLED controller and SD card connected to
1242 * the same SSI port, with the SD card chip select connected to a
1243 * GPIO pin. Technically the OLED chip select is connected to the
1244 * SSI Fss pin. We do not bother emulating that as both devices
1245 * should never be selected simultaneously, and our OLED controller
1246 * ignores stray 0xff commands that occur when deselecting the SD
1247 * card.
1248 *
1249 * The h/w wiring is:
1250 * - GPIO pin D0 is wired to the active-low SD card chip select
1251 * - GPIO pin A3 is wired to the active-low OLED chip select
1252 * - The SoC wiring of the PL061 "auxiliary function" for A3 is
1253 * SSI0Fss ("frame signal"), which is an output from the SoC's
1254 * SSI controller. The SSI controller takes SSI0Fss low when it
1255 * transmits a frame, so it can work as a chip-select signal.
1256 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
1257 * (the OLED never sends data to the CPU, so no wiring needed)
1258 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
1259 * and the OLED display-data-in
1260 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
1261 * serial-clock input
1262 * So a guest that wants to use the OLED can configure the PL061
1263 * to make pins A2, A3, A5 aux-function, so they are connected
1264 * directly to the SSI controller. When the SSI controller sends
1265 * data it asserts SSI0Fss which selects the OLED.
1266 * A guest that wants to use the SD card configures A2, A4 and A5
1267 * as aux-function, but leaves A3 as a software-controlled GPIO
1268 * line. It asserts the SD card chip-select by using the PL061
1269 * to control pin D0, and lets the SSI controller handle Clk, Tx
1270 * and Rx. (The SSI controller asserts Fss during tx cycles as
1271 * usual, but because A3 is not set to aux-function this is not
1272 * forwarded to the OLED, and so the OLED stays unselected.)
1273 *
1274 * The QEMU implementation instead is:
1275 * - GPIO pin D0 is wired to the active-low SD card chip select,
1276 * and also to the OLED chip-select which is implemented
1277 * as *active-high*
1278 * - SSI controller signals go to the devices regardless of
1279 * whether the guest programs A2, A4, A5 as aux-function or not
1280 *
1281 * The problem with this implementation is if the guest doesn't
1282 * care about the SD card and only uses the OLED. In that case it
1283 * may choose never to do anything with D0 (leaving it in its
1284 * default floating state, which reliably leaves the card disabled
1285 * because an SD card has a pullup on CS within the card itself),
1286 * and only set up A2, A3, A5. This for us would mean the OLED
1287 * never gets the chip-select assert it needs. We work around
1288 * this with a manual raise of D0 here (despite board creation
1289 * code being the wrong place to raise IRQ lines) to put the OLED
1290 * into an initially selected state.
1291 *
1292 * In theory the right way to model this would be:
1293 * - Implement aux-function support in the PL061, with an
1294 * extra set of AFIN and AFOUT GPIO lines (set up so that
1295 * if a GPIO line is in auxfn mode the main GPIO in and out
1296 * track the AFIN and AFOUT lines)
1297 * - Wire the AFOUT for D0 up to either a line from the
1298 * SSI controller that's pulled low around every transmit,
1299 * or at least to an always-0 line here on the board
1300 * - Make the ssd0323 OLED controller chipselect active-low
1301 */
1302 bus = qdev_get_child_bus(dev, "ssi");
1303 sddev = ssi_create_peripheral(bus, "ssi-sd");
1304
1305 dinfo = drive_get(IF_SD, 0, 0);
1306 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
1307 carddev = qdev_new(TYPE_SD_CARD_SPI);
1308 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
1309 qdev_realize_and_unref(carddev,
1310 qdev_get_child_bus(sddev, "sd-bus"),
1311 &error_fatal);
1312
1313 ssddev = qdev_new("ssd0323");
1314 object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
1315 qdev_prop_set_uint8(ssddev, "cs", 1);
1316 qdev_realize_and_unref(ssddev, bus, &error_fatal);
1317
1318 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
1319 object_property_add_child(OBJECT(ms), "splitter",
1320 OBJECT(gpio_d_splitter));
1321 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
1322 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
1323 qdev_connect_gpio_out(
1324 gpio_d_splitter, 0,
1325 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
1326 qdev_connect_gpio_out(
1327 gpio_d_splitter, 1,
1328 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1329 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
1330
1331 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1332
1333 /* Make sure the select pin is high. */
1334 qemu_irq_raise(gpio_out[GPIO_D][0]);
1335 }
1336 }
1337 if (DEV_CAP(4, EMAC)) {
1338 DeviceState *enet;
1339
1340 enet = qdev_new("stellaris_enet");
1341 object_property_add_child(soc_container, "enet", OBJECT(enet));
1342 if (nd) {
1343 qdev_set_nic_properties(enet, nd);
1344 } else {
1345 qdev_prop_set_macaddr(enet, "mac", mac.a);
1346 }
1347
1348 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1349 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1350 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1351 }
1352 if (board->peripherals & BP_GAMEPAD) {
1353 QList *gpad_keycode_list = qlist_new();
1354 static const int gpad_keycode[5] = {
1355 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT,
1356 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL,
1357 };
1358 DeviceState *gpad;
1359
1360 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
1361 object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
1362 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
1363 qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
1364 }
1365 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list);
1366 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal);
1367
1368 qdev_connect_gpio_out(gpad, 0,
1369 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */
1370 qdev_connect_gpio_out(gpad, 1,
1371 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */
1372 qdev_connect_gpio_out(gpad, 2,
1373 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */
1374 qdev_connect_gpio_out(gpad, 3,
1375 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */
1376 qdev_connect_gpio_out(gpad, 4,
1377 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */
1378 }
1379 for (i = 0; i < 7; i++) {
1380 if (board->dc4 & (1 << i)) {
1381 for (j = 0; j < 8; j++) {
1382 if (gpio_out[i][j]) {
1383 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1384 }
1385 }
1386 }
1387 }
1388
1389 /* Add dummy regions for the devices we don't implement yet,
1390 * so guest accesses don't cause unlogged crashes.
1391 */
1392 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1393 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1394 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1395 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1396 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1397 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1398
1399 armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size);
1400 }
1401
1402 /* FIXME: Figure out how to generate these from stellaris_boards. */
1403 static void lm3s811evb_init(MachineState *machine)
1404 {
1405 stellaris_init(machine, &stellaris_boards[0]);
1406 }
1407
1408 static void lm3s6965evb_init(MachineState *machine)
1409 {
1410 stellaris_init(machine, &stellaris_boards[1]);
1411 }
1412
1413 /*
1414 * Stellaris LM3S811 Evaluation Board Schematics:
1415 * https://www.ti.com/lit/ug/symlink/spmu030.pdf
1416 */
1417 static void lm3s811evb_class_init(ObjectClass *oc, const void *data)
1418 {
1419 MachineClass *mc = MACHINE_CLASS(oc);
1420
1421 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1422 mc->init = lm3s811evb_init;
1423 mc->ignore_memory_transaction_failures = true;
1424 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1425 }
1426
1427 static const TypeInfo lm3s811evb_type = {
1428 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1429 .parent = TYPE_MACHINE,
1430 .class_init = lm3s811evb_class_init,
1431 .interfaces = arm_machine_interfaces,
1432 };
1433
1434 /*
1435 * Stellaris: LM3S6965 Evaluation Board Schematics:
1436 * https://www.ti.com/lit/ug/symlink/spmu029.pdf
1437 */
1438 static void lm3s6965evb_class_init(ObjectClass *oc, const void *data)
1439 {
1440 MachineClass *mc = MACHINE_CLASS(oc);
1441
1442 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1443 mc->init = lm3s6965evb_init;
1444 mc->ignore_memory_transaction_failures = true;
1445 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1446 mc->auto_create_sdcard = true;
1447 }
1448
1449 static const TypeInfo lm3s6965evb_type = {
1450 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1451 .parent = TYPE_MACHINE,
1452 .class_init = lm3s6965evb_class_init,
1453 .interfaces = arm_machine_interfaces,
1454 };
1455
1456 static void stellaris_machine_init(void)
1457 {
1458 type_register_static(&lm3s811evb_type);
1459 type_register_static(&lm3s6965evb_type);
1460 }
1461
1462 type_init(stellaris_machine_init)
1463
1464 static void stellaris_i2c_class_init(ObjectClass *klass, const void *data)
1465 {
1466 DeviceClass *dc = DEVICE_CLASS(klass);
1467 ResettableClass *rc = RESETTABLE_CLASS(klass);
1468
1469 rc->phases.enter = stellaris_i2c_reset_enter;
1470 rc->phases.hold = stellaris_i2c_reset_hold;
1471 rc->phases.exit = stellaris_i2c_reset_exit;
1472 dc->vmsd = &vmstate_stellaris_i2c;
1473 }
1474
1475 static const TypeInfo stellaris_i2c_info = {
1476 .name = TYPE_STELLARIS_I2C,
1477 .parent = TYPE_SYS_BUS_DEVICE,
1478 .instance_size = sizeof(stellaris_i2c_state),
1479 .instance_init = stellaris_i2c_init,
1480 .class_init = stellaris_i2c_class_init,
1481 };
1482
1483 static void stellaris_adc_class_init(ObjectClass *klass, const void *data)
1484 {
1485 DeviceClass *dc = DEVICE_CLASS(klass);
1486 ResettableClass *rc = RESETTABLE_CLASS(klass);
1487
1488 rc->phases.hold = stellaris_adc_reset_hold;
1489 dc->vmsd = &vmstate_stellaris_adc;
1490 }
1491
1492 static const TypeInfo stellaris_adc_info = {
1493 .name = TYPE_STELLARIS_ADC,
1494 .parent = TYPE_SYS_BUS_DEVICE,
1495 .instance_size = sizeof(StellarisADCState),
1496 .instance_init = stellaris_adc_init,
1497 .class_init = stellaris_adc_class_init,
1498 };
1499
1500 static void stellaris_sys_class_init(ObjectClass *klass, const void *data)
1501 {
1502 DeviceClass *dc = DEVICE_CLASS(klass);
1503 ResettableClass *rc = RESETTABLE_CLASS(klass);
1504
1505 dc->vmsd = &vmstate_stellaris_sys;
1506 rc->phases.enter = stellaris_sys_reset_enter;
1507 rc->phases.hold = stellaris_sys_reset_hold;
1508 rc->phases.exit = stellaris_sys_reset_exit;
1509 device_class_set_props(dc, stellaris_sys_properties);
1510 }
1511
1512 static const TypeInfo stellaris_sys_info = {
1513 .name = TYPE_STELLARIS_SYS,
1514 .parent = TYPE_SYS_BUS_DEVICE,
1515 .instance_size = sizeof(ssys_state),
1516 .instance_init = stellaris_sys_instance_init,
1517 .class_init = stellaris_sys_class_init,
1518 };
1519
1520 static void stellaris_register_types(void)
1521 {
1522 type_register_static(&stellaris_i2c_info);
1523 type_register_static(&stellaris_adc_info);
1524 type_register_static(&stellaris_sys_info);
1525 }
1526
1527 type_init(stellaris_register_types)