| 1 | /* |
| 2 | * STM32F205 SoC |
| 3 | * |
| 4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qapi/error.h" |
| 27 | #include "qemu/module.h" |
| 28 | #include "hw/arm/boot.h" |
| 29 | #include "system/address-spaces.h" |
| 30 | #include "hw/arm/stm32f205_soc.h" |
| 31 | #include "hw/core/qdev-properties.h" |
| 32 | #include "hw/core/qdev-clock.h" |
| 33 | #include "system/system.h" |
| 34 | |
| 35 | /* At the moment only Timer 2 to 5 are modelled */ |
| 36 | static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, |
| 37 | 0x40000800, 0x40000C00 }; |
| 38 | static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, |
| 39 | 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; |
| 40 | static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, |
| 41 | 0x40012200 }; |
| 42 | static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, |
| 43 | 0x40003C00 }; |
| 44 | |
| 45 | static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; |
| 46 | static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; |
| 47 | #define ADC_IRQ 18 |
| 48 | static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; |
| 49 | |
| 50 | static void stm32f205_soc_initfn(Object *obj) |
| 51 | { |
| 52 | STM32F205State *s = STM32F205_SOC(obj); |
| 53 | int i; |
| 54 | |
| 55 | object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); |
| 56 | |
| 57 | object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); |
| 58 | |
| 59 | for (i = 0; i < STM_NUM_USARTS; i++) { |
| 60 | object_initialize_child(obj, "usart[*]", &s->usart[i], |
| 61 | TYPE_STM32F2XX_USART); |
| 62 | } |
| 63 | |
| 64 | for (i = 0; i < STM_NUM_TIMERS; i++) { |
| 65 | object_initialize_child(obj, "timer[*]", &s->timer[i], |
| 66 | TYPE_STM32F2XX_TIMER); |
| 67 | } |
| 68 | |
| 69 | object_initialize_child(obj, "adc-irq-orgate", &s->adc_irqs, TYPE_OR_IRQ); |
| 70 | |
| 71 | for (i = 0; i < STM_NUM_ADCS; i++) { |
| 72 | object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); |
| 73 | } |
| 74 | |
| 75 | for (i = 0; i < STM_NUM_SPIS; i++) { |
| 76 | object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); |
| 77 | } |
| 78 | |
| 79 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); |
| 80 | s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); |
| 81 | } |
| 82 | |
| 83 | static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) |
| 84 | { |
| 85 | STM32F205State *s = STM32F205_SOC(dev_soc); |
| 86 | DeviceState *dev, *armv7m; |
| 87 | SysBusDevice *busdev; |
| 88 | int i; |
| 89 | |
| 90 | MemoryRegion *system_memory = get_system_memory(); |
| 91 | |
| 92 | /* |
| 93 | * We use s->refclk internally and only define it with qdev_init_clock_in() |
| 94 | * so it is correctly parented and not leaked on an init/deinit; it is not |
| 95 | * intended as an externally exposed clock. |
| 96 | */ |
| 97 | if (clock_has_source(s->refclk)) { |
| 98 | error_setg(errp, "refclk clock must not be wired up by the board code"); |
| 99 | return; |
| 100 | } |
| 101 | |
| 102 | if (!clock_has_source(s->sysclk)) { |
| 103 | error_setg(errp, "sysclk clock must be wired up by the board code"); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * TODO: ideally we should model the SoC RCC and its ability to |
| 109 | * change the sysclk frequency and define different sysclk sources. |
| 110 | */ |
| 111 | |
| 112 | /* The refclk always runs at frequency HCLK / 8 */ |
| 113 | clock_set_mul_div(s->refclk, 8, 1); |
| 114 | clock_set_source(s->refclk, s->sysclk); |
| 115 | |
| 116 | memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", |
| 117 | FLASH_SIZE, &error_fatal); |
| 118 | memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), |
| 119 | "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE); |
| 120 | |
| 121 | memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); |
| 122 | memory_region_add_subregion(system_memory, 0, &s->flash_alias); |
| 123 | |
| 124 | memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE, |
| 125 | &error_fatal); |
| 126 | memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); |
| 127 | |
| 128 | armv7m = DEVICE(&s->armv7m); |
| 129 | qdev_prop_set_uint32(armv7m, "num-irq", 96); |
| 130 | qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); |
| 131 | qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); |
| 132 | qdev_prop_set_bit(armv7m, "enable-bitband", true); |
| 133 | qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); |
| 134 | qdev_connect_clock_in(armv7m, "refclk", s->refclk); |
| 135 | object_property_set_link(OBJECT(&s->armv7m), "memory", |
| 136 | OBJECT(get_system_memory()), &error_abort); |
| 137 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { |
| 138 | return; |
| 139 | } |
| 140 | |
| 141 | /* System configuration controller */ |
| 142 | dev = DEVICE(&s->syscfg); |
| 143 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { |
| 144 | return; |
| 145 | } |
| 146 | busdev = SYS_BUS_DEVICE(dev); |
| 147 | sysbus_mmio_map(busdev, 0, 0x40013800); |
| 148 | |
| 149 | /* Attach UART (uses USART registers) and USART controllers */ |
| 150 | for (i = 0; i < STM_NUM_USARTS; i++) { |
| 151 | dev = DEVICE(&(s->usart[i])); |
| 152 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 153 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { |
| 154 | return; |
| 155 | } |
| 156 | busdev = SYS_BUS_DEVICE(dev); |
| 157 | sysbus_mmio_map(busdev, 0, usart_addr[i]); |
| 158 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); |
| 159 | } |
| 160 | |
| 161 | /* Timer 2 to 5 */ |
| 162 | for (i = 0; i < STM_NUM_TIMERS; i++) { |
| 163 | dev = DEVICE(&(s->timer[i])); |
| 164 | qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); |
| 165 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { |
| 166 | return; |
| 167 | } |
| 168 | busdev = SYS_BUS_DEVICE(dev); |
| 169 | sysbus_mmio_map(busdev, 0, timer_addr[i]); |
| 170 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); |
| 171 | } |
| 172 | |
| 173 | /* ADC 1 to 3 */ |
| 174 | object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS, |
| 175 | &error_abort); |
| 176 | if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) { |
| 177 | return; |
| 178 | } |
| 179 | qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, |
| 180 | qdev_get_gpio_in(armv7m, ADC_IRQ)); |
| 181 | |
| 182 | for (i = 0; i < STM_NUM_ADCS; i++) { |
| 183 | dev = DEVICE(&(s->adc[i])); |
| 184 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) { |
| 185 | return; |
| 186 | } |
| 187 | busdev = SYS_BUS_DEVICE(dev); |
| 188 | sysbus_mmio_map(busdev, 0, adc_addr[i]); |
| 189 | sysbus_connect_irq(busdev, 0, |
| 190 | qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); |
| 191 | } |
| 192 | |
| 193 | /* SPI 1 and 2 */ |
| 194 | for (i = 0; i < STM_NUM_SPIS; i++) { |
| 195 | dev = DEVICE(&(s->spi[i])); |
| 196 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
| 197 | return; |
| 198 | } |
| 199 | busdev = SYS_BUS_DEVICE(dev); |
| 200 | sysbus_mmio_map(busdev, 0, spi_addr[i]); |
| 201 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | static void stm32f205_soc_class_init(ObjectClass *klass, const void *data) |
| 206 | { |
| 207 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 208 | |
| 209 | dc->realize = stm32f205_soc_realize; |
| 210 | /* No vmstate or reset required: device has no internal state */ |
| 211 | } |
| 212 | |
| 213 | static const TypeInfo stm32f205_soc_info = { |
| 214 | .name = TYPE_STM32F205_SOC, |
| 215 | .parent = TYPE_SYS_BUS_DEVICE, |
| 216 | .instance_size = sizeof(STM32F205State), |
| 217 | .instance_init = stm32f205_soc_initfn, |
| 218 | .class_init = stm32f205_soc_class_init, |
| 219 | }; |
| 220 | |
| 221 | static void stm32f205_soc_types(void) |
| 222 | { |
| 223 | type_register_static(&stm32f205_soc_info); |
| 224 | } |
| 225 | |
| 226 | type_init(stm32f205_soc_types) |