| 1 | /* |
| 2 | * StrongARM SA-1100/SA-1110 emulation |
| 3 | * |
| 4 | * Copyright (C) 2011 Dmitry Eremin-Solenikov |
| 5 | * |
| 6 | * Largely based on StrongARM emulation: |
| 7 | * Copyright (c) 2006 Openedhand Ltd. |
| 8 | * Written by Andrzej Zaborowski <balrog@zabor.org> |
| 9 | * |
| 10 | * UART code based on QEMU 16550A UART emulation |
| 11 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 12 | * Copyright (c) 2008 Citrix Systems, Inc. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License along |
| 24 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 25 | * |
| 26 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 27 | * GNU GPL, version 2 or (at your option) any later version. |
| 28 | */ |
| 29 | |
| 30 | #include "qemu/osdep.h" |
| 31 | #include "hw/core/irq.h" |
| 32 | #include "hw/core/qdev-properties.h" |
| 33 | #include "hw/core/qdev-properties-system.h" |
| 34 | #include "hw/core/sysbus.h" |
| 35 | #include "migration/vmstate.h" |
| 36 | #include "strongarm.h" |
| 37 | #include "qemu/error-report.h" |
| 38 | #include "hw/arm/boot.h" |
| 39 | #include "chardev/char-fe.h" |
| 40 | #include "chardev/char-serial.h" |
| 41 | #include "system/system.h" |
| 42 | #include "system/rtc.h" |
| 43 | #include "hw/ssi/ssi.h" |
| 44 | #include "qapi/error.h" |
| 45 | #include "qemu/cutils.h" |
| 46 | #include "qemu/log.h" |
| 47 | #include "qom/object.h" |
| 48 | #include "target/arm/cpu-qom.h" |
| 49 | #include "trace.h" |
| 50 | |
| 51 | /* |
| 52 | TODO |
| 53 | - Implement cp15, c14 ? |
| 54 | - Implement cp15, c15 !!! (idle used in L) |
| 55 | - Implement idle mode handling/DIM |
| 56 | - Implement sleep mode/Wake sources |
| 57 | - Implement reset control |
| 58 | - Implement memory control regs |
| 59 | - PCMCIA handling |
| 60 | - Maybe support MBGNT/MBREQ |
| 61 | - DMA channels |
| 62 | - GPCLK |
| 63 | - IrDA |
| 64 | - MCP |
| 65 | - Enhance UART with modem signals |
| 66 | */ |
| 67 | |
| 68 | static struct { |
| 69 | hwaddr io_base; |
| 70 | int irq; |
| 71 | } sa_serial[] = { |
| 72 | { 0x80010000, SA_PIC_UART1 }, |
| 73 | { 0x80030000, SA_PIC_UART2 }, |
| 74 | { 0x80050000, SA_PIC_UART3 }, |
| 75 | { 0, 0 } |
| 76 | }; |
| 77 | |
| 78 | /* Interrupt Controller */ |
| 79 | |
| 80 | #define TYPE_STRONGARM_PIC "strongarm_pic" |
| 81 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPICState, STRONGARM_PIC) |
| 82 | |
| 83 | struct StrongARMPICState { |
| 84 | SysBusDevice parent_obj; |
| 85 | |
| 86 | MemoryRegion iomem; |
| 87 | qemu_irq irq; |
| 88 | qemu_irq fiq; |
| 89 | |
| 90 | uint32_t pending; |
| 91 | uint32_t enabled; |
| 92 | uint32_t is_fiq; |
| 93 | uint32_t int_idle; |
| 94 | }; |
| 95 | |
| 96 | #define ICIP 0x00 |
| 97 | #define ICMR 0x04 |
| 98 | #define ICLR 0x08 |
| 99 | #define ICFP 0x10 |
| 100 | #define ICPR 0x20 |
| 101 | #define ICCR 0x0c |
| 102 | |
| 103 | #define SA_PIC_SRCS 32 |
| 104 | |
| 105 | |
| 106 | static void strongarm_pic_update(void *opaque) |
| 107 | { |
| 108 | StrongARMPICState *s = opaque; |
| 109 | |
| 110 | /* FIXME: reflect DIM */ |
| 111 | qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); |
| 112 | qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); |
| 113 | } |
| 114 | |
| 115 | static void strongarm_pic_set_irq(void *opaque, int irq, int level) |
| 116 | { |
| 117 | StrongARMPICState *s = opaque; |
| 118 | |
| 119 | if (level) { |
| 120 | s->pending |= 1 << irq; |
| 121 | } else { |
| 122 | s->pending &= ~(1 << irq); |
| 123 | } |
| 124 | |
| 125 | strongarm_pic_update(s); |
| 126 | } |
| 127 | |
| 128 | static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, |
| 129 | unsigned size) |
| 130 | { |
| 131 | StrongARMPICState *s = opaque; |
| 132 | |
| 133 | switch (offset) { |
| 134 | case ICIP: |
| 135 | return s->pending & ~s->is_fiq & s->enabled; |
| 136 | case ICMR: |
| 137 | return s->enabled; |
| 138 | case ICLR: |
| 139 | return s->is_fiq; |
| 140 | case ICCR: |
| 141 | return s->int_idle == 0; |
| 142 | case ICFP: |
| 143 | return s->pending & s->is_fiq & s->enabled; |
| 144 | case ICPR: |
| 145 | return s->pending; |
| 146 | default: |
| 147 | qemu_log_mask(LOG_GUEST_ERROR, |
| 148 | "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", |
| 149 | __func__, offset); |
| 150 | return 0; |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | static void strongarm_pic_mem_write(void *opaque, hwaddr offset, |
| 155 | uint64_t value, unsigned size) |
| 156 | { |
| 157 | StrongARMPICState *s = opaque; |
| 158 | |
| 159 | switch (offset) { |
| 160 | case ICMR: |
| 161 | s->enabled = value; |
| 162 | break; |
| 163 | case ICLR: |
| 164 | s->is_fiq = value; |
| 165 | break; |
| 166 | case ICCR: |
| 167 | s->int_idle = (value & 1) ? 0 : ~0; |
| 168 | break; |
| 169 | default: |
| 170 | qemu_log_mask(LOG_GUEST_ERROR, |
| 171 | "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", |
| 172 | __func__, offset); |
| 173 | break; |
| 174 | } |
| 175 | strongarm_pic_update(s); |
| 176 | } |
| 177 | |
| 178 | static const MemoryRegionOps strongarm_pic_ops = { |
| 179 | .read = strongarm_pic_mem_read, |
| 180 | .write = strongarm_pic_mem_write, |
| 181 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 182 | }; |
| 183 | |
| 184 | static void strongarm_pic_initfn(Object *obj) |
| 185 | { |
| 186 | DeviceState *dev = DEVICE(obj); |
| 187 | StrongARMPICState *s = STRONGARM_PIC(obj); |
| 188 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 189 | |
| 190 | qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); |
| 191 | memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, |
| 192 | "pic", 0x1000); |
| 193 | sysbus_init_mmio(sbd, &s->iomem); |
| 194 | sysbus_init_irq(sbd, &s->irq); |
| 195 | sysbus_init_irq(sbd, &s->fiq); |
| 196 | } |
| 197 | |
| 198 | static int strongarm_pic_post_load(void *opaque, int version_id) |
| 199 | { |
| 200 | strongarm_pic_update(opaque); |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | static const VMStateDescription vmstate_strongarm_pic_regs = { |
| 205 | .name = "strongarm_pic", |
| 206 | .version_id = 0, |
| 207 | .minimum_version_id = 0, |
| 208 | .post_load = strongarm_pic_post_load, |
| 209 | .fields = (const VMStateField[]) { |
| 210 | VMSTATE_UINT32(pending, StrongARMPICState), |
| 211 | VMSTATE_UINT32(enabled, StrongARMPICState), |
| 212 | VMSTATE_UINT32(is_fiq, StrongARMPICState), |
| 213 | VMSTATE_UINT32(int_idle, StrongARMPICState), |
| 214 | VMSTATE_END_OF_LIST(), |
| 215 | }, |
| 216 | }; |
| 217 | |
| 218 | static void strongarm_pic_class_init(ObjectClass *klass, const void *data) |
| 219 | { |
| 220 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 221 | |
| 222 | dc->desc = "StrongARM PIC"; |
| 223 | dc->vmsd = &vmstate_strongarm_pic_regs; |
| 224 | } |
| 225 | |
| 226 | static const TypeInfo strongarm_pic_info = { |
| 227 | .name = TYPE_STRONGARM_PIC, |
| 228 | .parent = TYPE_SYS_BUS_DEVICE, |
| 229 | .instance_size = sizeof(StrongARMPICState), |
| 230 | .instance_init = strongarm_pic_initfn, |
| 231 | .class_init = strongarm_pic_class_init, |
| 232 | }; |
| 233 | |
| 234 | /* Real-Time Clock */ |
| 235 | #define RTAR 0x00 /* RTC Alarm register */ |
| 236 | #define RCNR 0x04 /* RTC Counter register */ |
| 237 | #define RTTR 0x08 /* RTC Timer Trim register */ |
| 238 | #define RTSR 0x10 /* RTC Status register */ |
| 239 | |
| 240 | #define RTSR_AL (1 << 0) /* RTC Alarm detected */ |
| 241 | #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */ |
| 242 | #define RTSR_ALE (1 << 2) /* RTC Alarm enable */ |
| 243 | #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ |
| 244 | |
| 245 | /* 16 LSB of RTTR are clockdiv for internal trim logic, |
| 246 | * trim delete isn't emulated, so |
| 247 | * f = 32 768 / (RTTR_trim + 1) */ |
| 248 | |
| 249 | #define TYPE_STRONGARM_RTC "strongarm-rtc" |
| 250 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMRTCState, STRONGARM_RTC) |
| 251 | |
| 252 | struct StrongARMRTCState { |
| 253 | SysBusDevice parent_obj; |
| 254 | |
| 255 | MemoryRegion iomem; |
| 256 | uint32_t rttr; |
| 257 | uint32_t rtsr; |
| 258 | uint32_t rtar; |
| 259 | uint32_t last_rcnr; |
| 260 | int64_t last_hz; |
| 261 | QEMUTimer *rtc_alarm; |
| 262 | QEMUTimer *rtc_hz; |
| 263 | qemu_irq rtc_irq; |
| 264 | qemu_irq rtc_hz_irq; |
| 265 | }; |
| 266 | |
| 267 | static inline void strongarm_rtc_int_update(StrongARMRTCState *s) |
| 268 | { |
| 269 | qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); |
| 270 | qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); |
| 271 | } |
| 272 | |
| 273 | static void strongarm_rtc_hzupdate(StrongARMRTCState *s) |
| 274 | { |
| 275 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
| 276 | s->last_rcnr += ((rt - s->last_hz) << 15) / |
| 277 | (1000 * ((s->rttr & 0xffff) + 1)); |
| 278 | s->last_hz = rt; |
| 279 | } |
| 280 | |
| 281 | static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) |
| 282 | { |
| 283 | if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { |
| 284 | timer_mod(s->rtc_hz, s->last_hz + 1000); |
| 285 | } else { |
| 286 | timer_del(s->rtc_hz); |
| 287 | } |
| 288 | |
| 289 | if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { |
| 290 | timer_mod(s->rtc_alarm, s->last_hz + |
| 291 | (((s->rtar - s->last_rcnr) * 1000 * |
| 292 | ((s->rttr & 0xffff) + 1)) >> 15)); |
| 293 | } else { |
| 294 | timer_del(s->rtc_alarm); |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | static inline void strongarm_rtc_alarm_tick(void *opaque) |
| 299 | { |
| 300 | StrongARMRTCState *s = opaque; |
| 301 | s->rtsr |= RTSR_AL; |
| 302 | strongarm_rtc_timer_update(s); |
| 303 | strongarm_rtc_int_update(s); |
| 304 | } |
| 305 | |
| 306 | static inline void strongarm_rtc_hz_tick(void *opaque) |
| 307 | { |
| 308 | StrongARMRTCState *s = opaque; |
| 309 | s->rtsr |= RTSR_HZ; |
| 310 | strongarm_rtc_timer_update(s); |
| 311 | strongarm_rtc_int_update(s); |
| 312 | } |
| 313 | |
| 314 | static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, |
| 315 | unsigned size) |
| 316 | { |
| 317 | StrongARMRTCState *s = opaque; |
| 318 | |
| 319 | switch (addr) { |
| 320 | case RTTR: |
| 321 | return s->rttr; |
| 322 | case RTSR: |
| 323 | return s->rtsr; |
| 324 | case RTAR: |
| 325 | return s->rtar; |
| 326 | case RCNR: |
| 327 | return s->last_rcnr + |
| 328 | ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / |
| 329 | (1000 * ((s->rttr & 0xffff) + 1)); |
| 330 | default: |
| 331 | qemu_log_mask(LOG_GUEST_ERROR, |
| 332 | "%s: Bad rtc register read 0x"HWADDR_FMT_plx"\n", |
| 333 | __func__, addr); |
| 334 | return 0; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | static void strongarm_rtc_write(void *opaque, hwaddr addr, |
| 339 | uint64_t value, unsigned size) |
| 340 | { |
| 341 | StrongARMRTCState *s = opaque; |
| 342 | uint32_t old_rtsr; |
| 343 | |
| 344 | switch (addr) { |
| 345 | case RTTR: |
| 346 | strongarm_rtc_hzupdate(s); |
| 347 | s->rttr = value; |
| 348 | strongarm_rtc_timer_update(s); |
| 349 | break; |
| 350 | |
| 351 | case RTSR: |
| 352 | old_rtsr = s->rtsr; |
| 353 | s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | |
| 354 | (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); |
| 355 | |
| 356 | if (s->rtsr != old_rtsr) { |
| 357 | strongarm_rtc_timer_update(s); |
| 358 | } |
| 359 | |
| 360 | strongarm_rtc_int_update(s); |
| 361 | break; |
| 362 | |
| 363 | case RTAR: |
| 364 | s->rtar = value; |
| 365 | strongarm_rtc_timer_update(s); |
| 366 | break; |
| 367 | |
| 368 | case RCNR: |
| 369 | strongarm_rtc_hzupdate(s); |
| 370 | s->last_rcnr = value; |
| 371 | strongarm_rtc_timer_update(s); |
| 372 | break; |
| 373 | |
| 374 | default: |
| 375 | qemu_log_mask(LOG_GUEST_ERROR, |
| 376 | "%s: Bad rtc register write 0x"HWADDR_FMT_plx"\n", |
| 377 | __func__, addr); |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | static const MemoryRegionOps strongarm_rtc_ops = { |
| 382 | .read = strongarm_rtc_read, |
| 383 | .write = strongarm_rtc_write, |
| 384 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 385 | }; |
| 386 | |
| 387 | static void strongarm_rtc_init(Object *obj) |
| 388 | { |
| 389 | StrongARMRTCState *s = STRONGARM_RTC(obj); |
| 390 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
| 391 | struct tm tm; |
| 392 | |
| 393 | s->rttr = 0x0; |
| 394 | s->rtsr = 0; |
| 395 | |
| 396 | qemu_get_timedate(&tm, 0); |
| 397 | |
| 398 | s->last_rcnr = (uint32_t) mktimegm(&tm); |
| 399 | s->last_hz = qemu_clock_get_ms(rtc_clock); |
| 400 | |
| 401 | sysbus_init_irq(dev, &s->rtc_irq); |
| 402 | sysbus_init_irq(dev, &s->rtc_hz_irq); |
| 403 | |
| 404 | memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, |
| 405 | "rtc", 0x10000); |
| 406 | sysbus_init_mmio(dev, &s->iomem); |
| 407 | } |
| 408 | |
| 409 | static void strongarm_rtc_realize(DeviceState *dev, Error **errp) |
| 410 | { |
| 411 | StrongARMRTCState *s = STRONGARM_RTC(dev); |
| 412 | s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); |
| 413 | s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); |
| 414 | } |
| 415 | |
| 416 | static int strongarm_rtc_pre_save(void *opaque) |
| 417 | { |
| 418 | StrongARMRTCState *s = opaque; |
| 419 | |
| 420 | strongarm_rtc_hzupdate(s); |
| 421 | |
| 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | static int strongarm_rtc_post_load(void *opaque, int version_id) |
| 426 | { |
| 427 | StrongARMRTCState *s = opaque; |
| 428 | |
| 429 | strongarm_rtc_timer_update(s); |
| 430 | strongarm_rtc_int_update(s); |
| 431 | |
| 432 | return 0; |
| 433 | } |
| 434 | |
| 435 | static const VMStateDescription vmstate_strongarm_rtc_regs = { |
| 436 | .name = "strongarm-rtc", |
| 437 | .version_id = 0, |
| 438 | .minimum_version_id = 0, |
| 439 | .pre_save = strongarm_rtc_pre_save, |
| 440 | .post_load = strongarm_rtc_post_load, |
| 441 | .fields = (const VMStateField[]) { |
| 442 | VMSTATE_UINT32(rttr, StrongARMRTCState), |
| 443 | VMSTATE_UINT32(rtsr, StrongARMRTCState), |
| 444 | VMSTATE_UINT32(rtar, StrongARMRTCState), |
| 445 | VMSTATE_UINT32(last_rcnr, StrongARMRTCState), |
| 446 | VMSTATE_INT64(last_hz, StrongARMRTCState), |
| 447 | VMSTATE_END_OF_LIST(), |
| 448 | }, |
| 449 | }; |
| 450 | |
| 451 | static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, |
| 452 | const void *data) |
| 453 | { |
| 454 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 455 | |
| 456 | dc->desc = "StrongARM RTC Controller"; |
| 457 | dc->vmsd = &vmstate_strongarm_rtc_regs; |
| 458 | dc->realize = strongarm_rtc_realize; |
| 459 | } |
| 460 | |
| 461 | static const TypeInfo strongarm_rtc_sysbus_info = { |
| 462 | .name = TYPE_STRONGARM_RTC, |
| 463 | .parent = TYPE_SYS_BUS_DEVICE, |
| 464 | .instance_size = sizeof(StrongARMRTCState), |
| 465 | .instance_init = strongarm_rtc_init, |
| 466 | .class_init = strongarm_rtc_sysbus_class_init, |
| 467 | }; |
| 468 | |
| 469 | /* GPIO */ |
| 470 | #define GPLR 0x00 |
| 471 | #define GPDR 0x04 |
| 472 | #define GPSR 0x08 |
| 473 | #define GPCR 0x0c |
| 474 | #define GRER 0x10 |
| 475 | #define GFER 0x14 |
| 476 | #define GEDR 0x18 |
| 477 | #define GAFR 0x1c |
| 478 | |
| 479 | #define TYPE_STRONGARM_GPIO "strongarm-gpio" |
| 480 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMGPIOInfo, STRONGARM_GPIO) |
| 481 | |
| 482 | struct StrongARMGPIOInfo { |
| 483 | SysBusDevice busdev; |
| 484 | MemoryRegion iomem; |
| 485 | qemu_irq handler[28]; |
| 486 | qemu_irq irqs[11]; |
| 487 | qemu_irq irqX; |
| 488 | |
| 489 | uint32_t ilevel; |
| 490 | uint32_t olevel; |
| 491 | uint32_t dir; |
| 492 | uint32_t rising; |
| 493 | uint32_t falling; |
| 494 | uint32_t status; |
| 495 | uint32_t gafr; |
| 496 | |
| 497 | uint32_t prev_level; |
| 498 | }; |
| 499 | |
| 500 | |
| 501 | static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) |
| 502 | { |
| 503 | int i; |
| 504 | for (i = 0; i < 11; i++) { |
| 505 | qemu_set_irq(s->irqs[i], s->status & (1 << i)); |
| 506 | } |
| 507 | |
| 508 | qemu_set_irq(s->irqX, (s->status & ~0x7ff)); |
| 509 | } |
| 510 | |
| 511 | static void strongarm_gpio_set(void *opaque, int line, int level) |
| 512 | { |
| 513 | StrongARMGPIOInfo *s = opaque; |
| 514 | uint32_t mask; |
| 515 | |
| 516 | mask = 1 << line; |
| 517 | |
| 518 | if (level) { |
| 519 | s->status |= s->rising & mask & |
| 520 | ~s->ilevel & ~s->dir; |
| 521 | s->ilevel |= mask; |
| 522 | } else { |
| 523 | s->status |= s->falling & mask & |
| 524 | s->ilevel & ~s->dir; |
| 525 | s->ilevel &= ~mask; |
| 526 | } |
| 527 | |
| 528 | if (s->status & mask) { |
| 529 | strongarm_gpio_irq_update(s); |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) |
| 534 | { |
| 535 | uint32_t level, diff; |
| 536 | int bit; |
| 537 | |
| 538 | level = s->olevel & s->dir; |
| 539 | |
| 540 | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
| 541 | bit = ctz32(diff); |
| 542 | qemu_set_irq(s->handler[bit], (level >> bit) & 1); |
| 543 | } |
| 544 | |
| 545 | s->prev_level = level; |
| 546 | } |
| 547 | |
| 548 | static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, |
| 549 | unsigned size) |
| 550 | { |
| 551 | StrongARMGPIOInfo *s = opaque; |
| 552 | |
| 553 | switch (offset) { |
| 554 | case GPDR: /* GPIO Pin-Direction registers */ |
| 555 | return s->dir; |
| 556 | |
| 557 | case GPSR: /* GPIO Pin-Output Set registers */ |
| 558 | qemu_log_mask(LOG_GUEST_ERROR, |
| 559 | "%s: read from write only register GPSR\n", __func__); |
| 560 | return 0; |
| 561 | |
| 562 | case GPCR: /* GPIO Pin-Output Clear registers */ |
| 563 | qemu_log_mask(LOG_GUEST_ERROR, |
| 564 | "%s: read from write only register GPCR\n", __func__); |
| 565 | return 0; |
| 566 | |
| 567 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
| 568 | return s->rising; |
| 569 | |
| 570 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
| 571 | return s->falling; |
| 572 | |
| 573 | case GAFR: /* GPIO Alternate Function registers */ |
| 574 | return s->gafr; |
| 575 | |
| 576 | case GPLR: /* GPIO Pin-Level registers */ |
| 577 | return (s->olevel & s->dir) | |
| 578 | (s->ilevel & ~s->dir); |
| 579 | |
| 580 | case GEDR: /* GPIO Edge Detect Status registers */ |
| 581 | return s->status; |
| 582 | |
| 583 | default: |
| 584 | qemu_log_mask(LOG_GUEST_ERROR, |
| 585 | "%s: Bad gpio read offset 0x"HWADDR_FMT_plx"\n", |
| 586 | __func__, offset); |
| 587 | } |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static void strongarm_gpio_write(void *opaque, hwaddr offset, |
| 593 | uint64_t value, unsigned size) |
| 594 | { |
| 595 | StrongARMGPIOInfo *s = opaque; |
| 596 | |
| 597 | switch (offset) { |
| 598 | case GPDR: /* GPIO Pin-Direction registers */ |
| 599 | s->dir = value & 0x0fffffff; |
| 600 | strongarm_gpio_handler_update(s); |
| 601 | break; |
| 602 | |
| 603 | case GPSR: /* GPIO Pin-Output Set registers */ |
| 604 | s->olevel |= value & 0x0fffffff; |
| 605 | strongarm_gpio_handler_update(s); |
| 606 | break; |
| 607 | |
| 608 | case GPCR: /* GPIO Pin-Output Clear registers */ |
| 609 | s->olevel &= ~value; |
| 610 | strongarm_gpio_handler_update(s); |
| 611 | break; |
| 612 | |
| 613 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
| 614 | s->rising = value; |
| 615 | break; |
| 616 | |
| 617 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
| 618 | s->falling = value; |
| 619 | break; |
| 620 | |
| 621 | case GAFR: /* GPIO Alternate Function registers */ |
| 622 | s->gafr = value; |
| 623 | break; |
| 624 | |
| 625 | case GEDR: /* GPIO Edge Detect Status registers */ |
| 626 | s->status &= ~value; |
| 627 | strongarm_gpio_irq_update(s); |
| 628 | break; |
| 629 | |
| 630 | default: |
| 631 | qemu_log_mask(LOG_GUEST_ERROR, |
| 632 | "%s: Bad write offset 0x"HWADDR_FMT_plx"\n", |
| 633 | __func__, offset); |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | static const MemoryRegionOps strongarm_gpio_ops = { |
| 638 | .read = strongarm_gpio_read, |
| 639 | .write = strongarm_gpio_write, |
| 640 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 641 | }; |
| 642 | |
| 643 | static DeviceState *strongarm_gpio_init(hwaddr base, |
| 644 | DeviceState *pic) |
| 645 | { |
| 646 | DeviceState *dev; |
| 647 | int i; |
| 648 | |
| 649 | dev = qdev_new(TYPE_STRONGARM_GPIO); |
| 650 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 651 | |
| 652 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 653 | for (i = 0; i < 12; i++) |
| 654 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
| 655 | qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i)); |
| 656 | |
| 657 | return dev; |
| 658 | } |
| 659 | |
| 660 | static void strongarm_gpio_initfn(Object *obj) |
| 661 | { |
| 662 | DeviceState *dev = DEVICE(obj); |
| 663 | StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); |
| 664 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 665 | int i; |
| 666 | |
| 667 | qdev_init_gpio_in(dev, strongarm_gpio_set, 28); |
| 668 | qdev_init_gpio_out(dev, s->handler, 28); |
| 669 | |
| 670 | memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, |
| 671 | "gpio", 0x1000); |
| 672 | |
| 673 | sysbus_init_mmio(sbd, &s->iomem); |
| 674 | for (i = 0; i < 11; i++) { |
| 675 | sysbus_init_irq(sbd, &s->irqs[i]); |
| 676 | } |
| 677 | sysbus_init_irq(sbd, &s->irqX); |
| 678 | } |
| 679 | |
| 680 | static const VMStateDescription vmstate_strongarm_gpio_regs = { |
| 681 | .name = "strongarm-gpio", |
| 682 | .version_id = 0, |
| 683 | .minimum_version_id = 0, |
| 684 | .fields = (const VMStateField[]) { |
| 685 | VMSTATE_UINT32(ilevel, StrongARMGPIOInfo), |
| 686 | VMSTATE_UINT32(olevel, StrongARMGPIOInfo), |
| 687 | VMSTATE_UINT32(dir, StrongARMGPIOInfo), |
| 688 | VMSTATE_UINT32(rising, StrongARMGPIOInfo), |
| 689 | VMSTATE_UINT32(falling, StrongARMGPIOInfo), |
| 690 | VMSTATE_UINT32(status, StrongARMGPIOInfo), |
| 691 | VMSTATE_UINT32(gafr, StrongARMGPIOInfo), |
| 692 | VMSTATE_UINT32(prev_level, StrongARMGPIOInfo), |
| 693 | VMSTATE_END_OF_LIST(), |
| 694 | }, |
| 695 | }; |
| 696 | |
| 697 | static void strongarm_gpio_class_init(ObjectClass *klass, const void *data) |
| 698 | { |
| 699 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 700 | |
| 701 | dc->desc = "StrongARM GPIO controller"; |
| 702 | dc->vmsd = &vmstate_strongarm_gpio_regs; |
| 703 | } |
| 704 | |
| 705 | static const TypeInfo strongarm_gpio_info = { |
| 706 | .name = TYPE_STRONGARM_GPIO, |
| 707 | .parent = TYPE_SYS_BUS_DEVICE, |
| 708 | .instance_size = sizeof(StrongARMGPIOInfo), |
| 709 | .instance_init = strongarm_gpio_initfn, |
| 710 | .class_init = strongarm_gpio_class_init, |
| 711 | }; |
| 712 | |
| 713 | /* Peripheral Pin Controller */ |
| 714 | #define PPDR 0x00 |
| 715 | #define PPSR 0x04 |
| 716 | #define PPAR 0x08 |
| 717 | #define PSDR 0x0c |
| 718 | #define PPFR 0x10 |
| 719 | |
| 720 | #define TYPE_STRONGARM_PPC "strongarm-ppc" |
| 721 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPPCInfo, STRONGARM_PPC) |
| 722 | |
| 723 | struct StrongARMPPCInfo { |
| 724 | SysBusDevice parent_obj; |
| 725 | |
| 726 | MemoryRegion iomem; |
| 727 | qemu_irq handler[28]; |
| 728 | |
| 729 | uint32_t ilevel; |
| 730 | uint32_t olevel; |
| 731 | uint32_t dir; |
| 732 | uint32_t ppar; |
| 733 | uint32_t psdr; |
| 734 | uint32_t ppfr; |
| 735 | |
| 736 | uint32_t prev_level; |
| 737 | }; |
| 738 | |
| 739 | static void strongarm_ppc_set(void *opaque, int line, int level) |
| 740 | { |
| 741 | StrongARMPPCInfo *s = opaque; |
| 742 | |
| 743 | if (level) { |
| 744 | s->ilevel |= 1 << line; |
| 745 | } else { |
| 746 | s->ilevel &= ~(1 << line); |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) |
| 751 | { |
| 752 | uint32_t level, diff; |
| 753 | int bit; |
| 754 | |
| 755 | level = s->olevel & s->dir; |
| 756 | |
| 757 | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
| 758 | bit = ctz32(diff); |
| 759 | qemu_set_irq(s->handler[bit], (level >> bit) & 1); |
| 760 | } |
| 761 | |
| 762 | s->prev_level = level; |
| 763 | } |
| 764 | |
| 765 | static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, |
| 766 | unsigned size) |
| 767 | { |
| 768 | StrongARMPPCInfo *s = opaque; |
| 769 | |
| 770 | switch (offset) { |
| 771 | case PPDR: /* PPC Pin Direction registers */ |
| 772 | return s->dir | ~0x3fffff; |
| 773 | |
| 774 | case PPSR: /* PPC Pin State registers */ |
| 775 | return (s->olevel & s->dir) | |
| 776 | (s->ilevel & ~s->dir) | |
| 777 | ~0x3fffff; |
| 778 | |
| 779 | case PPAR: |
| 780 | return s->ppar | ~0x41000; |
| 781 | |
| 782 | case PSDR: |
| 783 | return s->psdr; |
| 784 | |
| 785 | case PPFR: |
| 786 | return s->ppfr | ~0x7f001; |
| 787 | |
| 788 | default: |
| 789 | qemu_log_mask(LOG_GUEST_ERROR, |
| 790 | "%s: Bad ppc read offset 0x"HWADDR_FMT_plx "\n", |
| 791 | __func__, offset); |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | static void strongarm_ppc_write(void *opaque, hwaddr offset, |
| 798 | uint64_t value, unsigned size) |
| 799 | { |
| 800 | StrongARMPPCInfo *s = opaque; |
| 801 | |
| 802 | switch (offset) { |
| 803 | case PPDR: /* PPC Pin Direction registers */ |
| 804 | s->dir = value & 0x3fffff; |
| 805 | strongarm_ppc_handler_update(s); |
| 806 | break; |
| 807 | |
| 808 | case PPSR: /* PPC Pin State registers */ |
| 809 | s->olevel = value & s->dir & 0x3fffff; |
| 810 | strongarm_ppc_handler_update(s); |
| 811 | break; |
| 812 | |
| 813 | case PPAR: |
| 814 | s->ppar = value & 0x41000; |
| 815 | break; |
| 816 | |
| 817 | case PSDR: |
| 818 | s->psdr = value & 0x3fffff; |
| 819 | break; |
| 820 | |
| 821 | case PPFR: |
| 822 | s->ppfr = value & 0x7f001; |
| 823 | break; |
| 824 | |
| 825 | default: |
| 826 | qemu_log_mask(LOG_GUEST_ERROR, |
| 827 | "%s: Bad ppc write offset 0x"HWADDR_FMT_plx"\n", |
| 828 | __func__, offset); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | static const MemoryRegionOps strongarm_ppc_ops = { |
| 833 | .read = strongarm_ppc_read, |
| 834 | .write = strongarm_ppc_write, |
| 835 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 836 | }; |
| 837 | |
| 838 | static void strongarm_ppc_init(Object *obj) |
| 839 | { |
| 840 | DeviceState *dev = DEVICE(obj); |
| 841 | StrongARMPPCInfo *s = STRONGARM_PPC(obj); |
| 842 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 843 | |
| 844 | qdev_init_gpio_in(dev, strongarm_ppc_set, 22); |
| 845 | qdev_init_gpio_out(dev, s->handler, 22); |
| 846 | |
| 847 | memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, |
| 848 | "ppc", 0x1000); |
| 849 | |
| 850 | sysbus_init_mmio(sbd, &s->iomem); |
| 851 | } |
| 852 | |
| 853 | static const VMStateDescription vmstate_strongarm_ppc_regs = { |
| 854 | .name = "strongarm-ppc", |
| 855 | .version_id = 0, |
| 856 | .minimum_version_id = 0, |
| 857 | .fields = (const VMStateField[]) { |
| 858 | VMSTATE_UINT32(ilevel, StrongARMPPCInfo), |
| 859 | VMSTATE_UINT32(olevel, StrongARMPPCInfo), |
| 860 | VMSTATE_UINT32(dir, StrongARMPPCInfo), |
| 861 | VMSTATE_UINT32(ppar, StrongARMPPCInfo), |
| 862 | VMSTATE_UINT32(psdr, StrongARMPPCInfo), |
| 863 | VMSTATE_UINT32(ppfr, StrongARMPPCInfo), |
| 864 | VMSTATE_UINT32(prev_level, StrongARMPPCInfo), |
| 865 | VMSTATE_END_OF_LIST(), |
| 866 | }, |
| 867 | }; |
| 868 | |
| 869 | static void strongarm_ppc_class_init(ObjectClass *klass, const void *data) |
| 870 | { |
| 871 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 872 | |
| 873 | dc->desc = "StrongARM PPC controller"; |
| 874 | dc->vmsd = &vmstate_strongarm_ppc_regs; |
| 875 | } |
| 876 | |
| 877 | static const TypeInfo strongarm_ppc_info = { |
| 878 | .name = TYPE_STRONGARM_PPC, |
| 879 | .parent = TYPE_SYS_BUS_DEVICE, |
| 880 | .instance_size = sizeof(StrongARMPPCInfo), |
| 881 | .instance_init = strongarm_ppc_init, |
| 882 | .class_init = strongarm_ppc_class_init, |
| 883 | }; |
| 884 | |
| 885 | /* UART Ports */ |
| 886 | #define UTCR0 0x00 |
| 887 | #define UTCR1 0x04 |
| 888 | #define UTCR2 0x08 |
| 889 | #define UTCR3 0x0c |
| 890 | #define UTDR 0x14 |
| 891 | #define UTSR0 0x1c |
| 892 | #define UTSR1 0x20 |
| 893 | |
| 894 | #define UTCR0_PE (1 << 0) /* Parity enable */ |
| 895 | #define UTCR0_OES (1 << 1) /* Even parity */ |
| 896 | #define UTCR0_SBS (1 << 2) /* 2 stop bits */ |
| 897 | #define UTCR0_DSS (1 << 3) /* 8-bit data */ |
| 898 | |
| 899 | #define UTCR3_RXE (1 << 0) /* Rx enable */ |
| 900 | #define UTCR3_TXE (1 << 1) /* Tx enable */ |
| 901 | #define UTCR3_BRK (1 << 2) /* Force Break */ |
| 902 | #define UTCR3_RIE (1 << 3) /* Rx int enable */ |
| 903 | #define UTCR3_TIE (1 << 4) /* Tx int enable */ |
| 904 | #define UTCR3_LBM (1 << 5) /* Loopback */ |
| 905 | |
| 906 | #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */ |
| 907 | #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */ |
| 908 | #define UTSR0_RID (1 << 2) /* Receiver Idle */ |
| 909 | #define UTSR0_RBB (1 << 3) /* Receiver begin break */ |
| 910 | #define UTSR0_REB (1 << 4) /* Receiver end break */ |
| 911 | #define UTSR0_EIF (1 << 5) /* Error in FIFO */ |
| 912 | |
| 913 | #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */ |
| 914 | #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */ |
| 915 | #define UTSR1_PRE (1 << 3) /* Parity error */ |
| 916 | #define UTSR1_FRE (1 << 4) /* Frame error */ |
| 917 | #define UTSR1_ROR (1 << 5) /* Receive Over Run */ |
| 918 | |
| 919 | #define RX_FIFO_PRE (1 << 8) |
| 920 | #define RX_FIFO_FRE (1 << 9) |
| 921 | #define RX_FIFO_ROR (1 << 10) |
| 922 | |
| 923 | #define TYPE_STRONGARM_UART "strongarm-uart" |
| 924 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMUARTState, STRONGARM_UART) |
| 925 | |
| 926 | struct StrongARMUARTState { |
| 927 | SysBusDevice parent_obj; |
| 928 | |
| 929 | MemoryRegion iomem; |
| 930 | CharFrontend chr; |
| 931 | qemu_irq irq; |
| 932 | |
| 933 | uint8_t utcr0; |
| 934 | uint16_t brd; |
| 935 | uint8_t utcr3; |
| 936 | uint8_t utsr0; |
| 937 | uint8_t utsr1; |
| 938 | |
| 939 | uint8_t tx_fifo[8]; |
| 940 | uint8_t tx_start; |
| 941 | uint8_t tx_len; |
| 942 | uint16_t rx_fifo[12]; /* value + error flags in high bits */ |
| 943 | uint8_t rx_start; |
| 944 | uint8_t rx_len; |
| 945 | |
| 946 | uint64_t char_transmit_time; /* time to transmit a char in nanoseconds */ |
| 947 | bool wait_break_end; |
| 948 | QEMUTimer *rx_timeout_timer; |
| 949 | QEMUTimer *tx_timer; |
| 950 | }; |
| 951 | |
| 952 | static void strongarm_uart_update_status(StrongARMUARTState *s) |
| 953 | { |
| 954 | uint16_t utsr1 = 0; |
| 955 | |
| 956 | if (s->tx_len != 8) { |
| 957 | utsr1 |= UTSR1_TNF; |
| 958 | } |
| 959 | |
| 960 | if (s->rx_len != 0) { |
| 961 | uint16_t ent = s->rx_fifo[s->rx_start]; |
| 962 | |
| 963 | utsr1 |= UTSR1_RNE; |
| 964 | if (ent & RX_FIFO_PRE) { |
| 965 | s->utsr1 |= UTSR1_PRE; |
| 966 | } |
| 967 | if (ent & RX_FIFO_FRE) { |
| 968 | s->utsr1 |= UTSR1_FRE; |
| 969 | } |
| 970 | if (ent & RX_FIFO_ROR) { |
| 971 | s->utsr1 |= UTSR1_ROR; |
| 972 | } |
| 973 | } |
| 974 | |
| 975 | s->utsr1 = utsr1; |
| 976 | } |
| 977 | |
| 978 | static void strongarm_uart_update_int_status(StrongARMUARTState *s) |
| 979 | { |
| 980 | uint16_t utsr0 = s->utsr0 & |
| 981 | (UTSR0_REB | UTSR0_RBB | UTSR0_RID); |
| 982 | int i; |
| 983 | |
| 984 | if ((s->utcr3 & UTCR3_TXE) && |
| 985 | (s->utcr3 & UTCR3_TIE) && |
| 986 | s->tx_len <= 4) { |
| 987 | utsr0 |= UTSR0_TFS; |
| 988 | } |
| 989 | |
| 990 | if ((s->utcr3 & UTCR3_RXE) && |
| 991 | (s->utcr3 & UTCR3_RIE) && |
| 992 | s->rx_len > 4) { |
| 993 | utsr0 |= UTSR0_RFS; |
| 994 | } |
| 995 | |
| 996 | for (i = 0; i < s->rx_len && i < 4; i++) |
| 997 | if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { |
| 998 | utsr0 |= UTSR0_EIF; |
| 999 | break; |
| 1000 | } |
| 1001 | |
| 1002 | s->utsr0 = utsr0; |
| 1003 | qemu_set_irq(s->irq, utsr0); |
| 1004 | } |
| 1005 | |
| 1006 | static void strongarm_uart_update_parameters(StrongARMUARTState *s) |
| 1007 | { |
| 1008 | int speed, parity, data_bits, stop_bits, frame_size; |
| 1009 | QEMUSerialSetParams ssp; |
| 1010 | |
| 1011 | /* Start bit. */ |
| 1012 | frame_size = 1; |
| 1013 | if (s->utcr0 & UTCR0_PE) { |
| 1014 | /* Parity bit. */ |
| 1015 | frame_size++; |
| 1016 | if (s->utcr0 & UTCR0_OES) { |
| 1017 | parity = 'E'; |
| 1018 | } else { |
| 1019 | parity = 'O'; |
| 1020 | } |
| 1021 | } else { |
| 1022 | parity = 'N'; |
| 1023 | } |
| 1024 | if (s->utcr0 & UTCR0_SBS) { |
| 1025 | stop_bits = 2; |
| 1026 | } else { |
| 1027 | stop_bits = 1; |
| 1028 | } |
| 1029 | |
| 1030 | data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; |
| 1031 | frame_size += data_bits + stop_bits; |
| 1032 | speed = 3686400 / 16 / (s->brd + 1); |
| 1033 | ssp.speed = speed; |
| 1034 | ssp.parity = parity; |
| 1035 | ssp.data_bits = data_bits; |
| 1036 | ssp.stop_bits = stop_bits; |
| 1037 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; |
| 1038 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 1039 | |
| 1040 | trace_strongarm_uart_update_parameters((s->chr.chr ? |
| 1041 | s->chr.chr->label : "NULL") ?: |
| 1042 | "NULL", |
| 1043 | speed, |
| 1044 | parity, |
| 1045 | data_bits, |
| 1046 | stop_bits); |
| 1047 | } |
| 1048 | |
| 1049 | static void strongarm_uart_rx_to(void *opaque) |
| 1050 | { |
| 1051 | StrongARMUARTState *s = opaque; |
| 1052 | |
| 1053 | if (s->rx_len) { |
| 1054 | s->utsr0 |= UTSR0_RID; |
| 1055 | strongarm_uart_update_int_status(s); |
| 1056 | } |
| 1057 | } |
| 1058 | |
| 1059 | static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) |
| 1060 | { |
| 1061 | if ((s->utcr3 & UTCR3_RXE) == 0) { |
| 1062 | /* rx disabled */ |
| 1063 | return; |
| 1064 | } |
| 1065 | |
| 1066 | if (s->wait_break_end) { |
| 1067 | s->utsr0 |= UTSR0_REB; |
| 1068 | s->wait_break_end = false; |
| 1069 | } |
| 1070 | |
| 1071 | if (s->rx_len < 12) { |
| 1072 | s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; |
| 1073 | s->rx_len++; |
| 1074 | } else |
| 1075 | s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; |
| 1076 | } |
| 1077 | |
| 1078 | static int strongarm_uart_can_receive(void *opaque) |
| 1079 | { |
| 1080 | StrongARMUARTState *s = opaque; |
| 1081 | |
| 1082 | if (s->rx_len == 12) { |
| 1083 | return 0; |
| 1084 | } |
| 1085 | /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ |
| 1086 | if (s->rx_len < 8) { |
| 1087 | return 8 - s->rx_len; |
| 1088 | } |
| 1089 | return 1; |
| 1090 | } |
| 1091 | |
| 1092 | static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) |
| 1093 | { |
| 1094 | StrongARMUARTState *s = opaque; |
| 1095 | int i; |
| 1096 | |
| 1097 | for (i = 0; i < size; i++) { |
| 1098 | strongarm_uart_rx_push(s, buf[i]); |
| 1099 | } |
| 1100 | |
| 1101 | /* call the timeout receive callback in 3 char transmit time */ |
| 1102 | timer_mod(s->rx_timeout_timer, |
| 1103 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); |
| 1104 | |
| 1105 | strongarm_uart_update_status(s); |
| 1106 | strongarm_uart_update_int_status(s); |
| 1107 | } |
| 1108 | |
| 1109 | static void strongarm_uart_event(void *opaque, QEMUChrEvent event) |
| 1110 | { |
| 1111 | StrongARMUARTState *s = opaque; |
| 1112 | if (event == CHR_EVENT_BREAK) { |
| 1113 | s->utsr0 |= UTSR0_RBB; |
| 1114 | strongarm_uart_rx_push(s, RX_FIFO_FRE); |
| 1115 | s->wait_break_end = true; |
| 1116 | strongarm_uart_update_status(s); |
| 1117 | strongarm_uart_update_int_status(s); |
| 1118 | } |
| 1119 | } |
| 1120 | |
| 1121 | static void strongarm_uart_tx(void *opaque) |
| 1122 | { |
| 1123 | StrongARMUARTState *s = opaque; |
| 1124 | uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 1125 | |
| 1126 | if (s->utcr3 & UTCR3_LBM) /* loopback */ { |
| 1127 | strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); |
| 1128 | } else if (qemu_chr_fe_backend_connected(&s->chr)) { |
| 1129 | /* XXX this blocks entire thread. Rewrite to use |
| 1130 | * qemu_chr_fe_write and background I/O callbacks */ |
| 1131 | qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); |
| 1132 | } |
| 1133 | |
| 1134 | s->tx_start = (s->tx_start + 1) % 8; |
| 1135 | s->tx_len--; |
| 1136 | if (s->tx_len) { |
| 1137 | timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); |
| 1138 | } |
| 1139 | strongarm_uart_update_status(s); |
| 1140 | strongarm_uart_update_int_status(s); |
| 1141 | } |
| 1142 | |
| 1143 | static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, |
| 1144 | unsigned size) |
| 1145 | { |
| 1146 | StrongARMUARTState *s = opaque; |
| 1147 | uint16_t ret; |
| 1148 | |
| 1149 | switch (addr) { |
| 1150 | case UTCR0: |
| 1151 | return s->utcr0; |
| 1152 | |
| 1153 | case UTCR1: |
| 1154 | return s->brd >> 8; |
| 1155 | |
| 1156 | case UTCR2: |
| 1157 | return s->brd & 0xff; |
| 1158 | |
| 1159 | case UTCR3: |
| 1160 | return s->utcr3; |
| 1161 | |
| 1162 | case UTDR: |
| 1163 | if (s->rx_len != 0) { |
| 1164 | ret = s->rx_fifo[s->rx_start]; |
| 1165 | s->rx_start = (s->rx_start + 1) % 12; |
| 1166 | s->rx_len--; |
| 1167 | strongarm_uart_update_status(s); |
| 1168 | strongarm_uart_update_int_status(s); |
| 1169 | return ret; |
| 1170 | } |
| 1171 | return 0; |
| 1172 | |
| 1173 | case UTSR0: |
| 1174 | return s->utsr0; |
| 1175 | |
| 1176 | case UTSR1: |
| 1177 | return s->utsr1; |
| 1178 | |
| 1179 | default: |
| 1180 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1181 | "%s: Bad uart register read 0x"HWADDR_FMT_plx"\n", |
| 1182 | __func__, addr); |
| 1183 | return 0; |
| 1184 | } |
| 1185 | } |
| 1186 | |
| 1187 | static void strongarm_uart_write(void *opaque, hwaddr addr, |
| 1188 | uint64_t value, unsigned size) |
| 1189 | { |
| 1190 | StrongARMUARTState *s = opaque; |
| 1191 | |
| 1192 | switch (addr) { |
| 1193 | case UTCR0: |
| 1194 | s->utcr0 = value & 0x7f; |
| 1195 | strongarm_uart_update_parameters(s); |
| 1196 | break; |
| 1197 | |
| 1198 | case UTCR1: |
| 1199 | s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); |
| 1200 | strongarm_uart_update_parameters(s); |
| 1201 | break; |
| 1202 | |
| 1203 | case UTCR2: |
| 1204 | s->brd = (s->brd & 0xf00) | (value & 0xff); |
| 1205 | strongarm_uart_update_parameters(s); |
| 1206 | break; |
| 1207 | |
| 1208 | case UTCR3: |
| 1209 | s->utcr3 = value & 0x3f; |
| 1210 | if ((s->utcr3 & UTCR3_RXE) == 0) { |
| 1211 | s->rx_len = 0; |
| 1212 | } |
| 1213 | if ((s->utcr3 & UTCR3_TXE) == 0) { |
| 1214 | s->tx_len = 0; |
| 1215 | } |
| 1216 | strongarm_uart_update_status(s); |
| 1217 | strongarm_uart_update_int_status(s); |
| 1218 | break; |
| 1219 | |
| 1220 | case UTDR: |
| 1221 | if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { |
| 1222 | s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; |
| 1223 | s->tx_len++; |
| 1224 | strongarm_uart_update_status(s); |
| 1225 | strongarm_uart_update_int_status(s); |
| 1226 | if (s->tx_len == 1) { |
| 1227 | strongarm_uart_tx(s); |
| 1228 | } |
| 1229 | } |
| 1230 | break; |
| 1231 | |
| 1232 | case UTSR0: |
| 1233 | s->utsr0 = s->utsr0 & ~(value & |
| 1234 | (UTSR0_REB | UTSR0_RBB | UTSR0_RID)); |
| 1235 | strongarm_uart_update_int_status(s); |
| 1236 | break; |
| 1237 | |
| 1238 | default: |
| 1239 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1240 | "%s: Bad uart register write 0x"HWADDR_FMT_plx"\n", |
| 1241 | __func__, addr); |
| 1242 | } |
| 1243 | } |
| 1244 | |
| 1245 | static const MemoryRegionOps strongarm_uart_ops = { |
| 1246 | .read = strongarm_uart_read, |
| 1247 | .write = strongarm_uart_write, |
| 1248 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 1249 | }; |
| 1250 | |
| 1251 | static void strongarm_uart_init(Object *obj) |
| 1252 | { |
| 1253 | StrongARMUARTState *s = STRONGARM_UART(obj); |
| 1254 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
| 1255 | |
| 1256 | memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, |
| 1257 | "uart", 0x10000); |
| 1258 | sysbus_init_mmio(dev, &s->iomem); |
| 1259 | sysbus_init_irq(dev, &s->irq); |
| 1260 | } |
| 1261 | |
| 1262 | static void strongarm_uart_realize(DeviceState *dev, Error **errp) |
| 1263 | { |
| 1264 | StrongARMUARTState *s = STRONGARM_UART(dev); |
| 1265 | |
| 1266 | s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
| 1267 | strongarm_uart_rx_to, |
| 1268 | s); |
| 1269 | s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); |
| 1270 | qemu_chr_fe_set_handlers(&s->chr, |
| 1271 | strongarm_uart_can_receive, |
| 1272 | strongarm_uart_receive, |
| 1273 | strongarm_uart_event, |
| 1274 | NULL, s, NULL, true); |
| 1275 | } |
| 1276 | |
| 1277 | static void strongarm_uart_reset(DeviceState *dev) |
| 1278 | { |
| 1279 | StrongARMUARTState *s = STRONGARM_UART(dev); |
| 1280 | |
| 1281 | s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ |
| 1282 | s->brd = 23; /* 9600 */ |
| 1283 | /* enable send & recv - this actually violates spec */ |
| 1284 | s->utcr3 = UTCR3_TXE | UTCR3_RXE; |
| 1285 | |
| 1286 | s->rx_len = s->tx_len = 0; |
| 1287 | |
| 1288 | strongarm_uart_update_parameters(s); |
| 1289 | strongarm_uart_update_status(s); |
| 1290 | strongarm_uart_update_int_status(s); |
| 1291 | } |
| 1292 | |
| 1293 | static int strongarm_uart_post_load(void *opaque, int version_id) |
| 1294 | { |
| 1295 | StrongARMUARTState *s = opaque; |
| 1296 | |
| 1297 | strongarm_uart_update_parameters(s); |
| 1298 | strongarm_uart_update_status(s); |
| 1299 | strongarm_uart_update_int_status(s); |
| 1300 | |
| 1301 | /* tx and restart timer */ |
| 1302 | if (s->tx_len) { |
| 1303 | strongarm_uart_tx(s); |
| 1304 | } |
| 1305 | |
| 1306 | /* restart rx timeout timer */ |
| 1307 | if (s->rx_len) { |
| 1308 | timer_mod(s->rx_timeout_timer, |
| 1309 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); |
| 1310 | } |
| 1311 | |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | static const VMStateDescription vmstate_strongarm_uart_regs = { |
| 1316 | .name = "strongarm-uart", |
| 1317 | .version_id = 0, |
| 1318 | .minimum_version_id = 0, |
| 1319 | .post_load = strongarm_uart_post_load, |
| 1320 | .fields = (const VMStateField[]) { |
| 1321 | VMSTATE_UINT8(utcr0, StrongARMUARTState), |
| 1322 | VMSTATE_UINT16(brd, StrongARMUARTState), |
| 1323 | VMSTATE_UINT8(utcr3, StrongARMUARTState), |
| 1324 | VMSTATE_UINT8(utsr0, StrongARMUARTState), |
| 1325 | VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8), |
| 1326 | VMSTATE_UINT8(tx_start, StrongARMUARTState), |
| 1327 | VMSTATE_UINT8(tx_len, StrongARMUARTState), |
| 1328 | VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12), |
| 1329 | VMSTATE_UINT8(rx_start, StrongARMUARTState), |
| 1330 | VMSTATE_UINT8(rx_len, StrongARMUARTState), |
| 1331 | VMSTATE_BOOL(wait_break_end, StrongARMUARTState), |
| 1332 | VMSTATE_END_OF_LIST(), |
| 1333 | }, |
| 1334 | }; |
| 1335 | |
| 1336 | static const Property strongarm_uart_properties[] = { |
| 1337 | DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), |
| 1338 | }; |
| 1339 | |
| 1340 | static void strongarm_uart_class_init(ObjectClass *klass, const void *data) |
| 1341 | { |
| 1342 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1343 | |
| 1344 | dc->desc = "StrongARM UART controller"; |
| 1345 | device_class_set_legacy_reset(dc, strongarm_uart_reset); |
| 1346 | dc->vmsd = &vmstate_strongarm_uart_regs; |
| 1347 | device_class_set_props(dc, strongarm_uart_properties); |
| 1348 | dc->realize = strongarm_uart_realize; |
| 1349 | } |
| 1350 | |
| 1351 | static const TypeInfo strongarm_uart_info = { |
| 1352 | .name = TYPE_STRONGARM_UART, |
| 1353 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1354 | .instance_size = sizeof(StrongARMUARTState), |
| 1355 | .instance_init = strongarm_uart_init, |
| 1356 | .class_init = strongarm_uart_class_init, |
| 1357 | }; |
| 1358 | |
| 1359 | /* Synchronous Serial Ports */ |
| 1360 | |
| 1361 | #define TYPE_STRONGARM_SSP "strongarm-ssp" |
| 1362 | OBJECT_DECLARE_SIMPLE_TYPE(StrongARMSSPState, STRONGARM_SSP) |
| 1363 | |
| 1364 | struct StrongARMSSPState { |
| 1365 | SysBusDevice parent_obj; |
| 1366 | |
| 1367 | MemoryRegion iomem; |
| 1368 | qemu_irq irq; |
| 1369 | SSIBus *bus; |
| 1370 | |
| 1371 | uint16_t sscr[2]; |
| 1372 | uint16_t sssr; |
| 1373 | |
| 1374 | uint16_t rx_fifo[8]; |
| 1375 | uint8_t rx_level; |
| 1376 | uint8_t rx_start; |
| 1377 | }; |
| 1378 | |
| 1379 | #define SSCR0 0x60 /* SSP Control register 0 */ |
| 1380 | #define SSCR1 0x64 /* SSP Control register 1 */ |
| 1381 | #define SSDR 0x6c /* SSP Data register */ |
| 1382 | #define SSSR 0x74 /* SSP Status register */ |
| 1383 | |
| 1384 | /* Bitfields for above registers */ |
| 1385 | #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) |
| 1386 | #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) |
| 1387 | #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) |
| 1388 | #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) |
| 1389 | #define SSCR0_SSE (1 << 7) |
| 1390 | #define SSCR0_DSS(x) (((x) & 0xf) + 1) |
| 1391 | #define SSCR1_RIE (1 << 0) |
| 1392 | #define SSCR1_TIE (1 << 1) |
| 1393 | #define SSCR1_LBM (1 << 2) |
| 1394 | #define SSSR_TNF (1 << 2) |
| 1395 | #define SSSR_RNE (1 << 3) |
| 1396 | #define SSSR_TFS (1 << 5) |
| 1397 | #define SSSR_RFS (1 << 6) |
| 1398 | #define SSSR_ROR (1 << 7) |
| 1399 | #define SSSR_RW 0x0080 |
| 1400 | |
| 1401 | static void strongarm_ssp_int_update(StrongARMSSPState *s) |
| 1402 | { |
| 1403 | int level = 0; |
| 1404 | |
| 1405 | level |= (s->sssr & SSSR_ROR); |
| 1406 | level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); |
| 1407 | level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); |
| 1408 | qemu_set_irq(s->irq, level); |
| 1409 | } |
| 1410 | |
| 1411 | static void strongarm_ssp_fifo_update(StrongARMSSPState *s) |
| 1412 | { |
| 1413 | s->sssr &= ~SSSR_TFS; |
| 1414 | s->sssr &= ~SSSR_TNF; |
| 1415 | if (s->sscr[0] & SSCR0_SSE) { |
| 1416 | if (s->rx_level >= 4) { |
| 1417 | s->sssr |= SSSR_RFS; |
| 1418 | } else { |
| 1419 | s->sssr &= ~SSSR_RFS; |
| 1420 | } |
| 1421 | if (s->rx_level) { |
| 1422 | s->sssr |= SSSR_RNE; |
| 1423 | } else { |
| 1424 | s->sssr &= ~SSSR_RNE; |
| 1425 | } |
| 1426 | /* TX FIFO is never filled, so it is always in underrun |
| 1427 | condition if SSP is enabled */ |
| 1428 | s->sssr |= SSSR_TFS; |
| 1429 | s->sssr |= SSSR_TNF; |
| 1430 | } |
| 1431 | |
| 1432 | strongarm_ssp_int_update(s); |
| 1433 | } |
| 1434 | |
| 1435 | static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, |
| 1436 | unsigned size) |
| 1437 | { |
| 1438 | StrongARMSSPState *s = opaque; |
| 1439 | uint32_t retval; |
| 1440 | |
| 1441 | switch (addr) { |
| 1442 | case SSCR0: |
| 1443 | return s->sscr[0]; |
| 1444 | case SSCR1: |
| 1445 | return s->sscr[1]; |
| 1446 | case SSSR: |
| 1447 | return s->sssr; |
| 1448 | case SSDR: |
| 1449 | if (~s->sscr[0] & SSCR0_SSE) { |
| 1450 | return 0xffffffff; |
| 1451 | } |
| 1452 | if (s->rx_level < 1) { |
| 1453 | trace_strongarm_ssp_read_underrun(); |
| 1454 | return 0xffffffff; |
| 1455 | } |
| 1456 | s->rx_level--; |
| 1457 | retval = s->rx_fifo[s->rx_start++]; |
| 1458 | s->rx_start &= 0x7; |
| 1459 | strongarm_ssp_fifo_update(s); |
| 1460 | return retval; |
| 1461 | default: |
| 1462 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1463 | "%s: Bad ssp register read 0x"HWADDR_FMT_plx"\n", |
| 1464 | __func__, addr); |
| 1465 | break; |
| 1466 | } |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
| 1470 | static void strongarm_ssp_write(void *opaque, hwaddr addr, |
| 1471 | uint64_t value, unsigned size) |
| 1472 | { |
| 1473 | StrongARMSSPState *s = opaque; |
| 1474 | |
| 1475 | switch (addr) { |
| 1476 | case SSCR0: |
| 1477 | s->sscr[0] = value & 0xffbf; |
| 1478 | if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { |
| 1479 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Wrong data size: %i bits\n", |
| 1480 | __func__, (int)SSCR0_DSS(value)); |
| 1481 | } |
| 1482 | if (!(value & SSCR0_SSE)) { |
| 1483 | s->sssr = 0; |
| 1484 | s->rx_level = 0; |
| 1485 | } |
| 1486 | strongarm_ssp_fifo_update(s); |
| 1487 | break; |
| 1488 | |
| 1489 | case SSCR1: |
| 1490 | s->sscr[1] = value & 0x2f; |
| 1491 | if (value & SSCR1_LBM) { |
| 1492 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1493 | "%s: Attempt to use SSP LBM mode\n", |
| 1494 | __func__); |
| 1495 | } |
| 1496 | strongarm_ssp_fifo_update(s); |
| 1497 | break; |
| 1498 | |
| 1499 | case SSSR: |
| 1500 | s->sssr &= ~(value & SSSR_RW); |
| 1501 | strongarm_ssp_int_update(s); |
| 1502 | break; |
| 1503 | |
| 1504 | case SSDR: |
| 1505 | if (SSCR0_UWIRE(s->sscr[0])) { |
| 1506 | value &= 0xff; |
| 1507 | } else |
| 1508 | /* Note how 32bits overflow does no harm here */ |
| 1509 | value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; |
| 1510 | |
| 1511 | /* Data goes from here to the Tx FIFO and is shifted out from |
| 1512 | * there directly to the slave, no need to buffer it. |
| 1513 | */ |
| 1514 | if (s->sscr[0] & SSCR0_SSE) { |
| 1515 | uint32_t readval; |
| 1516 | if (s->sscr[1] & SSCR1_LBM) { |
| 1517 | readval = value; |
| 1518 | } else { |
| 1519 | readval = ssi_transfer(s->bus, value); |
| 1520 | } |
| 1521 | |
| 1522 | if (s->rx_level < 0x08) { |
| 1523 | s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; |
| 1524 | } else { |
| 1525 | s->sssr |= SSSR_ROR; |
| 1526 | } |
| 1527 | } |
| 1528 | strongarm_ssp_fifo_update(s); |
| 1529 | break; |
| 1530 | |
| 1531 | default: |
| 1532 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1533 | "%s: Bad ssp register write 0x"HWADDR_FMT_plx"\n", |
| 1534 | __func__, addr); |
| 1535 | break; |
| 1536 | } |
| 1537 | } |
| 1538 | |
| 1539 | static const MemoryRegionOps strongarm_ssp_ops = { |
| 1540 | .read = strongarm_ssp_read, |
| 1541 | .write = strongarm_ssp_write, |
| 1542 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 1543 | }; |
| 1544 | |
| 1545 | static int strongarm_ssp_post_load(void *opaque, int version_id) |
| 1546 | { |
| 1547 | StrongARMSSPState *s = opaque; |
| 1548 | |
| 1549 | strongarm_ssp_fifo_update(s); |
| 1550 | |
| 1551 | return 0; |
| 1552 | } |
| 1553 | |
| 1554 | static void strongarm_ssp_init(Object *obj) |
| 1555 | { |
| 1556 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 1557 | DeviceState *dev = DEVICE(sbd); |
| 1558 | StrongARMSSPState *s = STRONGARM_SSP(dev); |
| 1559 | |
| 1560 | sysbus_init_irq(sbd, &s->irq); |
| 1561 | |
| 1562 | memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, |
| 1563 | "ssp", 0x1000); |
| 1564 | sysbus_init_mmio(sbd, &s->iomem); |
| 1565 | |
| 1566 | s->bus = ssi_create_bus(dev, "ssi"); |
| 1567 | } |
| 1568 | |
| 1569 | static void strongarm_ssp_reset(DeviceState *dev) |
| 1570 | { |
| 1571 | StrongARMSSPState *s = STRONGARM_SSP(dev); |
| 1572 | |
| 1573 | s->sssr = 0x03; /* 3 bit data, SPI, disabled */ |
| 1574 | s->rx_start = 0; |
| 1575 | s->rx_level = 0; |
| 1576 | } |
| 1577 | |
| 1578 | static const VMStateDescription vmstate_strongarm_ssp_regs = { |
| 1579 | .name = "strongarm-ssp", |
| 1580 | .version_id = 0, |
| 1581 | .minimum_version_id = 0, |
| 1582 | .post_load = strongarm_ssp_post_load, |
| 1583 | .fields = (const VMStateField[]) { |
| 1584 | VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2), |
| 1585 | VMSTATE_UINT16(sssr, StrongARMSSPState), |
| 1586 | VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8), |
| 1587 | VMSTATE_UINT8(rx_start, StrongARMSSPState), |
| 1588 | VMSTATE_UINT8(rx_level, StrongARMSSPState), |
| 1589 | VMSTATE_END_OF_LIST(), |
| 1590 | }, |
| 1591 | }; |
| 1592 | |
| 1593 | static void strongarm_ssp_class_init(ObjectClass *klass, const void *data) |
| 1594 | { |
| 1595 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1596 | |
| 1597 | dc->desc = "StrongARM SSP controller"; |
| 1598 | device_class_set_legacy_reset(dc, strongarm_ssp_reset); |
| 1599 | dc->vmsd = &vmstate_strongarm_ssp_regs; |
| 1600 | } |
| 1601 | |
| 1602 | static const TypeInfo strongarm_ssp_info = { |
| 1603 | .name = TYPE_STRONGARM_SSP, |
| 1604 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1605 | .instance_size = sizeof(StrongARMSSPState), |
| 1606 | .instance_init = strongarm_ssp_init, |
| 1607 | .class_init = strongarm_ssp_class_init, |
| 1608 | }; |
| 1609 | |
| 1610 | /* Main CPU functions */ |
| 1611 | StrongARMState *sa1110_init(const char *cpu_type) |
| 1612 | { |
| 1613 | StrongARMState *s; |
| 1614 | int i; |
| 1615 | |
| 1616 | s = g_new0(StrongARMState, 1); |
| 1617 | |
| 1618 | if (strncmp(cpu_type, "sa1110", 6)) { |
| 1619 | error_report("Machine requires a SA1110 processor."); |
| 1620 | exit(1); |
| 1621 | } |
| 1622 | |
| 1623 | s->cpu = ARM_CPU(cpu_create(cpu_type)); |
| 1624 | |
| 1625 | s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, |
| 1626 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), |
| 1627 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), |
| 1628 | NULL); |
| 1629 | |
| 1630 | sysbus_create_varargs("pxa25x-timer", 0x90000000, |
| 1631 | qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), |
| 1632 | qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), |
| 1633 | qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), |
| 1634 | qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), |
| 1635 | NULL); |
| 1636 | |
| 1637 | sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000, |
| 1638 | qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); |
| 1639 | |
| 1640 | s->gpio = strongarm_gpio_init(0x90040000, s->pic); |
| 1641 | |
| 1642 | s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); |
| 1643 | |
| 1644 | for (i = 0; sa_serial[i].io_base; i++) { |
| 1645 | DeviceState *dev = qdev_new(TYPE_STRONGARM_UART); |
| 1646 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 1647 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 1648 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, |
| 1649 | sa_serial[i].io_base); |
| 1650 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, |
| 1651 | qdev_get_gpio_in(s->pic, sa_serial[i].irq)); |
| 1652 | } |
| 1653 | |
| 1654 | s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, |
| 1655 | qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); |
| 1656 | s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); |
| 1657 | |
| 1658 | return s; |
| 1659 | } |
| 1660 | |
| 1661 | static void strongarm_register_types(void) |
| 1662 | { |
| 1663 | type_register_static(&strongarm_pic_info); |
| 1664 | type_register_static(&strongarm_rtc_sysbus_info); |
| 1665 | type_register_static(&strongarm_gpio_info); |
| 1666 | type_register_static(&strongarm_ppc_info); |
| 1667 | type_register_static(&strongarm_uart_info); |
| 1668 | type_register_static(&strongarm_ssp_info); |
| 1669 | } |
| 1670 | |
| 1671 | type_init(strongarm_register_types) |